Chapter 6: Input / Output Organization

6.1 External Devices

The input/output subsystem of a computer, referred to as I/O, provides an efficient mode of
communication between the central system and the outside environment. Programs and data must be
entered into computer memory for processing and results obtained from computations must be recorded
or displayed for users. A computer serves no useful purpose without the ability to receive information
from an outside source and to transmit results in a meaningful form.
I/O operations are accomplished through a wide assortment of external devices that provide a means of
exchanging data between the external environment and the computer. An external device attaches to the
computer by a link to an I/O module as shown in figure below. The link is used to exchange control,
status, and data between the I/O module and the external device. An external device connected to an I/O
module also called Interface is often referred to as a peripheral device or simply a peripheral.
6.2 Classification of External devices
External devices broadly can be classified into three categories:
Human readable: suitable for communicating with the computer user. Examples: Screen, keyboard,
video display terminals (VDT) and printers.
Machine readable: suitable for communicating with equipment’s. Examples: magnetic disk & tapes
systems, Monitoring and control, sensors and actuators which are used in robotics.
Communication: These devices allow a computer to exchange data with remote devices, which may be
machine readable or human readable. Examples: Modem, Network Interface Card (NIC)

Figure 6.1: Connection of CPU,I/O modules and Peripheral Devices

6.3 Input/output Problems

 Wide variety of peripherals and
 Delivering different amounts of data per second
 Work at different speeds
 Send/receive data in different formats.
 All slower than CPU and RAM.
 Hence I/O modules are used as a solution.
 6.4 Input/output Module
It is the entity within a computer that is responsible for the control of one or more external devices
 Interface to CPU and memory
 Interface to one or more peripherals
6.5 I/O Module Function
The major functions or requirements for an I/O module fall into the following five categories.
 Control & Timing
 CPU Communication
 Device Communication
 Data Buffering
 Error Detection
During any period of time, the CPU may communicate with one or more external devices in
unpredictable patterns on the program’s need for I/O. The internal resources, main memory and the CPU
must be shared among number of activities including handling data I/O. Thus the I/O device includes a
control and timing requirement to coordinate the flow of traffic between internal resources and external
devices to the CPU. Thus CPU might involve in sequence of operations like:
 CPU checks I/O module device status
 I/O module returns device status
 If ready, CPU requests data transfer
 I/O module gets data from device
 I/O module transfers data to CPU variations for output, DMA, etc.
I/O module must have the capability to engage in communication with the CPU and external device. Thus
CPU communication involves:
1. Command decoding: The I/O module accepts commands from the CPU carried on the control bus.
2. Data: data are exchanged between the CPU and the I/O module over data bus.
3. Status reporting: Because peripherals are slow it is important to know the status of I/O device. I/O
module can report with the status signals common used status signals are BUSY or READY. Various
other status signals may be used to report various error conditions.
4. Address recognition: just as each memory word has an address, there is address associated with
every I/O device. Thus I/O module must be recognized with a unique address for each peripheral it
controls.
The I/O module must also be able to perform device communication. This communication involves
commands, status information, and data. Some of the essentials tasks are listed below:
I. Error detection: I/O module is often responsible for error detection and subsequently reporting errors to
the CPU.
II. Data buffering: the transfer rate into and out of main memory or CPU is quite high, and the rate is
much lower for most of the peripherals. The data is buffered in the I/O module and then sent to the
peripheral device at its rate. In the opposite direction data are buffered so as not to tie up the memory in
a slow transfer operation. Thus I/O module must be able to operate at both device and memory speeds.
 6.6 Input / Output Techniques (Data transfer mode)
Three techniques are possible for I/O operations or data transfer mode. They are:
1. Programmed I/O
2. Interrupt Driven
3. Direct Memory Access (DMA)
6.7 Programmed I/O
With Programmed I/O, data are exchanged between the CPU and the I/O module. The CPU executes a
program that gives it direct control of the I/O operation, including sensing device status, sending a read
or write command and transferring data. When CPU issues a command to I/O module, it must wait until
I/O operation is complete. If the CPU is faster than I/O module, there is wastage of CPU time.
The I/O module does not take any further action to alert CPU. That is, it doesn’t interrupt CPU. Hence it
is the responsibility of the CPU to periodically check the status of the I/O module until it finds that the
operation is complete.
The sequences of actions that take place with programmed I/O are:
1) CPU requests I/O operation
2) I/O module performs operation
3) I/O module sets status bits
4) CPU checks status bits periodically
5) I/O module does not inform CPU directly
6) I/O module does not interrupt CPU
7) CPU may wait or come back later
6.7.1 I/O commands
To execute an I/O related instruction, the CPU issues an address, specifying the particular I/O module and
external device and an I/O command. Four types of I/O commands can be received by the I/O module
when it is addressed by the CPU. They are:
1. A control command: is used to activate a peripheral and tell what to do. Example: a magnetic tape may
be directed to rewind or move forward a record.
2. A test command: is used to test various status conditions associated with an I/O module and its
peripherals. The CPU wants to know the interested peripheral for use. It also wants to know the most
recent I/O operation is completed and if any errors have occurred.
3.A read command: it causes the I/O module to obtain an item of data from the peripheral and place it in
an internal buffer. The CPU then gets the data items by requesting I/O module to place it on the data bus.
4. A write command: it causes the I/O module to take an item of data from the data bus and subsequently
transmit the data item to the peripheral.
6.8 I/O Mapping
When the CPU, main memory, and I/O module share a common bus two modes of addressing are
possible.
Memory mapped I/O
 Devices and memory share an address space
 I/O looks just like memory read/write
  No special commands for I/O
 Large selection of memory access commands available
Isolated I/O
 Separate address spaces
 Need I/O or memory select lines
 Special commands for I/O and Limited set
6. 9 Interrupt Driven I/O
Using Program-controlled I/O requires continuous involvement of the processor in the I/O activities. It is
desirable to avoid wasting processor execution time. An alternative is for the CPU to issue an I/O
command to a module and then go on other work. The I/O module will then interrupt the CPU requesting
service when it is ready to exchange data with the CPU. The CPU will then execute the data transfer and
then resumes its former processing. Based on the use of interrupts, this technique improves the utilization
of the processor.
With Interrupt driven I/O, the CPU issues a command to I/O module and it does not wait until I/O
operation is complete but instead continues to execute other instructions. When I/O module has
completed its work, it interrupts the CPU.
An interrupt is more than a simple mechanism for coordinating I/O transfers. In a general sense,
interrupts enable transfer of control from one program to another to be initiated by an event that is
external to a computer. Execution of the interrupted program resumes after completion of execution of
the interrupt service routine. The concept of interrupts is useful in operating systems and in many control
applications where processing of certain routines has to be accurately timed relative to the external
events.
Using Interrupt Driven I/O technique CPU issues read command. I/O module gets data from peripheral
while CPU does other work and I/O module interrupts CPU checks the status if no error that is the device
is ready then CPU requests data and I/O module transfers data. Thus, CPU reads the data and stores it in
the main memory.
6.10 Basic concepts of an Interrupt
An interrupt is an exception condition in a computer system caused by an event external to the CPU.
Interrupts are commonly used in I/O operations by a device interface (or controller) to notify the CPU
that it has completed an I/O operation. An interrupt is indicated by a signal sent by the device interface to
the CPU via an interrupt request line (on an external bus). This signal notifies the CPU that the signalling
interface needs to be serviced. The signal is held until the CPU acknowledges or otherwise services the
interface from which the interrupt originated.
6. 11 Response of CPU to an Interrupt
The CPU checks periodically to determine if an interrupt signal is pending. This check is usually done at
the end of each instruction, although some modern machines allow for interrupts to be checked for
several times during the execution of very long instructions. When the CPU detects an interrupt, it then
saves its current state (at least the PC and the Processor Status Register containing condition codes); this
state information is usually saved in memory. After the interrupt has been serviced, this state information
is restored in the CPU and the previously executing software resumes execution as if nothing had
happened.

Figure 6.2: CPU Interrupts

6.12 Direct Memory Access (DMA)
Interrupt driven and programmed I/O require active CPU intervention. Transfer rate is limited. CPU is
tied up. DMA is the solution for these problems. Direct Memory Access is capabilities provided by some
computer bus architectures that allow data to be sent directly from an attached device (such as a disk
drive) to the memory on the computer’s motherboard. The microprocessor (CPU) is freed from
involvement with the data transfer, thus speeding up overall computer operation.

Figure 6.3: Direct Memory Access (DMA)

When the CPU wishes to read or write a block of data, it issues a command to the DMA module and
gives following information: CPU tells DMA controller:
 Whether to read or write
 Device address
 Starting address of memory block for data
 Amount of data to be transferred
The CPU carries on with other work. Thus DMA controller steals the CPU‟s work of I/O operation. The
DMA module transfers the entire block of data, one word at a time, directly to or from memory, without
going through CPU. When the transfer is complete. DMA controller sends interrupt when finished.
Thus CPU is involved only at the beginning and at the end of the transfer.
6. 13 DMA Configurations
The DMA mechanism can be configured in variety of ways. Some of the common configurations are
discussed here.
Single Bus Detached DMA: In this configuration all modules share the same system bus. The block
diagram of single bus detached DMA is as shown in Figure 6.4. The DMA module that is mimicking the
CPU uses the programmed I/O to exchange the data between the memory and the I/O module through the
DMA module. This scheme may be inexpensive but is clearly inefficient. The features of this
configuration are:
 Single Bus, Detached DMA controller
 Each transfer uses bus twice
 I/O to DMA then DMA to memory
 CPU is suspended twice

Figure 6.4: Single Bus Detached DMA

Single Bus, integrated DMA: Here, there is a path between DMA module and one or more I/O modules
that do not include the system bus. The block diagram of single bus Integrated DMA is as shown in
Figure 6.5. The DMA logic can actually be considered as a part of an I/O module or there may be a
separate module that controls one more I/O modules.

Figure 6.5: Single

Bus, integrated DMA
The features of this configuration can be considered as:
 Single Bus, Integrated DMA controller
 Controller may support >1 device
 Each transfer uses the bus once
 DMA to memory
 CPU is suspended once
DMA using an I/O bus: One further step of the concept of integrated DMA is to connect I/O modules to
DMA controller using a separate bus called I/O bus. This reduces the number of I/O interfaces in the
DMA module to one and provides for an easily expandable configuration. The block diagram of DMA
using I/O bus is as shown in Figure 6.6. Here the system bus that the DMA shares with CPU and main
memory is used by DMA module only to exchange data with memory. And the exchange of data between
the DMA module and the I/O modules takes place off the system bus that is through the I/O bus.

Figure 6. 6: DMA using an

I/O bus

The features of this configuration are:

 Separate I/O Bus
 Bus supports all DMA enabled devices
 Each transfer uses bus once
 DMA to memory
 CPU is suspended once
With both Programmed I/O and Interrupt driven I/O the CPU is responsible for extracting data from
main memory for output and storing data in main memory for input. Table indicates the relationship
among the three techniques.

Advantages of DMA

DMA has several advantages over polling and interrupts.

 DMA is fast because a dedicated piece of hardware transfers data from one computer location
to another and only one or two bus read/write cycles are required per piece of data transferred
 In addition, DMA is usually required to achieve maximum data transfer speed, and thus is
useful for high speed data acquisition devices.
 DMA also minimizes latency in servicing a data acquisition device because the dedicated
hardware responds more quickly than interrupts and transfer time is short. Minimizing latency
reduces the amount of temporary storage (memory) required on an I/O device.
 DMA also off-loads the processor, which means the processor does not have to execute any
instructions to transfer data. Therefore, the processor is not used for handling the data transfer
activity and is available for other processing activity. Also, in systems where the processor
primarily operates out of its cache, data transfer is actually occurring in parallel, thus
increasing overall system utilization.