Lehrstuhl für Schaltungsentwurf

Technische Universität München • Arcisstraße 21 • 80333 München

Tel: 089/289-22929 • Fax: 089/289-22938
Email: [email protected]

Prof. Dr.-Ing. Ralf Brederlow

LAB CMOS analog-to-digital

converters

LSE, WiSe 2021

Prof. Dr.-Ing. Ralf Brederlow
M.Sc. Tauseef Siddiqui
M.Sc. Vartika Verma
B.Sc Tobias Chlan
LAB Introduction
This lab gives you an opportunity to get a deeper insight into the circuit design process
and to develop an analog circuit on your own. This handout explains the basic boundary
conditions, describes the circuits to be designed, illustrates the main steps to succeed in
their design, and gives the specifications that the circuit has to fulfill in the different
design steps.

Over the course of this lab, you will design a circuit/system that operates according to the
given specifications. You will have to choose and size the transistors and the circuits in
order to meet these requirements, while you will characterize the circuit through
simulation. Due to time constraints, the final step towards silicon manufacturing, the
layout, is omitted.

The design of a circuit in CMOS technology is more complex than the theory you already
know from lectures. Furthermore, there are many more degrees of freedom in the design
compared to what you have learned in the lectures. Therefore, you are encouraged to
come to discuss with us potential difficulties during the consultation hours. Additionally,
the relevant materials will be available on Moodle for reference.

To get the credit points, you will have to report your progress during the semester –
details will be given later in this report. For all tasks, a suitable mixture of hand
calculations and transistor level simulations is mandatory to let your design meet the
circuit specifications. A ’brute force’ approach will not lead to a satisfactory design within
a reasonable time and we recommend following the procedures described below.

Task: 2nd Order 1-Bit Continuous time Σ∆-ADC*

In this lab, you will design a 2nd order CT Σ∆-ADC able to process signals from
system level to circuit level. This lab will have an emphasis on signal processing
and system level design.

*The digital filtering of the output has been omitted due to time constraints.

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 Rules and Suggestions in the Labs:
1. Deliverables:

• A “Design Report” comprising of 4 parts should be handed in. It has to be

properly formatted and written such that a reader familiar with the topic, but
not necessarily an expert can understand and follow the discussed topics.
• The first part should be uploaded on Moodle by 14.11.2021, the second part
by 12.12.2021, the third part by 02.01.2022 and the last part by 30.01.2022.
• A 15-minute final presentation will take place between February 7th and
February 11th, where each group shows their final results.
• The final presentation has to be uploaded in Moodle one day before the
presentation.
• Your Simulink model, any MATLAB scripts used, HDL code (if applicable), and
the Cadence schematics along with the ADE states used to simulate your
results; all these should be delivered when the relevant section of the report is
due.

2. Teamwork: Each group will have 2 members. Please make sure you are in good
relationship and achieve the final goal together. The division of labour is
determined by each group themselves.

3. Lab usage: The lab room (N4303) is open Monday to Friday during office hours
(9:00 - 18:00). Please do not shutdown the computers after you finish your work,
since they are also used by others. So just log off. For security purposes, these
machines will not read USB drives.

4. Grading: The final report containing all submissions and the final presentation are
graded, not only in terms of its content, but also considering their quality and
clarity.

Reference Books
D.A. Johns; K. Martin, Analog Integrated Circuit Design, Wiley, 1997
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001
R. Schreier; G.C. Temes, Understanding Delta-Sigma Data Converters, IEEE Press, 2005
S.R. Norsworthy; R. Schreier, Delta-Sigma Data Converters, IEEE Press, 1997
A.V. Oppenheim; A.S. Willsky, Signals and Systems, Prentice Hall, 1999
R.J. Baker; H.W. Li; D.E. Boyce, CMOS, Circuit Design, Layout and Simulation, Wiley, 1997
R. Gregorian; G.C. Temes, Analog MOS Integrated Circuits For Signal Processing, Wiley, 1986
S.J. Orfanidis, Introduction to Signal Processing, Prentice Hall, 1998

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A 2nd Order CT Σ∆ Modulator
Problem for system design
In this LAB, the understanding of Σ∆ modulators shall be deepened. All questions can be
answered by studying the literature and making simulations with MATLAB/Simulink and
Cadence.

The ADC should be of second order with a 1-bit quantizer.

The circuit has to meet the specifications given below:

Input voltage range ±500mV

Signal Bandwidth 100KHz
Supply voltage (Vdd) 1.8V
Ground voltage (Vgnd) 0.0V
Required SNR 90dB

The circuit will be designed in a 45nm n-well technology. The available circuit
components are n-MOSFET and p-MOSFET transistors, parasitic bipolar pnp transistors,
capacitors and resistors.

The MOSFET devices are defined in the gpdk045 CMOS

! technology library. The library element nmos2V
corresponds to the n-MOSFET and pmos2V to the p-
MOSFET. The minimum channel length is 150 nm, and the
minimum width is 320 nm.

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Task 1: Concept and Theories (Deadline - 14.11.2021)

(a) What is the difference between a Σ∆ ADC and a Nyquist rate ADC? Which
applications are best suited for a Σ∆ ADC and why?
(b) What is the function of a Σ∆ modulator within a Σ∆ ADC?
(c) Sketch the signal block diagram for both 1st and 2nd order Σ∆ modulators.
Describe each of the functional blocks in the diagrams. What is the NTF and
STF of these modulators.
(d) What is an idle tone? What is the relationship between idle tones and the
order of a Σ∆ modulator? How can the effects of these tones be removed?
(e) What is the Discrete Fourier Transform? What is the equation that defines
it?
(f) MATLAB does not provide a DFT function; instead it provides the similar
function FFT. What is the relationship between these two functions?
(g) Briefly explain what a ‘window function’ is. Why is it used and how does it
affect the results?
(h) Determine the minimum required OSR needed to implement the required
SNR with a 2nd order Σ∆ modulator. What would the OSR be in case on a 1st
order Σ∆ modulator?

Task 2: System development and analysis (Deadline - 12.12.2021)

(a) Use the Delta-Sigma toolbox in MATLAB to find the NTF and for both 1st and
2nd order modulators. Use the in-built commands to find the coefficients
needed for system level realization for both modulators. You can use any
topology of your choice.
(b) Prototype the both modulators in Simulink.
(c) Plot a sinusoidal input with the maximum possible amplitude and the resulting
output signal over time on the same graph. Describe and interpret your
results.
(d) Transform the output signal with the help of FFT in the frequency domain.
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Display the whole spectrum in the range from 0 ≤ 𝑓 ≤ 2 𝑓𝑠 , where fs is the
sample rate. Describe and interpret your result. Do this for both modulators.
(e) Does the obtained SNR meet the specifications? What circuit non-idealities are
neglected in Simulink right now? How would they affect the SNR in actual
circuit implementation?
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(f) Use a constant input signal 𝑉𝑖𝑛 = 𝑉 . Simulate the system and analyze the
3 𝑟𝑒𝑓
output signal in the time and frequency domain. What undesired effects occur
and why do they occur? Are they same in both 1st and 2nd order modulator?
Why or why not?

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 (g) Design and implement a strategy that reduces this problem. Test your
implementation via simulation and compare the results. What are the main
downsides to this solution?

Task 3: Implementation and testing using ideal components (Deadline –

02.01.2022)

You will now implement your Simulink prototype in Cadence Virtuoso in two
iterations. In the first iteration, you will create a circuit using (mostly) ideal
components. Please implement your design using a continuous-time approach.
You only need to do the following steps for a 2nd order modulator.

(a) The noise budget will set a limit on the resistor and capacitance in the circuit.
Determine the values such that the RMS noise is less than 0.5 LSB.
(b) What is the effective ENOB of this system? Plot the frequency spectrum and
calculate the SNR.
Verify that the circuit behaviour using the same input signals used in your Simulink
model.

Task 4: Implementation and real components (Deadline – 30.01.2022)

Once the circuit works with ideal components, work on the “transistor-level”
implementation. In this iteration, you should replace the ideal components with more
realistic components.

Design a quantizer using clocked comparator and an Opamp for the integrator,
summer etc.

(a) What non-ideal behaviour is introduced by using transistors instead of ideal

switches? Which type of switch (NMOS, transmission gate, etc...) is best suited
for this ADC?
(b) How does a finite gain of a real OpAmp affect the result? Calculate the minimum
DC-gain for the OpAmp to ensure an error of less than 0.5 LSB (ignoring the
thermal noise and finite bandwidth).
Apply the same input signals as before to your circuit. Compare these results to your
Simulink results. What is the final SNR of your circuit and where is the source of
this noise?

Please save the settings for all of the simulations you

! use for your report! Go to Session → Save State..., then
select Cellview at the top of the dialog. Then under
Cellview Options give a meaningful name for State and
a brief description of the test under Description.

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Relevant materials:
These are just for reference. Feel free to use any other circuits or topologies that
you like.

Clocked comparators:
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7130773

Delta-Sigma toolbox:
https://www.eecis.udel.edu/~vsaxena/courses/ece697A/docs/DSToolbox.pdf