COMBINATIONAL
CIRCUITS
Dr. József Sütő
EXCLUSIVE OR LOGIC
A B Y
0 0 0
0 1 1 ഥ+𝐀
𝐘 = 𝐀 ⊕ 𝐁 = 𝐀𝐁 ഥ𝐁
1 0 1
1 1 0
Some logic functions require an enormous amount
of hardware when built using two-level logic!
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EVEN PARITY GENERATOR
Exercise: Use logical gates to implement an even-parity code
generator for an original 4-bit code
Steps:
1. Create the truth table
2. From the truth table create a K-map
3. Find the logical equation
4. Determine the combinational circuit from the equation
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EVEN PARITY GENERATOR
Exercise: Use XOR gates to implement the even-parity code
generator.
4-bit code parity bit
4-bit code
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UNIVERSAL PROPERTY OF NAND GATE
NOT
• The NAND gate is a universal
gate because it can be used
to produce NOT, AND, OR, and
the NOR functions AN
D
• Dual symbols – De Morgan’s
theorem:
A O
Y
B R
A
Y
B
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UNIVERSAL PROPERTY OF NOR GATE
NOT
• The NOR gate is also a
universal gate because it
can be used to produce NOT,
AND, OR, and the NOR AN
functions D
• Dual symbols – De Morgan’s
theorem: O
R
A
Y
B
A
Y
B
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UNIVERSAL GATES EXAMPLE
Exercise: Implement both expressions with NAND logic
1. 𝐘 = 𝐀𝐁𝐂 + 𝐃𝐄
ഥ + 𝐄ത
2. 𝐘 = 𝐀𝐁𝐂 + 𝐃
1. Double Inversion Law
2. De Morgan’s Law
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UNIVERSAL GATES EXAMPLE
Exercise: Redraw the below logic diagram. The new circuit must
consist of AND, OR, and NOT symbols. Develop the output
expression for the new circuit
Rule: every connection
between a gate output
and a gate input is either
bubble to bubble or non
bubble to non bubble
ഥ+𝐁
𝐘= 𝐀 ഥ 𝐂+ 𝐃
ഥ + 𝐄ത 𝐅
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UNIVERSAL GATES EXAMPLE
Exercise: Redraw the below logic diagram. The new circuit must
consist of AND, OR, and NOT symbols. Develop the output expression
for the new circuit
ഥ𝐁
𝐘= 𝐀 ഥ+𝐂 𝐃
ഥ 𝐄ത + 𝐅 = 𝐀
ഥ𝐁ഥ+𝐂 𝐃
ഥ 𝐄ത + 𝐅
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MULTIPLEXER
• Multiplexer (MUX) • Implementation - Logic
• Selects between one of N inputs to gates
connect to output • SOP form: 𝐘 = 𝐃𝟎 𝐒ത + 𝐃𝟏 𝐒
• log2N-bit select input – control
input
• Example: S D1 D0 Y
2:1 Multiplexer 0 0 0 0
0 0 1 1
0 1 0 0 S Y
0 1 1 1 ≡ 0 D0
1 0 0 0 1 D1
1 0 1 0
1 1 0 1
1 1 1 1
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USING MUX AS A LOOK UP TABLE
A B Y
0 0 0
0 1 1
1 0 0
1 1 0
ഥ𝐁
𝐘=𝐀
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REDUCING THE SIZE OF MUX
• With a little cleverness we can cut the MUX size in half using
only a 2 N-1 –input MUX to perform any N input logic function
• The strategy is to provide one of the literals as well as 0’s and
1’s to the MUX data inputs
A B Y A Y
0 0 0
0 0
𝐘 = 𝐀𝐁 0 1 0
1 0 0 1 B
1 1 1
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COMBINATIONAL LOGIC WITH MUX
Exercise: Implement the function 𝐘 = 𝐀𝐁ഥ+𝐁ഥ 𝐂ത + 𝐀
ഥ 𝐁𝐂
a) With a 8:1 multiplexer
b) With a 4:1 multiplexer and an inverter
A B C Y
0 0 0 1
0 0 1 0 A B Y
0 1 0 0 0 0 Cത
0 1 1 1 ≡ 0 1 C
1 0 0 1 1 0 1
1 0 1 1 1 1 0
1 1 0 0
1 1 1 0
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A B C D Y
COMBINATIONAL LOGIC WITH MUX
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
A B C Y
0 0 1 1 0
0 0 0 0
Exercise: Use 8:1 multiplexer to 0 0 1 1
0 1 0 0 0
implement the operation 0 1 0 0
0 1 0 1 1
specified in the truth tables 0 1 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1 0 0 0 1
1 0 1 1 1 0 0 1 0
1 1 0 1 1 0 1 0 1
1 1 1 0 1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1 14
DECODER
• N inputs, 2N outputs
• Decoder asserts exactly one of its
outputs depending on the input
combination
• One-hot outputs: only one output
HIGH at once
• In general, an N:2N decoder can be A1 A0 Y3 Y2 Y1 Y0
constructed from 2N N-input AND 0 0 0 0 0 1
gates 0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
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DECODER EXAMPLE
Exercise: Implement a 2:4 decoder (previous slide) with AND,
OR, and NOT gates
A1 A0
Y3
Y2
Y1
Y0
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LOGICAL EXPRESSION WITH DECODER
Exercise: Implement the below equation using a 2:4 decoder
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PRIORITY CIRCUIT
Exercise: The dean, the department chair, the associate professor, and the teaching assistant
each use the auditorium from time to time. In order to avoid collision, design a room reservation
system. The reservation priority is equivalent of the post of instructors. Write a truth table and
Boolean equation for the system. Sketch a circuit that performs this function.
A3
A3 A2 A1 A0 Y3 Y2 Y1 Y0
Y3
0 0 0 0 0 0 0 0
A2 Y2 0 0 0 1 0 0 0 1
A3 A 2 A1 A0
Y3 A1 Y1 0 0 1 0 0 0 1 0
0 0 1 1 0 0 1 0
Y2 A0 Y0 0 1 0 0 0 1 0 0
PRIORITY
CiIRCUIT
0 1 0 1 0 1 0 0
0 1 1 0 0 1 0 0
Y1 0 1 1 1 0 1 0 0
A3 A2 A1 A0 Y3 Y2 Y1 Y0
1 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0
Y0 1 0 1 0 1 0 0 0
0 0 0 1 0 0 0 1 1 0 1 1 1 0 0 0
0 0 1 X 0 0 1 0 1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 0
0 1 X X 0 1 0 0 1 1 1 0 1 0 0 0
1 X X X 1 0 0 0 1 1 1 1 1 0 0
18 0
REFERENCES
[1] D.M. Harris, S.L. Harris, Digital Design and Computer
Architecture, 2. edition, Elsevier, 2013.
[2] T.L. Floyd, Digital Fundamentals, 11. edition, Global
Edition, Pearson, 2015.
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THANK YOU
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