A Summer Internship Report On

VERY LARGE SCALE INTEGRATION (VLSI)

An Internship Report submitted to
GURU NANAK INSTITUTIONS TECHNICAL CAMPUS
(Autonomous)
In partial fulfillment of the requirement for the award of the degree of

BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted by

Nellutla Pravalika
(21WJ5A0424)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

GURU NANAK INSTITUTIONS TECHNICAL CAMPUS
SCHOOL OF ENGINEERING & TECHNOLOGY
(An UGC Autonomous Institution - Affiliated to JNTU, Hyderabad)
Ibrahimpatnam, Ranga Reddy District -501506
Telangana
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE

This is to certify that the Summer Internship entitled “VERY LARGE SCALE

INTEGRATION (VLSI)” is being presented with report by Ms. NELLUTLA

PRAVALIKA bearing Roll.No.21WJ5A0424, in partial fulfillment for the award of Degree

of Bachelor of Technology in Electronics and Communication Engineering to Guru

Nanak Institutions Technical Campus (Autonomous) affiliated to Jawaharlal Nehru

Technological University, Hyderabad during the academic Year 2023-2024.

Internship Incharge HEAD OF DEPARTMENT

Mr. K Krishna Kumar Dr. Maheswara Reddy Sura
Assistant Professor Professor & HOD-ECE
 ACKNOWLEDGEMENT

I would like to express my sincere gratitude to my supervisor Mr. K Krishna Kumar,

Assistant Professor, Department of Electronics and Communication Engineering, for his
excellent guidance and invaluable support, which helped me accomplish my Bachelor degree
and prepared me to achieve more life goals in the future. His total support of my dissertation
and countless contributions to my technical and professional development made for a truly
enjoyable and fruitful experience. Special thanks are dedicated for the discussions we had on
almost every working day during the internship period and for reviewing my dissertation.
I am very much grateful to the Internship Co-Ordinator Mr. K Krishna Kumar, Assistant
Professor of ECE, GNITC, Hyderabad, who has not only shown utmost patience, but was
fertile in suggestions, vigilant in directions of error and has been infinitely helpful.

I am also thankful to our Academic Co-Ordinator, IV Year, Mr. D. Surendra Rao,

Associate Professor of ECE, GNITC, Hyderabad, for his support.
I am also thankful to Dr. Maheswara Reddy Sura, Professor & HOD of ECE & Academic
Coordinator, GNITC, Hyderabad, for being so helpful with valuable insights and guidance
during our internship period.
I am incredibly grateful to our Mentor Mr. K Krishna Kumar & Mr. A Vinisha, Assistant
Professors of ECE, GNITC, Hyderabad for being so thoughtful and helpful with truly
valuable insights and guidance during internship
I am thankful to Dr. P. Parthasarathy, Joint Director, GNITC for his support and valuable
inputs in our internship work.
I express my deepest gratitude and thanks to Dr. Koduganti Venkata Rao, Director,
GNITC for his constant support and encouragement and for providing me all the facilities in
the college during my internship work.
My sincere thanks to all the faculty members, administrative staff and management of
GNITC, without whose support our work would always remain incomplete.
On a more personal note, I thank our beloved parents and friends for their moral support
during the course of my internship.

In All Sincerity,
Nellutla Pravalika
(20WJ1A04Q8)
 LIST OF CONTENTS
Chapter no. Topic Name Page No.
Title page i
Certificate ii
Acknowledgement iii
List of content iv
List of figures v
Abstract vi
1 INTRODUCTION
1.1 General 1
1.2 History of VLSI Design 1
1.3 Basic Principles of VLSI Design 2

2 LITERATURE REVIEW
2.1 Evolution of VLSI Technology 3
2.2 Design Challenges and Innovations 3
2.3 Future Trends and Emerging Technologies 4

3 DESCRIPTION/METHODOLOGY
3.1 The Design Process of a VLSI IC 5
3.2 Software Specification 7
3.3 XILINX ISE Design Tools 8
3.4 Verilog -Language 9
3.5 Hardware Requirement 10
3.6 Introduction To Asics and Programmable Logic 11
3.7 Field-Programmable Gate Array (FPGA) 13
3.8 Definitions Of Relevant Terminology 14
3.9 Evolution Of Programmable Logic Devices 17
3.10 Modules And Ports in Verilog 18
3.11 Connection Rules in Verilog Port 20
3.12 Gate Level Modeling 23

4 ADVANTAGES AND DISADVANTAGES

4.1 The Advantages of VLSI Technology 31
4.2 The Disadvantages of VLSI Technology 32
5 APPLICATIONS
5.1 Computers
5.2 Mobile Devices 33
5.3 Automotive Electronics 34
5.4 Medical Electronics
5.5 Aerospace
6 CONCLUSION AND FUTURE SCOPE 35
7 REFERENCE 36

iv
 LIST OF FIGURES
S.no. Name of the Figure Page No.

3.1 This PCB with semiconductors would not be possible 7

without VLSI technology
3.2 Ports in Verilog 19
3.3 Multiplexer 28
3.4 Half adder 29
3.5 Full adder 30

v
ABSTRACT
The field of Very Large Scale Integration (VLSI) stands at the forefront of technological
advancement, facilitating the integration of millions to billions of transistors onto a single chip.
This documentation provides a comprehensive overview of VLSI design principles,
methodologies, and its pervasive applications across diverse industries.

Beginning with an exploration of the evolution of VLSI technology, this documentation delves
into the fundamental concepts of chip design, highlighting key challenges and innovations in
the field. It discusses the design methodologies, manufacturing processes, and the intricate
balance between performance, power efficiency, and reliability.

The documentation extensively covers the broad spectrum of VLSI applications, ranging from
its pivotal role in revolutionizing computing devices, mobile technologies, automotive
electronics, medical diagnostics, and aerospace systems. It showcases how VLSI chips drive
innovation, enabling advanced functionalities crucial for modern society.

Furthermore, the documentation examines the future prospects and emerging trends in VLSI,
emphasizing the potential impact of nanotechnology, novel materials, and their convergence
with AI, IoT, and quantum computing. It outlines the anticipated directions for VLSI,
envisioning a landscape where innovation continues to shape smarter, more efficient, and
interconnected technologies.

This comprehensive documentation serves as a guide for enthusiasts, researchers, and

practitioners in the VLSI domain, offering insights into the present landscape and charting the
course for the future of this ever-evolving field.

vi
 CHAPTER 1
INTRODUCTION TO VLSI
1.1 GENERAL

VLSI (Very Large-Scale Integration) design is a process of designing integrated circuits

(ICs) by integrating thousands, millions or even billions of transistors on a single chip. These
ICs are used in a variety of electronic devices ranging from simple handheld devices to complex
supercomputers. VLSI design involves designing and testing of integrated circuits at a very
small scale, typically in the range of 0.1 to 0.01 micrometers. This article will discuss the basics
of VLSI design, its history, and its applications.

1.2 History of VLSI Design:

The history of VLSI design can be traced back to the 1950s when the first transistor was
invented. Later on, in the 1960s, the first integrated circuit (IC) was developed which
revolutionized the electronics industry. With the development of ICs, the size of electronic
devices reduced drastically, and their functionality increased. In the 1970s, the first
microprocessor was invented, which gave birth to the modern computer era. The 1980s saw
the emergence of VLSI design as a discipline, and the first VLSI chip was designed in 1983.
Since then, VLSI design has been advancing at a rapid pace, and the technology has evolved
to produce more complex and efficient chips.

1.3 Basic Principles of VLSI Design:

The design of a VLSI chip involves various stages, starting from the specification of the chip
to the fabrication of the final product. The design process involves the following steps:
1. Specification: This is the first stage of VLSI design, where the requirements of the chip
are identified. The specifications of the chip are defined in terms of its functionality,
performance, and power consumption.
2. Architecture: Once the specifications of the chip are defined, the next step is to design
the architecture of the chip. This involves identifying the various components of the
chip, their interconnections, and their functions.
3. Logic Design: The logic design stage involves the creation of a digital circuit that
performs the desired functions. This involves the use of logic gates, which are combined
to create the required circuit.

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 4. Verification: The verification stage involves testing the functionality of the chip design.
This is done using simulation tools, which simulate the behavior of the chip under
various conditions.
5. Physical Design: The physical design stage involves laying out the various components
of the chip on a physical layout. This involves optimizing the layout to reduce the size
of the chip and improve its performance.
6. Fabrication: The final stage of VLSI design involves the fabrication of the chip. This is
done using lithography techniques, which involve the use of light to transfer the circuit
pattern onto the silicon wafer.

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 CHAPTER 2
LITERATURE REVIEW
2.1 Evolution of VLSI Technology:
The evolution of VLSI technology has been a cornerstone in the advancement of electronic
systems. Initially, the focus was on miniaturization and integration, leading to the birth of
integrated circuits (ICs) in the late 1950s. As Moore's Law predicted the doubling of transistor
density every two years, the semiconductor industry embraced this trajectory, enabling the
development of increasingly complex and powerful chips.

Researchers and engineers have continually pushed the boundaries of VLSI, transitioning from
simple designs to complex systems-on-chip (SoCs) and multi-core processors. This progression
has been pivotal in various domains, including computing, communication, and consumer
electronics. Moreover, the rise of nanoscale fabrication techniques has significantly contributed
to packing more functionality into smaller areas, propelling VLSI into new realms of efficiency
and capability.
2.2 Design Challenges and Innovations:

The relentless pursuit of higher performance and energy efficiency in VLSI design has
presented numerous challenges. Shrinking transistor sizes brought issues like leakage current,
heat dissipation, and reliability concerns to the forefront. Researchers have responded with
innovative design methodologies, exploring techniques such as low-power design, 3D
integration, and emerging technologies like nanowire transistors and memristors to mitigate
these challenges.

Furthermore, the increasing complexity of designs demands robust verification and testing
methodologies. This has led to the adoption of simulation tools, formal verification, and
hardware emulation platforms to ensure the functionality and reliability of VLSI systems.
Moreover, the shift towards heterogeneous computing architectures, incorporating CPUs,
GPUs, and specialized accelerators, has brought new challenges in system-level integration
and optimization.

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2.3 Future Trends and Emerging Technologies:

The future of VLSI is marked by the exploration of novel materials, architectures, and
computing paradigms. Researchers are investigating beyond CMOS technology towards
alternatives like spintronics, quantum computing, and nanotechnologies. These alternatives
promise leaps in energy efficiency, computation speed, and density, potentially surpassing the
limits of classical CMOS-based VLSI.

Moreover, the integration of VLSI with emerging fields like AI/ML hardware accelerators,
neuromorphic computing, and bio-inspired architectures opens new frontiers for specialized
and efficient computing. The convergence of these technologies holds promise for next-
generation applications in healthcare, autonomous systems, and personalized computing,
shaping the future landscape of VLSI technology.

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 CHAPTER 3
DISCRIPTION/METHODOLOGY
3.1 The Design Process of a VLSI IC
Overall, VLSI IC design incorporates two primary stages or parts:
1. Front-End Design: This includes digital design using a hardware description language, for
example, Verilog, System Verilog, and VHDL. Furthermore, this stage encompasses design
verification via simulation and other verification techniques. The entire process also
incorporates designing, which starts with the gates and continues through to design for
testability.
2. Back-End Design: This consists of characterization and CMOS library design.
Additionally, it involves fault simulation and physical design.
The entire design process follows a step-by-step approach, and the following are the front-end
design steps:
• Problem Specification: This is a high-level interpretation of a system. We address the
key parameters, such as design techniques, functionality, performance, fabrication
technology, and physical dimensions. The final specifications include the power,
functionality, speed, and size of the VLSI system.
• Architecture Definition: This includes fundamental specifications such as floating-
point units and which system to use, such as RISC or CISC and ALU's cache size.
• Functional Design: This recognizes the vital functional units of a system and, thus,
enables identification of each unit's physical and electrical specifications and
interconnect requirements.
• Logic Design: This step involves control flow, Boolean expressions, word width, and
register allocation.
• Circuit Design: This step performs the realization of the circuit in the form of a netlist.
Since this is a software step, it utilizes simulation to check the outcome.
• Physical Design: In this step, we create the layout by converting the netlist into a
geometrical depiction. This step also follows some preconceived static rules, such as
the lambda rules, which afford precise details of the ratio, spacing between components,
and size.
The following are the back-end design steps for hardware development:

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 • Wafer Processing: This step utilizes pure silicon melted in a pot at 1400º C. Then, a
small seed comprising the required crystal orientation is injected into liquefied silicon
and gradually pulled out, 1mm per minute. We manufacture the silicon crystal as a
cylindrical ingot and cut it into discs or wafers before polishing and crystal orientation.
• Lithography: This process (photolithography) includes masking with photo etching and
a photographic mask. Next, we apply a photoresist film on the wafer. A photo aligner
then aligns the wafer to a mask. Finally, we expose the wafer to ultraviolet light, thus
highlighting the tracks through the mask.
• Etching: Here, we selectively remove material from the surface of the wafer to produce
patterns. With an etching mask to protect the essential parts of the material, we use
additional plasma or chemicals to remove the remaining photoresist.
• Ion Implantation: Here, we utilize a method to achieve a desired electrical characteristic
in the semiconductor, i.e., a process of adding dopants. The process uses a beam of
high-energy dopant ions to target precise areas of the wafer. The beam's energy level
determines the depth of wafer penetration.
• Metallization: In this step, we apply a thin layer of aluminum over the entire wafer.
• Assembly and Packaging: Every one of the wafers contains hundreds of chips.
Therefore, we use a diamond saw to cut the wafers into single chips. Afterward, they
receive electrical testing, and we discard the failures. In contrast, those that pass receive
a thorough visual inspection utilizing a microscope. Finally, we package the chips that
pass the visual inspection as well as recheck them.
VLSI technology is ideally suited to the demands of today's electronic devices and systems.
With the ever-increasing demand for miniaturization, portability, performance, reliability, and
functionality, VLSI technology will continue to drive electronics advancement.

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Fig 3.1 This PCB with semiconductors would not be possible without VLSI technology.
Designing for the low margin of error that exists in VLSI technology requires using a state-of-
the-art PCB Design and Analysis software to help you get the job done right. Allegro,
by Cadence, is one such software that has all the features and analysis tools you need for
everything from basic to elaborate circuit designs.

3.2 SOFTWARE SPECIFICATION

XILINX ISE
INTRODUCTION
For over two decades, Xilinx has been at the bleeding edge of the programmable rationale
transformation, with the creation and proceeded with movement of FPGA stage innovation.
During that time, the job of the FPGA has developed from a vehicle for prototyping and paste
rationale to a profoundly adaptable option to ASICs and ASSPs for a large group of uses and
markets. Today, Xilinx® FPGAs have turned out to be deliberately fundamental to world-class
framework organizations that are wanting to endure and contend in this season of outrageous
worldwide monetary insecurity, transforming what was at one time the programmable upset
into the "programmable goal" for both Xilinx and our clients.

Programmable Imperative
At the point when seen from the client's viewpoint, the programmable basic is the need to
accomplish more with less, to evacuate hazard at every possible opportunity, and to separate
so as to endure. Generally, it is the journey to all the while fulfill the clashing requests made

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by consistently advancing item prerequisites (i.e., cost, power, execution, and thickness) and
mounting business challenges (i.e., contracting market windows, flighty market requests,
topped designing spending plans, raising ASIC and ASSP non-repeating building costs,
spiraling multifaceted nature, and expanded hazard). To Xilinx, the programmable basic speaks
to a two-overlay duty. The first is to keep creating programmable silicon developments at each
procedure hub that convey industry-driving an incentive for each key figure of legitimacy
against which FPGAs are estimated: value, control, execution, thickness, highlights, and
programmability. The subsequent duty is to furnish clients with more straightforward, more
intelligent, and all the more deliberately suitable plan stages for the formation of world-class
FPGA-based arrangements in a wide assortment of businesses—what Xilinx calls focused on
structure stages.

Base Platform
The base stage is both the conveyance vehicle for all new silicon contributions from Xilinx and
the establishment whereupon all Xilinx focused on plan stages are assembled. All things
considered, it is the most central stage used to create and run client explicit programming
applications and equipment plans as generation framework arrangements. Discharged at
dispatch, the base stage contains a strong arrangement of well-incorporated, tried, and focused
on components that empower clients to quickly begin a plan. These components include:

• FPGA silicon
• ISE® Design Suite structure condition
• Third-party union, recreation, and sign trustworthiness devices
• Reference plans basic to numerous applications, for example, memory interface and setup
structures.
• Development sheets that run the reference plans
• A large group of broadly utilized IP, for example, GigE, Ethernet, memory controllers, and
PCIe.

3.3 XILINX ISE Design Tools:

Xilinx ISE is the structure instrument given by Xilinx. Xilinx would be essentially
indistinguishable for our motivations.
There are four major strides in all advanced rationale plan. These comprise of:

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1. Plan – The schematic or code that portrays the circuit.
2. Amalgamation – The middle of the road transformation of intelligible circuit depiction to
FPGA code (EDIF) position. It includes sentence structure checking and consolidating of all
these paratedesign documents into a solitary record.
3. Spot Route–Where the design of the circuit is settled. This is the interpretation of the EDIF
into rationale doors on the FPGA.
4. Program – The FPGA is refreshed to mirror the structure using programming (.bit)
documents.
Test seat recreation is in the subsequent advance. As its name suggests, it is utilized for testing
the structure by mimicking the aftereffect of driving the sources of info and watching the yields
to check your plan.
ISE has the ability to complete a wide range of structure philosophies including: Schematic
Capture, Finite State Machine and Hardware Descriptive Language(VHDL or Verilog).

3.4 VERILOG -LANGUAGE

Equipment depiction dialects, for example, Verilog are like programming dialects since they
incorporate methods for portraying the engendering time and sign qualities (affectability).
There are two kinds of task administrators; a blocking task (=), and a non-blocking (<=) task.
The non-blocking task enables architects to portray a state-machine update without expecting
to announce and utilize impermanent capacity factors.

Since these ideas are a piece of Verilog's language semantics, originators could rapidly
compose portrayals of huge circuits in a moderately conservative and compact structure. At the
season of Verilog's presentation (1984), Verilog spoke to a gigantic efficiency improvement
for circuit creators who were at that point utilizing graphical schematic catch programming and
extraordinarily composed programming projects to report and reenact electronic circuits.

The creators of Verilog needed a language with grammar like the C programming language,
which was at that point generally utilized in building programming advancement. Like C,
Verilog is case-touchy and has an essential preprocessor (however less modern than that of
ANSI C/C++). Its control stream catchphrases (if/else, for, while, case, and so on.) are
proportional, and its administrator priority is perfect with C.

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Syntactic contrasts include: required piece widths for variable revelations, boundary of
procedural squares (Verilog uses start/end rather than wavy props {}), and numerous other
minor contrasts. Verilog necessitates that factors be given an unequivocal size. In C these sizes
are expected from the 'type' of the variable (for example a whole number sort might be 8 bits).

A Verilog configuration comprises of a chain of command of modules. Modules exemplify

plan progressive system, and speak with different modules through a lot of proclaimed
information, yield, and bidirectional ports. Inside, a module can contain any blend of the
accompanying: net/variable presentations (wire, reg, whole number, and so forth.),
simultaneous and successive articulation squares, and occasions of different modules (sub-
progressive systems). Successive explanations are set inside a start/end square and executed in
consecutive request inside the square. In any case, the squares themselves are executed
simultaneously, making Verilog a dataflow language.
Verilog's idea of 'wire' comprises of both sign qualities(4-state: "1, 0, skimming, vague") and
sign qualities (solid, feeble, and so on.). This framework permits dynamic displaying of shared
sign lines, where different sources drive a typical net. At the point when a wire has different
drivers, the wire's (meaningful) esteem is settled by an element of the source drivers and their
qualities.
A subset of explanations in the Verilog language is synthesizable. Verilog modules that fit in
with a synthesizable coding style, known as RTL (register-move level), can be physically
acknowledged by combination programming. Combination programming algorithmically
changes the (conceptual) Verilog source into a netlist, a coherently proportionate depiction
comprising just of basic rationale natives (AND, OR, NOT, flip-flops, and so on.) that are
accessible in a particular FPGA or VLSI innovation. Further controls to the net rundown at last
lead to a circuit manufacture outline, (for example, a photograph cover set for an ASIC or a bit
stream document for a FPGA).

3.5 HARDWARE REQUIREMENT

GENERAL
An incorporated circuit or solid coordinated circuit (likewise alluded to as IC, chip, or
microchip) is an electronic circuit produced by the designed dissemination of follow
components into the outside of a meager substrate of semiconductor material. Extra materials
are saved and designed to frame interconnections between semiconductor gadgets. Coordinated

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circuits are utilized in basically all electronic gear today and have altered the universe of
gadgets. PCs, cell phones, and other advanced apparatuses are presently inseparable pieces of
the structure of current social orders, made conceivable by the minimal effort of creation of
coordinated circuits. ICs were made conceivable by test revelations demonstrating that
semiconductor gadgets could play out the elements of vacuum tubes and by mid-twentieth
century innovation headways in semiconductor gadget creation.

3.6 INTRODUCTION TO ASICS AND PROGRAMMABLE LOGIC:

The most recent 15 years have seen the death in the quantity of cell-based ASIC plans as a
method for creating altered SoCs. Rising NREs, improvement times and hazard have for the
most part limited the utilization of cell-based ASICs to the most elevated volume applications;
applications that can withstand the multi-million-dollar advancement expenses related with 1-
2 structure re-turns. Experts gauge that the quantity of cell-based ASIC configuration begins
every year is presently just between 2000-3000 contrasted with ~10,000 in the late 1990s. The
FPGA has developed as an innovation that fills a portion of the hole left by cell-based ASICs.
However even after 20+ long stretches of presence and 40X more structure begins every year
than cell-based ASICs, the size of the FPGA showcase in dollar terms stays just a small amount
of that of cell-based ASICs.

This recommends there are numerous FPGA structures that never make it into generation and
that generally, the FPGA is still observed by numerous individuals as a vehicle for prototyping
or school training and has maybe even prevailing in really smothering industry development.
This paper presents another innovation, the subsequent age Structured ASIC that is tipped to
reenergize the way to development inside the gadgets business. It unites a portion of the key
points of interest of FPGA innovation (for example quick turnaround, no cover charges, no
base request amount) and of cell-based ASIC (for example low unit cost and power) to convey
another stage for SoC structure. This record characterizes necessities for advancement of
Application Specific Integrated Circuits (ASICs). It is proposed to be utilized as an informative
supplement to a Statement of Work. The record supplements the ESA ASIC Design and
Assurance Requirements (AD1), which is a forerunner to a future ESA PSS archive on ASIC
plan.

Structured ASICs

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Another option has as of late developed to address the market void among FPGAs and cell-
based ASICs. Investigators term this as the Structured ASIC.

Original Structured ASICs

Like the FPGA advertise, the Structured ASIC market had a whirlwind of early participants a
considerable lot of who have withdrawn the market. Models incorporate good semiconductor
organizations like NEC, LSI rationale and EDA merchants, for example, Simplicity.
Original Structured ASICs gave planners impressive power and cost enhancements over
FPGAs yet neglected to evacuate numerous boundaries to section that existed with customary
cell-based ASICs. Original Structured ASICs had the accompanying attributes:
Turn-around times were still 2-5 months from tape-out to silicon
NREs were still in the scope of $150-$250K or all the more making the innovation hard to
access for standard clients.
Minimum request amounts were required as wafers couldn't be shared among tasks or clients
Development expenses and time were additionally exceptionally high and long separately,
as planners were relied upon to experience thorough check down to the transistor level
Designers progressing from prototyping gadgets like FPGAs to original Structured ASICs
were as yet expected to overhaul the item into a totally new gadget, return to timing conclusion
and re-qualify the new gadget before it creation prepared.
While a few organizations still offer original Structured ASICs today, advertise
acknowledgment has been seriously restricted because of these boundaries to passage.
Nonetheless, these original Structured ASICs made ready for another age that would join the
advantages of both FPGAs and cell-based ASICs.

Second Generation Structured ASICs

Another age of Structured ASICs has developed available and is picking up footing. This age
uses a solitary by means of veil for arranging the gadget. In doing as such, it expels the
requirement for the enormous measures of SRAM arrangement components and metal
interconnect that torment the present FPGAs. The advantages to creators are conveyed through
a gadget that gives up to 20X lower gadget control utilization and up to 80% lower unit cost
than FPGAs, contingent upon gadget thickness, (bigger FPGAs have more design components
and metal interconnect).

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This new age of Structured ASICs, accessible from eASIC Corporation, and named Extreme
additionally expels the boundaries of conventional cell based ASICs and furthermore original
Structured ASICs. With Extremes Structured ASICs points of interest include:
• Turn-around times from tape-out to silicon is just 3 a month
• There are zero veil charges as different ventures can be shared on a wafer
• There is no base request amount
• Development apparatuses expenses are low (comparable to FPGA type instruments)
• Development time is short as fashioners need not perform check down to the transistor
level or perform thorough test inclusion
• Coarse FPGA-like engineering dependent on calls which gives assembling yield
favorable circumstances.

There are gadget alternatives for both prototyping and large scale manufacturing. Originators
progressing from prototyping N outrageous Structured ASICs to large scale manufacturing
Nextreme Structured ASICs need not return to timing conclusion or re-qualify the generation
gadget.

3.7 FIELD-PROGRAMMABLE GATE ARRAY (FPGA)

Incited by the advancement of new kinds of modern field-programmable gadgets (FPDs),the
procedure of planning computerized equipment has changed drastically in the course of recent
years. In contrast to past ages of innovation, in which board-level structures included huge
quantities of SSI chips containing fundamental entryways, for all intents and purposes each
computerized plan created today comprises for the most part of high-thickness gadgets. This
applies not exclusively to custom gadgets like processors and memory, yet in addition for
rationale circuits, for example, state machine controllers, counters, registers, and decoders. At
the point when such circuits are bound for high-volume frameworks they have been
incorporated into high-thickness door clusters. Notwithstanding, door cluster NRE costs
regularly are excessively costly and entryway exhibits take too long to even think about
manufacturing to be reasonable for prototyping or other low-volume situations. Therefore,
most models, and furthermore numerous creation structures are currently manufactured
utilizing FPDs. The most convincing points of interest of FPDs are moment producing
turnaround, low start-up costs, low money related hazard and (since writing computer programs

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is finished by the end client) simplicity of configuration changes. The market for FPDs has
become drastically over the previous decade to the point where there is presently a wide
combination of gadgets to browse.

3.8 Definitions of Relevant Terminology

Field-Programmable Device (FPD)
A general term that alludes to an incorporated circuit utilized for executing computerized
equipment, where the chip can be arranged by the end client to acknowledge various plans.
Programming of such a gadget frequently includes putting the chip into an exceptional
programming unit, yet a few chips can likewise be arranged "in-framework". Another name for
FPDs is programmable rationale gadgets (PLDs); in spite of the fact that PLDs envelop
indistinguishable sorts of chips from FPDs, we incline toward the term FPD on the grounds
that verifiably the word PLD has alluded to generally straightforward kinds of gadgets.

Programmable Logic Array (PLA)

A Programmable Logic Array (PLA) is a moderately little FPD that contains two
degrees of rationale, an AND-plane and an OR-plane, where the two levels are programmable
(note: in spite of the fact that PLA structures are in some cases installed into full-custom chips,
we allude here just to those PLAs that are given as isolated coordinated circuits and are client
programmable).

Programmable Array Logic (PAL)

A Programmable Array Logic (PAL) is a generally little FPD that has a programmable AND-
plane pursued by a fixed OR-plane.

Straight forward PLD

Alludes to a Simple PLD, for the most part either a PLA or PAL.

Complex PLD

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A progressively Complex PLD that comprises of a course of action of different SPLD-like
squares on a solitary chip. Elective names (that won't be utilized in this paper) once in a while
embraced for this style of chip are Enhanced PLD (EPLD), Super PAL, Mega PAL, and others.

Field-Programmable Gate Array (FPGA)

A Field-Programmable Gate Array is a FPD including a general structure that permits
extremely high rationale limit. Though CPLDs highlight rationale assets with a wide number
of sources of info (AND planes), FPGAs offer increasingly restricted rationale assets. FPGAs
additionally offer a higher proportion of flip-failures to rationale assets than do CPLDs.

High-Capacity PLDs (HCPLD):

High-limit PLDs: a solitary abbreviation that alludes to both CPLDs and FPGAs. This term has
been begat in exchange writing for giving a simple method to allude to the two sorts of gadgets.
Buddy is a trademark of Advanced Micro Devices.

• Interconnect - the wiring assets in a FPD.

• Programmable Switch-a client programmable switch that can interface a rationale
component to an interconnect wire, or one interconnect wire to another
• Logic Block-a generally little circuit hinder that is recreated in a cluster in a FPD. At
the point when a circuit is actualized in a FPD, it is first deteriorated into littler sub-
circuits that can each be mapped into a rationale square. The term rationale square is
for the most part utilized with regards to FPGAs, yet it could likewise allude to a square
of hardware in a CPLD.
• Logic Capacity-the measure of computerized rationale that can be mapped into a
solitary FPD. This is typically estimated in units of "identical number of doors in a
customary entryway cluster". At the end of the day, the limit of a FPD is estimated by
the size of door exhibit that it is practically identical to. In easier terms, rationale limit
can be thought of as "number of 2-input NAND entryways".
• Logic Density - the measure of rationale per unit zone in a FPD.
• Speed-Performance-measures the most extreme operable speed of a circuit when
executed in a FPD. For combinational circuits, it is set by the longest postponement
through any way, and for successive circuits it is the greatest clock recurrence for which
the circuit capacities appropriately. In the rest of this area, to give knowledge into FPD

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 advancement the development of FPDs in the course of recent decades is depicted.
Extra foundation data is likewise included on the semiconductor innovations utilized in
the assembling of FPDs.

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3.9 Evolution of Programmable Logic Devices:
The main sort of client programmable chip that could execute rationale circuits was the
Programmable Read-Only Memory (PROM), in which address lines can be utilized as rationale
circuit sources of info and information lines as yields. Rationale capacities, be that as it may,
once in a while require in excess of a couple of item terms, and a PROM contains a full decoder
for its location inputs. PROMS are along these lines a wasteful design for acknowledging
rationale circuits, as are once in a while utilized by and by for that reason. The primary gadget
grew later explicitly for actualizing rationale circuits was the Field-Programmable Logic Array
(FPLA), or essentially PLA for short.

A PLA comprises of two degrees of rationale entryways: a programmable "wired"

AND-plane pursued by a programmable "wired" OR-plane. A PLAis organized with the goal
that any of its sources of info (or their supplements) can be AND'ed together in the AND-plane;
each AND-plane yield would thus be able to compare to any item term of the information
sources. Also, each OR plane yield can be arranged to create the consistent aggregate of any of
the AND-plane yields.

The two drawbacks were because of the two degrees of configurable rationale, in light
of the fact that programmable rationale planes were hard to make and presented noteworthy
proliferation delays. To defeat these shortcomings, Programmable Array Logic (PAL) gadgets
were created. Buddies highlight just a solitary degree of programmability, comprising of a
programmable "wired" AND plane that feeds fixed OR-entryways. To make up for absence of
sweeping statement acquired on the grounds that the OR-Outputs plane is fixed, a few
variations of PALs are created, with various quantities of sources of info and yields, and
different sizes of OR-doors. Buddies as a rule contain flip-flops associated with the OR-
entryway yields so successive circuits can be figured it out.

Buddy gadgets are significant in light of the fact that when presented they profoundly
affected computerized equipment structure, and furthermore they are the reason for a portion
of the more up to date, increasingly complex models that will be depicted in a matter of seconds.
Variations of the fundamental PAL design are included in a few different items known by various
abbreviations. All little PLDs, including PLAs, PALs, and PAL-like gadgets are assembled
into a solitary classification called Simple PLDs (SPLDs), who's most significant

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qualities are minimal effort and high stick to-stick speed-execution. As innovation has
propelled, it has turned out to be conceivable to deliver gadgets with higher limit than SPLDs.
The trouble with expanding limit of a severe SPLD engineering is that the structure of the
programmable rationale planes develops too rapidly in size as the quantity of sources of info is
expanded.

3.10 Modules and Ports in Verilog

Modules
A Module is a basic building design block in Verilog and it can be an element that implements
necessary functionality. It can also be a collection of lower-level design blocks. As a part of
defining a module, it has a module name, port interface, and parameters (optional). The port
interface i.e. inputs and outputs is used to connect the high-level module with the lower one
and hides internal implementation.

Declaration
The module is declared using a keyword ‘module’ with an optional port list and followed by
its implementation. In the end, it is enclosed with the keyword ‘endmodule’.

module <module_name> (<port_list>);

...
<implementation>
...
endmodule

A module consists of variable declaration, dataflow statements, behavioral blocks, instantiation

of lower hierarchical modules, tasks, and functions. All of these are optional depending on the
requirement statements or blocks that can be used, but module, endmodule, and module name
are mandatory. It is not allowed to have nested modules; instead, it allows instantiating sub-
module to have the module connections.

// This is illegal to write

module dut_1;

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 ...
module dut_2;
...
endmodule
endmodule

Ports
An interface to communicate with other modules or a testbench environment is called a port.
In simple words, the input/ output pins of digital design are known as ports. This interface is
termed a port interface or port list. Since the port list is available for connection, internal design
implementation can be hidden from other modules or an environment.
Verilog keywords used for port declaration are as follows:

Port Type Keywords used Description

Input port input To receive signal values from another module

Output port output To send signal values to another module

Bidirectional port inout To send or receive signal values to another module.

Fig 3.2 Ports in Verilog

Example:
module mod(input a, b, output y);
...
endmodule

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Note:
1. Ports are of wire data type by default.
2. If output ports hold their value, then they must be declared as reg data type.
3. The input and inout ports can not be reg as they can not store values. Input ports pass
signals from externally connected signals.

3.11 Connection rules in Verilog port

While writing a module, the designer needs to make sure what type of signals have to be
connected to the module’s inputs and outputs and follow the below rules.

For understanding port connecting rules, consider the current design module as an internal
world and outside of the module to be an external world.

Port External Internal

Description
type world world

In an internal world, the input port must be of the net

input reg or net net type and it can be connected to reg or net type variable
in an external world.

In an internal world, the output port can be of reg or

output net reg or net net type and it must be connected to the net type
variable in an external world.

In an internal world, the inout port must be of the net

inout net net type and it must be connected to the net type variable
in an external world.

Module instantiation
While designing complex digital circuits, usually it is split into various modules that connect
to have a top-level block. Thus, Verilog supports a hierarchical design methodology. When a
module is instantiated, a unique object is created and it has a unique name. Similarly, a top-
level design can also be instantiated while creating a testbench.

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module dut_1(<port_list>);
...
endmodule

module dut_2(<port_list>);
...
endmodule

module dut_3(<port_list>);
dut_2 d2(...);
...
endmodule

// Top level module

module dut_top(<port_list>);
dut_1 d1(...);
dut_3 d3(...);
endmodule

Following the hierarchical approach, a particular signal can be reached out following hierarchy
and each identifier is separated using a dot.
// Hierarchical connections
dut_top.d3.d2.<signal> // To track a signal in dut_2 module.

A mechanism for connecting the port to the external signals

When a module is instantiated in the top-level hierarchy or top-level design in a testbench, any
one of the following methods can be used.

Method A: Connecting a port list in an ordered manner

An ordered manner connection is feasible when a port list has minimum signals as the user has
to follow the same order in which design level signals are declared.
Design declaration:

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module mux_2_1(
input sel,
input i0, i1,
output y);

Design instantiation in testbench:

module mux_tb;
reg in0, in1, select;
wire out;

mux_2_1 mux(select, in0, in1, out);

...
endmodule

Observe that the port list in design mux_2_1 and its instantiation in testbench mux_tb follow
the same order.
module mux_2_1(input sel, input i0, i1, output y); // At design
mux_2_1 mux(select, in0, in1, out); // At testbench

Note: It is not mandatory to use different names at the design and testbench level.
module mux_2_1(input sel, input i0, i1, output y); // At design
mux_2_1 mux(sel, i0, i1, y); // At testbench

Method B: Connecting a port list by name

For complex designs having more ports, remembering and writing in the same order while
instantiating the design is error-prone. In this method, the order of port list connection does not
matter based on the port name, the connection is established.
For an above example,
module mux_2_1(input sel, input i0, i1, output y); // At design
mux_2_1 mux(.i0(in0), .sel(select), .y(out), .i1(in1)); // At testbench

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3.12 GATE LEVEL MODELING
In Verilog, most of the digital designs are done at a higher level of abstraction like RTL.
However, it becomes natural to build smaller deterministic circuits at a lower level by using
combinational elements such as AND and OR.
Modeling done at this level is called gate-level modeling as it involves gates and has a one-to-
one relationship between a hardware schematic and the Verilog code.
Verilog supports a few basic logic gates known as primitives, as they can be instantiated, such
as modules, and they are already predefined.
Gate level modeling is virtually the lowest level of abstraction because the switch-level
abstraction is rarely used. Gate level modeling is used to implement the lowest-level modules
in a design, such as multiplexers, full-adder, etc. Verilog has gate primitives for all basic gates.

Verilog supports built-in primitive gates modeling. The gates supported are multiple-input,
multiple-output, tri-state, and pull gates.
The multiple-input gates are and, nand, or, nor, xor, and xnor whose number of inputs are two
or more, and has only one output.
The multiple-output gates are buf and not whose output is one or more and has only one input.
The language also supports the modeling of tri-state gates, including bufif0, bufif1, notif0,
and notif1. These gates have one input, one control signal, and one output.
The pull gates are pullup and pulldown with a single output only.

Syntax
Following is the basic syntax for each type of gates with zero delays, such as:
1. and | nand | or | nor | xor | xnor [instance name] (out, in1, ..., inN); // [] is optional a
nd | is selection
2. buf | not [instance name] (out1, out2, ..., out2, input);
3. bufif0 | bufif1 | notif0 | notif1 [instance name] (outputA, inputB, controlC);
4. pullup | pulldown [instance name] (output A);
One can also have multiple instances of the same type of gate in one construct separated by a
comma:
1. and [inst1] (out11, in11, in12), [inst2] (out21, in21, in22, in23), [inst3] (out31, in31, i
n32, in33);

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The gate-level modeling is useful when a circuit is a simple combinational, such as
a multiplexer. A multiplexer is a simple circuit that connects one of many inputs to an output.
Gate Primitives
Gate primitives are predefined modules in Verilog, which are ready to use. There are two
classes of gate primitives:
1. Single input gate primitives
2. Multiple input gate primitives

1. Single input gate primitives

Single input gate primitives have a single input and one or more outputs. The gate primitive
are not, buf, notif, and bufif also have a control signal.
The gates propagate only if the control signal is asserted, else the output is high impedance
state.
Not, buf Gates
These gates have only one scalar input but may have multiple outputs.
buf stands for a buffer and transfer the value from input to the output without any change in
polarity.
not stands for an inverter which inverts the polarity of the signal at its input. So a 0 at its input
will yield a 1 and vice versa.

Syntax
1. module gates ( input a, b,
2. output c, d);
3.
4. buf (c, a, b); // c is the output, a and b are inputs
5. not (d, a, b); // d is the output, a and b are inputs
6.
7. endmodule
Example
1. module tb;
2. reg a, b;
3. wire c, d;
4. integer i;

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 5. gates u0 ( .a(a), .b(b), .c(c), .d(d));
6. initial begin
7. {a, b} = 0;
8. $monitor ("[T=%0t a=%0b b=%0b c(buf)=%0b d(not)=%0b", $time, a, b, c, d);
9. for (i = 0; i < 10; i = i+1) begin
10. #1 a <= $random;
11. b <= $random;
12. end
13. end
14. endmodule

Bufif, Notif Gates

Bufif and notif primitives are buffers and inverters, respectively, with an additional control
signal to enable the output is available through bufif and notif primitives.
These gates have a valid output only if the control signal is enabled else, and the output will be
in high impedance.
There are two versions of these, one with the normal polarity of control indicated by a 1 such
as bufif1 and notif1. And second with the inverted polarity of control indicated by a 0 such as
bufif0 and notif0.
Syntax
1. module bufif_notif_gates (output c, d, input a, b);
2. bufif (c, a, b); // c is the output, a and b are inputs
3. notif (d, a, b); // d is the output, a and b are inputs
4. endmodule
Example
1. module bufif_notif_gates_tb;
2. reg a, b;
3. wire c, d;
4. bufif_notif_gates Instance0 (c, d, a, b);
5. initial begin
6. a = 0; b = 0;
7. #1 a = 0; b = 1;
8. #1 a = 1; b = 0;

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 9. #1 a = 1; b = 1;
10. end
11. initial begin
12. $monitor ("T=%t| a=%b |b=%b| c(bufif)=%b |d(notif)=%b", $time, a, b, c, d);
13. end
14. endmodule

2. Multiple Input Gate Primitives

Multiple input gate primitives include AND, OR, XOR, NAND, NOR, and XNOR. They may
have multiple inputs and a single output.
AND, OR, XOR Gates
An AND, OR, and an XOR gate need multiple scalar inputs and produce a single scalar output.
The first terminal in the argument list to these primitives is the output, which changed as any
inputs shift.
Syntax
1. module and_or_xor_gates (output c, d, e, input a, b);
2. and (c, a, b); // c is the output, a and b are inputs
3. or (d, a, b); // d is the output, a and b are inputs
4. xor (e, a, b); // e is the output, a and b are inputs
5. endmodule
Example
1. module and_or_xor_gates_tb;
2. reg a, b;
3. wire c, d, e;
4. and_or_xor_gates Instance0 (c, d, e, a, b);
5. initial begin
6. a = 0; b = 0;
7. #1 a = 0; b = 1;
8. #1 a = 1; b = 0;
9. #1 a = 1; b = 1;
10. end
11. initial begin

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 12. $monitor ("T=%t |a=%b |b=%b |c(and)=%b |d(or)=%b |e(xor)=%b", $time, a, b, c, d
, e);
13. end
14. endmodule

NAND, NOR, XNOR Gates

The inverse of all the above gates is NAND, NOR, and XNOR. The same design from above
is reused only that the primitives are interchanged with their inverse versions.
Syntax
1. module nand_nor_xnor_gates (output c, d, e, input a, b);
2. nand (c, a, b); // c is the output, a and b are inputs
3. nor (d, a, b); // d is the output, a and b are inputs
4. xnor (e, a, b); // e is the output, a and b are inputs
5. endmodule
Example
1. module nand_nor_xnor_gates_tb;
2. reg a, b;
3. wire c, d, e;
4. nand_nor_xnor_gates Instance0 (c, d, e, a, b);
5. initial begin
6. a = 0; b = 0;
7. #1 a = 0; b = 1;
8. #1 a = 1; b = 0;
9. #1 a = 1; b = 1;
10. end
11. initial begin
12. $monitor ("T=%t |a=%b |b=%b |c(nand)=%b |d(nor)=%b |e(xnor)=%b", $time, a, b,
c, d, e);
13. end
14. endmodule
All these gates may also have more than two inputs.
1. module all_gates (output x1, y1, z1, x2, y2, z2 , input a, b, c, d);
2. and (x1, a, b, c, d); // x1 is the output, a, b, c, d are inputs

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 3. or (y1, a, b, c, d); // y1 is the output, a, b, c, d are inputs
4. xor (z1, a, b, c, d); // z1 is the output, a, b, c, d are inputs
5. nand (x2, a, b, c, d); // x2 is the output, a, b, c, d are inputs
6. nor (y2, a, b, c, d); // y2 is the output, a, b, c, d are inputs
7. xnor (z2, a, b, c, d); // z2 is the output, a, b, c, d are inputs
8. endmodule
Gate Level Modeling of a Multiplexer
The gate-level circuit diagram of 4x1 mux is shown below. It is used to write a module for 4x1
mux.

Fig 3.3 Multiplexer

1. module 4x1_mux (out, in0, in1, in2, in3, s0, s1);
// port declarations

2. output out; // Output port.

3. input in0, in1, in2. in3; // Input ports.
4. input s0, s1; // Input ports: select lines.
5. // intermediate wires
6. wire inv0, inv1; // Inverter outputs.
5. 7.wire a0, a1, a2, a3; // AND gates outputs.

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 8. // Inverters.
9. not not_0 (inv0, s0);
10. not not_1 (inv1, s1);
11. // 3-input AND gates.
12. and and_0 (a0, in0, inv0, inv1);
13. and and_1 (a1, in1, inv0, s1);
14. and and_2 (a2, in2, s0, inv1);
15. and and_3 (a3, in3, s0, s1);
16. // 4-input OR gate.
17. or or_0 (out, a0, a1,a2,a3);
18. endmodule

Gate Level Modeling of Full-adder

Here is the implementation of a full adder using the half adder.
1. Half adder

Fig3.4 Half adder

1. module half_adder (sum, carry, in0, in1);
2. output sum, carry;
3. input in0, in1;
4. // 2-input XOR gate.

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 5. xor xor_1 (sum, in0, in1);
6. // 2-input AND gate.
And and_1 (carry, in0, in1);
7.endmodule
2. Full adder

Fig 3.5 Full adder

1. module full_adder (sum, c_out, ino, in1, c_in);

2. output sum, c_out;

3. input in0, in1, c_in;

4.

5. wire s0, c0, c1;

6. // Half adder: port connecting by order.

7. half_adder ha_0 (s0, c0, in0, in1);

8. // Half adder : port connecting by name.

9. half_adder ha_1 (.sum(sum),.in0(s0),.in1(c_in),.carry(c1));

10. // 2-input XOR gate, to get c_out.
11. xor xor_1 (c_out, c0, c1); 18.
12. Endmodule

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 CHAPTER 4

ADVANTAGES AND DISADVANTAGE

4.1 The Advantages of VLSI Technology
The following are the primary advantages of VLSI technology:
Reduced size for circuits:
Shrinking the physical footprint of circuits through VLSI techniques allows more components
to be integrated onto a single chip.
Increased cost-effectiveness for devices:
VLSI enables higher component integration, reducing manufacturing costs per unit and
enhancing overall device cost-effectiveness.
Improved performance in terms of the operating speed of circuits:
VLSI facilitates faster signal processing and data transfer due to shorter interconnect distances
and optimized layouts.
Requires less power than discrete components:
VLSI designs optimize power consumption by minimizing unnecessary operations and
enhancing energy efficiency.
Higher device reliability:
Integration reduces interconnections, minimizing failure points and enhancing the overall
reliability of the circuit.
Requires less space and promotes miniaturization:
VLSI's compactness allows for smaller device sizes, promoting miniaturization without
compromising functionality.

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4.2 The Disadvantages of VLSI Technology
Increased complexity in design and manufacturing:
The complexity of VLSI design demands specialized expertise and intricate manufacturing
processes, escalating development costs.
Higher sensitivity to fabrication defects:
The miniaturization in VLSI makes chips more susceptible to defects during manufacturing,
affecting yield rates and reliability.
Challenges in heat dissipation:
Higher integration densities lead to increased heat generation, posing challenges in effective
heat dissipation and impacting device performance.
Limited flexibility for upgrades or modifications: Once fabricated, VLSI circuits are
challenging to modify or upgrade, limiting flexibility for future improvements without
redesigning the entire system.
Potential for increased susceptibility to electromagnetic interference (EMI):
Dense integration in VLSI circuits can exacerbate EMI issues, affecting signal integrity and
overall performance.
Dependency on fabrication technology advancements:
VLSI heavily relies on advancements in semiconductor fabrication technologies, making it
subject to constraints or delays associated with these advancements.

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 CHAPTER 5
APPLICATIONS
5.1 Computers: VLSI chips, particularly GPUs (Graphics Processing Units), are indispensable
for parallel processing in graphics rendering, enabling high-quality visuals, gaming
experiences, and multimedia content creation. Additionally, VLSI plays a crucial role in data
centers, powering servers and enabling large-scale data processing, cloud computing, and
artificial intelligence algorithms.

5.2 Mobile Devices: Beyond enhancing battery life and functionality, VLSI chips enable
advanced features such as facial recognition, augmented reality (AR), and virtual reality (VR)
experiences in smartphones and tablets. Moreover, these chips facilitate efficient power
management, optimizing performance while conserving energy.

5.3 Automotive Electronics: In addition to safety features, VLSI chips enable infotainment
systems, GPS navigation, and vehicle-to-everything (V2X) communication in modern
automobiles. These chips support the integration of multiple sensors, enabling smart decision-
making and autonomous functionalities in vehicles.

5.4 Medical Electronics: VLSI chips continue to advance medical technology with their
applications in DNA sequencing, bioinformatics, and personalized medicine. They empower
cutting-edge research in genomics, proteomics, and drug discovery by enabling high-
throughput data processing and analysis.

5.5 Aerospace: VLSI technology contributes to advancements in satellite imaging, Earth

observation, and deep-space exploration. These chips enable high-speed data processing for
remote sensing, weather forecasting, and satellite communication systems critical for space
missions and satellite operations.

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Department of ECE, GNITC 34
 CHAPTER 6
CONCLUSION AND FUTURE SCOPE
Conclusion:

VLSI technology has revolutionized the modern world, serving as the backbone of innovation
across diverse industries. Its impact spans from powering the computing devices we use daily
to enabling critical applications in healthcare, automotive, aerospace, and beyond. VLSI chips
have not only enhanced processing power, reduced device sizes, and improved functionalities
but also paved the way for groundbreaking advancements in artificial intelligence, machine
learning, and complex data processing. The relentless evolution of VLSI has propelled
technological progress, making devices smarter, more efficient, and more capable than ever
before.

Future Scope:

Looking ahead, the future of VLSI holds immense promise and potential for further
transformation. Advancements in nanotechnology and emerging materials are poised to push
the limits of chip density and performance. The integration of VLSI with novel computing
paradigms like quantum computing and neuromorphic engineering opens new frontiers for
faster, more energy-efficient computing. Additionally, the convergence of VLSI with fields
like IoT, edge computing, and 5G technology is set to revolutionize connectivity and drive the
proliferation of smart, interconnected devices.

Moreover, the demand for specialized VLSI designs catering to specific applications, such as
AI hardware accelerators and customized medical devices, is expected to rise. This will fuel a
wave of innovation, prompting the development of tailored solutions to address unique
challenges across various industries. Furthermore, VLSI's role in sustainable technology,
particularly in energy-efficient computing and green electronics, will continue to grow,
contributing to a more eco-friendly and efficient technological landscape.

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 CHAPTER 7
REFERENCES

J. André, R. Furuta, and V. Quint, editors. Structured Documents, volume 2 of The

Cambridge Series on Electronic Publishing. Cambridge UniversityPress, 1989.

[Andr93]Marc Andreessen. NCSA Mosaic Technical Summary. Technical report,

National Center for Supercomputing Applications, 605 E. Springfield,Champaign, IL
61820, May 93.

[App93]Apple Computer. OpenDoc Technical Summary, October 1993. Version1.0.

[ATL94]ATLIS Consulting Group, Inc., 6011 Executive Boulevard, Rockville, MD 20852

Department of ECE, GNITC 36

 Guru Nanak Institutions Technical Campus
Department of Electronics and Communication Engineering
SUMMER INTERNSHIP-2023-24

VERY LARGE SCALE INTEGRATION (VLSI)

Presented by
Nellutla Pravalika
21WJ5A0424
Outline

• Introduction
• Objectives and Methodology
• Advantages and Disadvantages
• Applications
• Conclusion
• Future Scope
• References

SUMMER INTERNSHIP-2023 1
Introduction

Introduction to VLSI
Semiconductor Technology Integrated Circuits
Revolutionizing electronic design Creating complex functions on a single
microfabrication techniques single chip, optimizing performance

Historical Evolution
From the first microprocessors to the current era of nanotechnology

SUMMER INTERNSHIP-2023 2
Objectives and Methodology

O bjectives and M etho do lo g y

1 Research O bjectives
Defining the purpose and goals of VLS I research and development

2 M ethodolog y Selection
Exploring various approaches to VLSI design and fabrication

Testing and Validatio n

3
Evaluating the performance and reliability of VLS I systems

SUMMER INTERNSHIP-2023 3
Advantages

Advantages of VLSI
1 Compact Design 2 Enhanced Performance
Enabling com plex functionality in Im proving speed, efficiency, and
tight spatial constraints power consum ption of electronic
devices

3 Cost-Efficiency
Reducing production and maintenance expenses through integration

SUMMER INTERNSHIP-2023 4
Disadvantages

D isadvantag es of VLSI
Complex Design Challenges Design Verification

Managing heat dissipation and signal Ensuring error-free functionality of intricate VLSI
interference in densely packed circuits VLSI systems

M anufacturing Complexity Techno log ical O bsolescence

Requiring specialized equipment and Facing rapid advancem ents that render
for precise fabrication designs outdated

SUMMER INTERNSHIP-2023 5
Applications

Applications of VLSI

Biomedical D evices Autonomous Systems Consumer Electronics

Utilizing VLSI for advanced Enabling intelligent functions in Powering smartphones,
medical imaging and diagnostic in self-driving cars and robotic wearables, and smart home
diagnostic equipment robotic platforms devices with VLSI technology

SUMMER INTERNSHIP-2023 6
Conclusion

Conclusion: VLSI Innovations

Technological Integration Impact Future Prospects

Advancements Growing influence of VLSI Predicting new frontiers
Continued evolution in VLS I modern electronic systems and trends for VLSI in the
VLS I driving innovation and applications upcoming era
across industries

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Future Scope

Future Scope of VLSI

Q uantum Computing Green Electronics
Exploring VLSI applications in Developing energy- efficient VLSI
processing and supercom puting designs for sustainable electronic
systems

Artificial Intellig ence

Integrating VLSI with AI technologies for enhanced com putational capabilities

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References

References
• J. André, R. Furuta, and V. Quint, editors. Structured Documents, volume 2 of The
Cambridge Series on Electronic Publishing.
• Cambridge UniversityPress, 1989. [Andr93]Marc Andreessen. NCSA Mosaic Technical
Summary. Technical report, National Center for Supercomputing Applications, 605 E.
Springfield,Champaign, IL 61820, May 93.
• [App93]Apple Computer. OpenDoc Technical Summary, October 1993. Version1.0.
• [ATL94]ATLIS Consulting Group, Inc., 6011 Executive Boulevard, Rockville, MD 20852,

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 Thank You..!

SUMMER INTERNSHIP-2023