ROUTING
BY : Abhishek Mandole
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check_routability
▪ check_routability function, designers can identify potential problems early on and adjust the
placement of components or routing strategy to ensure a manufacturable design.
▪ Function might look for Blocked pins, Minimum spacing violation, Congestion etc.
set_app_option -name route.detail.timing_driven -value true
▪ set_app_option : This is likely a command used within the EDA tool to set an application option.
This option controls specific functionalities within the routing engine of the tool.
▪ -name route.detail.timing_driven : This specifies the name of the option being set.
▪ route : This indicates the option is related to the routing functionality of the tool
▪ detail : This part might be specific to a particular EDA tool and could refer to a more detailed or
advanced routing mode.
▪ timing_driven : This indicates that the routing should consider timing constraints during the
process. Timing constraints ensure signals can propagate between components within a specified
time frame, crucial for proper circuit functionality.
▪ -value true : This sets the value of the option to true. By setting it to true you are enabling timing
driven routing for detail routing steps.
BY : Abhishek Mandole
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set_app_options -name route.track.timing_driven -value true
▪ track : This refers to the stage of routing where individual wires (tracks) are placed to connect
components. It's a fundamental step after higher-level planning of connections.
▪ -value true : Sets the value of the option to true , enabling timing-driven routing during track
placement.
set_app_options -name route.track.crosstalk_driven -value true
▪ Instructs an Electronic Design Automation (EDA) tool to consider crosstalk during the track
placement stage of Integrated Circuit (IC) design.
▪ crosstalk_driven : This part is new and signifies that crosstalk effects should be considered
during track placement.
▪ -value true : Sets the value of the option true , enabling crosstalk-driven routing during track
placement.
set_app_options -name route.global.timing_driven -value true
▪ Applies timing constraints during the global routing stage of an Integrated Circuit (IC) design
process within an Electronic Design Automation (EDA) tool.
▪ global : This refers to the initial or global routing stage. In this stage, the EDA tool determines
the overall routing paths for connections between different blocks or modules on the chip. It
provides a high-level plan for the detailed routing to follow.
▪ -value true : sets the value of the option to true, enabling timing driven global routing.
BY : Abhishek Mandole
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set_ignored_layers -max_routing_layers M7 -min_routing_layer M2
▪ The command to be related to defining via restrictions in a via aware routing process within
an Electronic Design Automation (EDA) tool, likely for Integrated Circuit (IC) design.
▪ set_ignored_layers : This command instructs the EDA tool to configure via restrictions
during routing. Vias are tiny holes that allow electrical connections to pass between different
metal layers in a multilayer IC.
▪ -max_routing_layers M7 -min_routing_layer M2 : These options define the via restriction
based on metal layers.
set_app_options -name route.common.global_min_layer_mode -value allow_pin_connection
▪ common : Indicates this is a general routing option, likely applicable throughout the routing
process.
▪ global_min_layer_mode : This refers to the mode used to handle minimum via layer
restrictions during global routing.
▪ Global routing, as mentioned earlier, focuses on establishing initial connections between
different blocks or modules on the chip.
▪ Minimum via layer restrictions define the lowest metal layer that can be used for routing
connections.
▪ -value allow_pin_connection : This means via connections to pins will be allowed even if
they violate the minimum via layer restriction.
BY : Abhishek Mandole
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set_app_options -name route.common.global_max_layer_mode -value soft
▪ Appears to be related to via restrictions during the global routing stage of Integrated Circuit (IC)
design within an Electronic Design Automation (EDA) tool. Here's a breakdown of the command
and its effect.
▪ global_max_layer_mode : This refers to the mode used to handle maximum via layer restrictions
during global routing.
▪ Maximum via layer restrictions define the highest metal layer that can be used for routing
connections (except for power/ground connections).
▪ -value soft : This sets the value of the option to soft. Here, “Soft” likely refers to a mode that
prioritizes minimizing via usage during global routing, but with some flexibility.
set_app_options -name time.si_enable_analysis -value true
▪ set_app_options : This sets an application option within the EDA tool, specifically related to timing
analysis.
▪ -name time.si_enable_analysis : This defines the option and its value
▪ time : Signifies the timing analysis functionality of the tool
▪ si_enable_analysis : This refers to enabling a specific type of timing analysis, and "si" likely stands
for "Static Integrity" (though the exact naming convention might vary between EDA tools).
▪ -value true : Sets the value to true activating static timing analysis.
BY : Abhishek Mandole
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set_app_options -name time.enable_si_timing_windows -value true
▪ Instructs an Electronic Design Automation (EDA) tool to consider Signal Integrity (SI) effects
when calculating timing windows during Static Timing Analysis (STA) within the Integrated
Circuit (IC) design process.
▪ -name time.enable_si_timing_windows : This defines the option and its value
▪ time : Signifies the timing analysis functionality of the tool.
▪ enable_si_timing_windows : This indicates enabling the consideration of SI (Signal Integrity)
effects when calculating timing windows.
▪ -value true : sets the value true, activating SI-aware timing window calculation.
set_app_options -name time.enable_ccs_rcv_cap -value true
▪ Instructs an Electronic Design Automation (EDA) tool to consider the effects of receiver
capacitance during Static Timing Analysis (STA) within the Integrated Circuit (IC) design
process.
▪ -name time.enable_ccs_rcv_cap : This defines the option and its value.
▪ time : Signifies the timing analysis functionality of the tool.
▪ time.enable_ccs_rcv_cap : This part likely refers to enabling the inclusion of "Cell Charging
Time" (CCT) at the receiver during STA. "Rcv" might be a misspelling or abbreviation for
"receiver" in this context.
▪ -value true : sets the value true, activating the consideration of receiver capacitance during
timing analysis
BY : Abhishek Mandole
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route_auto -max_detail_route_iterations 10
▪ Applies to the detailed routing stage of an Integrated Circuit (IC) design process within an
Electronic Design Automation (EDA) tool. It sets a limit on the number of attempts the tool will
make to complete detailed routing connections.
▪ route_auto : This indicates that the command is related to the automatic detailed routing
functionality within the EDA tool.
▪ -max_detail_route_iterations : This specifies the maximum number of iterations the tool will
attempt for detailed routing.
▪ 10 : Sets the value to 10, limiting the tool to 10 attempts at completing all connections.
Save_block –as initial_routedone
route_opt
▪ Is a command likely used within an Electronic Design Automation (EDA) tool for the detailed
routing stage of Integrated Circuit (IC) design. It signifies initiating an optimization process for
the existing detailed routing.
▪ route_opt : This suggests the command triggers an optimization process on the current routing.
Save_block -as routing_done
BY : Abhishek Mandole
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Thank You
BY : Abhishek Mandole
LinkedIn : Abhishek Mandole
