CCS Technology

Synopsys Interoperability Forum

November 9, 2005

Bill Mullen
Vice President of Engineering
Synopsys, Inc.
 Composite Current Source (CCS)
Timing

Timing Noise Power

© 2005 Synopsys, Inc. (2)

 Delay Calculation Requirements
• Driver Model: drive arbitrary interconnect, including
high-impedance nets
• Receiver model: complex input capacitance
• Efficient characterization
• Vdd & Temperature scaling for IR drop, multi-Vdd, DVFS,
corners

load1

driver
Receiver Model
Driver Model
load2

© 2005 Synopsys, Inc. (3)

 NLDM Based Driver/Receiver Models
Cinp
+ Rd
Reduced-Order
-
Network Model
v(t)
Input cap –
single value

Driver Model Receiver Model

• Ramp voltage source, • min/max rise/fall input caps
fixed drive resistance
• Very fast – accurate for • Doesn’t model capacitance
most nets variation during transition
• Limited accuracy for
high impedance networks
with large drivers (RC-009)

© 2005 Synopsys, Inc. (4)

 Basics of CCS Timing
Receiver model C1, C2 vary with
Driver model
9 Input slew
9 Output load
i(t,v)
C1 C2 9 Rise vs. fall

Nonlinear 9 State of cell

Current
Source
Load1

Driver

Load2

© 2005 Synopsys, Inc. (5)

 Characterization for NLDM
Pin Capacitance Cell Delay / Slew Tables
input input
slew slew
0.7 0.7 3.31 3.61 3.98 4.12 5.32

0.5 Cinp 0.5 2.72 3.12 3.43 3.82 4.25

(single value)
0.2 0.2 2.22 2.54 2.72 3.11 3.47

0.1 0.1 1.31 1.75 1.99 2.31 2.77

.023 .047 .065 .078 .091 .023 .047 .065 .078 .091
output cap output cap

Measure cell delay

and output slew
Measure current
and voltage at input
pin for receiver
model

© 2005 Synopsys, Inc. (6)

 Characterization for CCS Timing
Receiver Model Driver Model
input input
slew slew
0.7 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 0.7
0.5 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 0.5
0.2 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 0.2
0.1 C1,C2 C1,C2 C1,C2 C1,C2 C1,C2 0.1
.023 .047 .065 .078 .091 .023 .047 .065 .078 .091
output cap output cap

Measure current
through load cap
Measure current for driver model
and voltage at input
pin for receiver
model

© 2005 Synopsys, Inc. (7)

 CCS Receiver Model Advantage
CCS Receiver
Model matches
both delay &
slew

Miller effect
One Cinp at input pin
value is of inverter
insufficient

Input cap: C1 CCS

single value Cinp Receiver model
C2

© 2005 Synopsys, Inc. (8)

 Vdd and Temperature

• CCS Timing enables high accuracy delay

calculation for wide range of Vdd and Temperature
• For power-aware design styles:
ƒ Single Vdd lib_1.2v.db
ƒ Multiple Vdd
ƒ Dynamic Voltage & Frequency Scaling (DVFS) lib_1.0v.db
• Advanced analysis including IR Drop effects
• What is scaled: lib_0.8v.db
ƒ Driver model
ƒ Receiver model Separate CCS
Libraries
ƒ Timing constraints: setup, hold, recovery, removal,
MPW
• Straightforward characterization

© 2005 Synopsys, Inc. (9)

 Constraint Arcs: Vdd & Temperature
• Constraint arc (timing check) values depend on
Vdd and Temperature
• CCS Timing supports nonlinear scaling of
constraint arcs
Setup vs. Vdd

110

105
D 100

tsetup 95

90
CK
setup (ps)

85

80

75

CK 70

65

60
0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2
D Vdd (V)

© 2005 Synopsys, Inc. (10)

CCS Timing Results
 Results: STARC, TSMC

STARC Major Foundry

3500
Delay (HSPIC E vs PT-liberty,PT-C C S)
900
Delay (HSPIC E vs PT-liberty,PT-C C S)

850
3000
liberty,C C S [ps]

800

2500
750
liberty
-3%
+3%
2% vs.
liberty,CC S[ps]

CC S

HSPICE
700

650
2000
HSPICE[ps]
600
600 650 700 750 800 850 900
liberty
-3%
1500 +3%
CC S

1000 3% vs.
500
HSPICE
HSPICE[ps]
0
0 500 1000 1500 2000 2500 3000 3500

PrimeTime2004.12 with STARC PrimeTime2005.06 with 90nm

90nm CCS liberty libraries CCS liberty libraries
Error : < 3% vs. HSpice Error : < 2% vs. HSpice

© 2005 Synopsys, Inc. (12)

 Customers Demonstrate CCS Accuracy

CCS Accuracy v s. HSPICE CCS & NLDM vs. HSPICE

+/-2%
5 +/-3%
6,000

4 5,000

4,000
3
C C S [ns]

CCS
NLDM

H SP IC E
-2% 3,000
CCS
+2% +3%
2 -3%

2,000

1
1,000

-
0
0 1,000 2,000 3,000 4,000 5,000 6,000
0 1 2 3 4 5 Prime Time
Hspice [ns]

90nm Library 65nm Library

Major Electronics Firm in Asia Leading Global IDM

© 2005 Synopsys, Inc. (13)

 CCS Timing Summary

• High accuracy delay and slew calculation

ƒ Advanced driver and receiver modeling
ƒ Results within 2% of SPICE
ƒ Powerful scaling for Vdd and Temperature
• No impact on analysis runtime
• Easy and efficient characterization
• Industry Support
ƒ ARM, TSMC, Virage Logic, STARC, Library
Technologies, Synopsys NanoChar

© 2005 Synopsys, Inc. (14)

 Composite Current Source (CCS)
Noise

Timing Noise Power

© 2005 Synopsys, Inc. (15)

 Noise Analysis

Aggressor Failure Analysis

0
Victim

Calculate Propagated
Glitch
Glitch

© 2005 Synopsys, Inc. (16)

 Noise Modeling Requirements

• Accurate model to support:

ƒ Noise bump calculation
ƒ Noise propagation
ƒ Driver weakening (combination of propagated and
injected bumps)
ƒ Vdd and Temperature scaling
• Characterization should be fast and cover a broad
set of cell types
• Model must enable efficient calculation in
analysis and implementation tools

© 2005 Synopsys, Inc. (17)

 NLDM Noise Modeling in Liberty

Aggressor Noise
Immunity
Curve

0
Victim

I/V Curve
Noise
Propagation

Table-based noise immunity and propagation

characterization require extensive circuit simulation

© 2005 Synopsys, Inc. (18)

 Introducing CCS Noise

• Faster Characterization:
ƒ 100X faster characterization vs. NLDM Noise
• Much less circuit simulation is needed
ƒ Typical 90nm library in under 4 hours on 10 cpus
• High Accuracy:
ƒ Accurately models noise propagation and driver
weakening
ƒ Accurate voltage and temperature scaling using
the same scaling mechanism as CCS Timing
ƒ Same accurate receiver modeling as CCS Timing

© 2005 Synopsys, Inc. (19)

 CCS Noise: Cell Model
Inverter: 1 stage cell

DFF: multi-stage cell

CCS-N

CCS-N Q
D CCS-N
AND: 2 stage cell
CK CCS-N
CCS-N

CCS-N
CCS-N

• First and last transistor stages are modeled

© 2005 Synopsys, Inc. (20)
 Arc and Pin CCS Noise Models
• Input stage: Noise immunity
• Output stage: Driving strength
• Arc: Immunity + Driving Strength + Noise Propagation
ƒ For paths of one or two stages

Pin-Based Model
Arc-based Model

CCS-N CCS-N Q
D CCS-N
CCS-N
CCS-N
CK CCS-N

© 2005 Synopsys, Inc. (21)

 Arc-Based Example: AND2

A1 A1
Z CCS-N
N_7 Z
CCS-N
A2
CCS-N

A2

© 2005 Synopsys, Inc. (22)

 AND2 – Liberty Syntax
pin(Z) {
direction : output;
…
timing() {
related_pin : "A1";
ccsn_first_stage() { /* A1 to N_7 */
…
}
ccsn_last_stage() { /* N_7 to Z */
…
}
}

timing() {
related_pin : "A2";
ccsn_first_stage() { /* A2 to N_7 */
…
}
ccsn_last_stage() { /* N_7 to Z, copy of the above */
…
}
}
}

© 2005 Synopsys, Inc. (23)

 CCS Noise Stage Contents

Each CCS Noise stage has three components:

1. DC Current Table
2. Dynamic Behavior
CCS Noise stage
Information
3. Parameters

© 2005 Synopsys, Inc. (24)

 Characterization: DC Current Table

• DC Current table represents output current as a function

of two variables
ƒ Vin: Input voltage
ƒ Vout: Output voltage
• A fast DC sweep simulation is used to capture data

+ +
Vin - - Vout

© 2005 Synopsys, Inc. (25)

 Characterization: Dynamic Behavior

• Small number of transient simulation runs

ƒ Inputs: A few ramps and a few glitches
ƒ Output response is used to derive the dynamic
behavior of the stage

© 2005 Synopsys, Inc. (26)

 Noise Propagation Accuracy

• CCS Noise accurately models dynamic effects

such as the impact of charging/discharging of
internal nodes Propagated noise
waveform (HSPICE)
1

Internal Nodes
Voltage (V)
0.5

Propagated noise
waveform (PTSI)

Input noise waveform

0
(HSPICE)
0 100 200 300 400
Time (ps)

© 2005 Synopsys, Inc. (27)

 CCS Noise Bump Height Correlation
aggressor

A B
(quiet) victim

aggressor

1.2 1.2

Noise Bump Calculation Noise Propagation

1
(Node A) 1
(Node B)
PTSI Noise Height (V)

PTSI Noise Height (V)

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0 0
0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 1.2
SPICE Noise Height (V) SPICE Noise Height (V)

© 2005 Synopsys, Inc. (28)

 Noise Propagation Correlation

1.2 1.2

10%
1 1
PTSI Noise Height (V)

PTSI Noise Height (V)

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0 0
0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 1.2
SPICE Noise Height (V) SPICE Noise Height (V)

NLDM Noise CCS Noise

© 2005 Synopsys, Inc. (29)

 CCS Noise – Fast Characterization

Library Technology Number Characterization

of cells time on 10 CPUs
Lib1 90-nm 595 1.5 hrs

Lib2 90-nm 747 2 hrs

Lib3 90-nm 593 4 hrs

Lib4 90-nm 541 1 hr

Lib5 90-nm 1304 4 hrs

Lib6 65-nm 766 3 hrs

© 2005 Synopsys, Inc. (30)

 CCS Noise Summary

• Very good customer beta test results

• Fast characterization
ƒ Typical library in under 4 hours on 10 cpus
ƒ For large blocks, only need to characterize
boundary stages
• Fast calculation – no measurable overhead
during noise analysis
• High Accuracy
ƒ Noise propagation and driver weakening
ƒ Voltage and temperature scaling

© 2005 Synopsys, Inc. (31)

 Composite Current Source (CCS)
Power

Timing Noise Power

© 2005 Synopsys, Inc. (32)

 Power Library Requirements

• Address needs of Multi-Voltage designs

ƒ Multi-Rail cells (Vdd, Vss)
ƒ Non-zero ground rail
ƒ MTCMOS (power gating)
• Static and dynamic rail analysis
ƒ Support accurate voltage (IR) drop calculation
• Single library / model for all power related
applications
• Fast and easy library characterization

© 2005 Synopsys, Inc. (33)

 Power Gating (MTCMOS)
Reduce Leakage by turning block off
Fine Grain:
Vdd Vsleep Sleep transistor within each cell

MTCMOS IN LVt OUT

VirtualVdd
Block A
Sleep
Block B
Sleep-mode
Power switch control
Coarse Grain:
Sleep transistor for entire block
Block C VDD

VDD
VSS
Challenge: Analyze “in-rush
INTERNAL VSS
current” when block turns on

© 2005 Synopsys, Inc. (34)

 Introducing CCS Power

• Switching current waveform for each power or ground pin

ƒ Finer time resolution
ƒ Full Multi-Voltage support
• Equivalent parasitics as seen from the power network
ƒ Allows fast yet accurate rail analysis
• Support for macro power modeling for memory and IP
• Unified library model for power optimization, power
analysis, rail analysis
ƒ Fast and easy to characterize

© 2005 Synopsys, Inc. (35)

 Characterization for NLPM
Liberty Non-Linear Power Model

Internal Energy per 3.31

transition
0.7 3.61 3.98 4.12 5.32

input 0.5
2.72 3.12 3.43 3.82 4.25

slew 0.2 2.22 2.54 2.72 3.11 3.47

0.1 1.31 1.75 1.99 2.31 2.77

.023 .047 .065 .078 .091

Leakage power per state output cap

© 2005 Synopsys, Inc. (36)

 Characterization for CCS Power

Dynamic Current
Waveform per
transition per Rail
0.7
0.5
i(t)
0.2
0.1
input
Leakage current per state slew .023 .047 .065 .078 .091

per rail output cap

Can characterize CCS Power switching

information concurrently with CCS Timing
© 2005 Synopsys, Inc. (37)
 CCS Power Characterization
• HSPICE Simulation: AND gate with rising input
ƒ Power pin (Vdd) current
ƒ Ground pin (Vss) current

© 2005 Synopsys, Inc. (38)

 Advantages: Time Resolution

• Captures complete
power and ground pin
current waveforms
ƒ Charge/energy can
be calculated by
integrating current
I n (t n − t n −1 )
+∞
I i + I i −1
n

∫0 Idt ≈ ∑ (ti − ti −1 ) +
i =1 2 ln (I n −1 I n )

© 2005 Synopsys, Inc. (39)

 Dynamic Rail Analysis
• Compute instance-specific voltage drop at
all power/ground pins
• Requires cell model for switching and non-
switching cases

VDD1

Rpar
Cpar

GND

© 2005 Synopsys, Inc. (40)

 Equivalent Parasitics for Non-
Switching Case
• Essential for accurate rail analysis – additional decoupling cap
• Cpar per input state for each power or ground pin
• Rpar per input state for each power or ground pin to each output

IN1 Rpar

OUT
Cpar Cload
Cload
Cint
IN2

Equivalent Parasitics

© 2005 Synopsys, Inc. (41)

 CCS Power Summary

• Single Power Model For All Power Applications:

ƒ Power Optimization, Dynamic Rail Analysis, Power
Analysis
• Accurately Models:
ƒ Transient current during switching
ƒ Equivalent parasitics for non-switching case
ƒ Leakage current
ƒ Multi-Voltage designs
• Multi-rail cells
• Non-zero ground rail
ƒ MTCMOS: fine-grain or coarse-grain
• Characterized concurrently with CCS Timing

© 2005 Synopsys, Inc. (42)

 CCS Summary
Continuing With A Tradition Of Innovation
• CCS - Next Generation Modeling Technology
ƒ Open Source
ƒ Unified Model For Timing, Noise and Power
ƒ Higher Accuracy as Needed By 90nm and Below

• Easy and Efficient Library Characterization

• Complete Ecosystem: Models, Format, Characterization

Timing Noise Power

© 2005 Synopsys, Inc. (43)

 Technical Collateral Material

• Technical collateral material for CCS is available on:

www.synopsys.com/products/solutions/galaxy/ccs/cc_source.html

• It includes:
ƒ CCS Backgrounder
ƒ White Papers
ƒ Format Specification
ƒ FAQ

© 2005 Synopsys, Inc. (44)