Unit – 2 INTERFACING WITH 8086

❖Memory interfacing
❖Parallel communication interface
❖Timer
❖ Keyboard /display controller
❖Interrupt controller
❖ DMA controller
❖ Assembly language programming related to the above
interfacing

1
2
Programmable Peripheral Interface

8255

10
Block Diagram of 8255
It has a 40 pins of 4 groups.

1. Data bus buffer

2. Read Write control logic
3. Group A and Group B controls
4. Port A, B and C

Data bus buffer:

●This is a tri state bidirectional buffer used to interface the 8255

to system data bus. Data is transmitted or received by the buffer
on execution of input or output instruction by the CPU.

• Control word and status information are also transferred

through this unit.
Read/Write control logic
 __ __ __
A1 A0 RD WR CS Operations
0 0 0 1 0 PORT A Read Operation

0 1 0 1 0 PORT B Read Operation

1 0 0 1 0 PORT C Read Operation

0 0 1 0 0 PORT A Write Operation

0 1 1 0 0 PORT B Write Operation

1 0 1 0 0 PORT C Write Operation

1 1 1 0 0 CONTROL REGISTER Write Operation

x x x x 1 DATA BUS TRI STATED

1 1 0 1 0 ILLEGAL CONDITION

x x 1 1 0 DATA BUS TRI STATED

 Group A and Group B controls
These block receive control from the CPU and issues commands
to their respective ports.

● Group A – Port A and PCU ( PC7 –PC4)

• Group B – Port B and PCL ( PC3 – PC0)

• Control word register can only be written into no read

operation of the CW register is allowed.
 PORTS
a) Port A: This has an 8 bit latched/buffered O/P and 8 bit input
latch. It can be programmed in 3 modes – mode 0, mode 1,
mode 2.

b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input
latch. It can be programmed in mode 0, mode1.

c) Port C : This has an 8 bit latched input buffer and 8 bit out put
latched/buffer. This port can be divided into two 4 bit ports
and can be used as control signals for port A and port B. it can
be programmed in mode 0.
8255 MODES OF OPERATION

8255 modes

Basic I/O mode Bit Set Reset (BSR) mode

Mode 0 Mode 1 Mode 2

Mode 0:
▪ In this mode port A, port B and port C can be used individually either as
input or as output.
Mode 1:
▪ In this mode port A, port B can be used individually either as input or as
output.
▪ Port C is used as handshake lines for port A and port B.
Mode 2:
▪ In this mode port A is used as bidirectional data bus.
▪ Port B is used either as input or as output either in mode 0 or in mode 1.
▪ Port C is used as handshake lines for port A and port B.
BSR mode:
▪ This mode is applicable only for port C
▪ Each bit in port C can be set or reset individually
▪ This is used for On/Off applications.
8255 CONTROL WORD FORMAT
1) I/O Control Word Format
2) BSR Control Word Format
BSR Mode: In this mode any of the 8-bits of port C can be set or reset
depending on D0 of the control word. The bit to be set or reset is selected by
bit select flags D3, D2 and D1 of the CWR
Example:
An 8255 is interfaced with 8 number of switches at port A, and 8
number of LEDs at port B, as shown in the Figure below. It is required
to read the status of the switches and display it in the LEDs. Determine
a suitable control word and develop a program to perform the
requirement. Assume that the address of Port A,B,C and control
register is FFE0,FFE2,FFE4 and FFE6 respectively
Control word: 1 0 0 1 0 0 0 0 = 90H

Program:
MOV DX, FFE6
MOV AL, 10010000B
OUT DX,AL
MOV DX, FFE0
IN AL, DX
MOV DX, FFE2
OUT DX,AL
 8279
Programmable Keyboard/Display
Interface
● A programmable keyboard and display interfacing chip.

● Scans and encodes up to a 64-key keyboard. And Controls up to

a 16 digit numerical display.

● Keyboard section has a built-in FIFO 8 character buffer.

● The display is controlled from an internal 16x8 RAM that stores

the coded display information.

● 8279 has 8 control words to be considered before It is

programmed
8279 INTERNAL ARCTHITECTURE
IRQ
FIFO/Sensor RAM and Status Logic:

●Strobed input mode, this block acts as 8-byte first-in-first out (FIFO) RAM. Each
key code of the pressed key is entered in the order of the entry and in the mean time
read by the CPU, till the RAM become empty.

In scanned sensor matrix mode, this unit acts as sensor RAM. Each row of the sensor
RAM is loaded with the status of the corresponding row of sensors in the matrix. If a
sensor changes its state, the IRQ line goes high to interrupt the CPU.

●The status logic generates an interrupt after each FIFO read operation till the FIFO
is empty.

● Key Board Debounce and Control:

It is enabled only when keyboard mode is selected

●

In this mode, return lines are scanned whether any kays are closed in the row.
●

If debounce circuit is detect any closed switch it waits about 10ms.

●

It is continued, the status and control keys are transferred into RAM.
●
●Display Address Registers and Display RAM : The display address register
holds the address of the word currently being written or read by the CPU to or
from the display RAM. The contents of the registers are automatically updated
by 8279 to accept the next data entry by CPU.
(i)Scanned Keyboard mode with 2 Key Lockout :
● In this mode of operation, when a key is pressed, a debounce logic comes
into operation. During the next two scans, other keys are checked for
closure and if no other key is pressed the first pressed key is identified.

● The key code of the identified key is entered into the FIFO with SHIFT
and CNTL status, provided the FIFO is not full, i.e. it has at least one byte
free. If the FIFO does not have any free byte, naturally the key data will not
be entered and the error flag is set.

● If FIFO has at least one byte free, the above code is entered into it and the
8279 generates an interrupt on IRQ line to the CPU to inform about the
previous key closures. If another key is found closed during the first key,
the keycode is entered in FIFO.

• If the first pressed key is released before the others, the first will be
ignored. A key code is entered to FIFO only once for each valid depression,
independent of other keys pressed along with it, or released before it.

● If two keys are pressed within a debounce cycle (simultaneously ), no key

is recognized till one of them remains closed and the other is released. The
last key, that remains depressed is considered as single valid key
depression.
(ii)Scanned Keyboard with N-Key Rollover
● In this mode, each key depression is treated independently.
When a key is pressed, the debounce circuit waits for 2
keyboards scans and then checks whether the key is still
depressed. If it is still depressed, the code is entered in FIFO
RAM.
● Any number of keys can be pressed simultaneously and
recognized in the order, the keyboard scan recorded them. All
the codes of such keys are entered into FIFO.
● In this mode, the first pressed key need not be released before
the second is pressed. All the keys are sensed in the order of
their depression, rather in the order the keyboard scan senses
them, and independent of the order of their release.
Output (Display) Modes : 8279 provides two output modes for selecting the
display options. These are discussed briefly.

1. Display Scan : In this mode 8279 provides 8 or 16character multiplexed

displays those can be organized as dual 4- bit or single 8-bit display units.

2. Display Entry : ( right entry or left entry mode ) 8279 allows options for
data entry on the displays. The display data is entered for display either from
the right side or from the left side.
 8259
Programmable Interrupt Controller
 8259 Programmable Interrupt Controller

● The 8259 programmable interrupt controller (PIC) adds eight

vectored priority encoded interrupts to the microprocessor.
● It accepts request from the peripheral equipment, determine
which of the incoming requests is of the highest importance
● Special features of 8259:
● Eight level priority controller

● Expandable to 64 levels

● Programmable interrupt modes

● Individual request mash capability

 It is packaged in a 28-pin DIP, uses NMOS technology and requires a single
a5V supply. Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and real time overhead in
handling multi-level priority interrupts.
It has several modes, permitting optimization for a variety of system
requirements
 INTERRUPT REQUEST REGISTER (IRR) AND
IN-SERVICE REGISTER (ISR)
The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt
Request Register (IRR) and the In-Service (ISR). The IRR is used to store all the interrupt levels
which are requesting service; and the ISR is used to store all the interrupt levels which are being
serviced.

PRIORITY RESOLVER
This logic block determines the priorities of the bits set in the IRR. The highest priority
is selected and stored into the corresponding bit of the ISR during INTA pulse.

INTERRUPT MASK REGISTER (IMR

The IMR stores the bits which mask the interrupt lines to be masked. The IMR operates
on the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower
quality.

INT (INTERRUPT)
This output goes directly to the CPU interrupt input. The V level on this line is
designed to be fully compatible with the 8080A, 8085A and 8086 input
levels.
INTA (INTERRUPT ACKNOWLEDGE)
INTA pulses will cause the 8259A to release vectoring information onto the data bus. The format
of this data depends on the system mode (mPM) of the 8259A.
DATA BUS BUFFER
This 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the system Data Bus.
Control words and status information are transferred through the Data Bus Buffer.
READ/WRITE CONTROL LOGIC
The function of this block is to accept Output commands from the CPU. It contains the
Initialization Command Word (ICW) registers and Operation Command Word (OCW) registers which
store the various control formats for device operation. This function block also allows the status of the
8259A to be transferred onto the Data Bus.
CS (CHIP SELECT)
A LOW on this input enables the 8259A. No reading or writing of the chip will occur unless
the device is selected.
WR (WRITE)
A LOW on this input enables the CPU to write control words (ICWs and OCWs) to the
8259A.
RD (READ)
A LOW on this input enables the 8259A to send the status of the Interrupt Request Register
(IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or the Interrupt level onto the Data
Bus.

A0 This input signal is used in conjunction with WR and RD signals to write commands into the
various command registers, as well as reading the various status registers of the chip. This line can be
tied directly to one of the address lines
.
 PROGRAMMING THE 8259A

The 8259A accepts two types of command words generated by the CPU:
1.Initialization Command Words (ICWs):
Before normal operation can begin, each 8259A in the system must be brought to a
starting point -by WR pulses.
2. Operation Command Words (OCWs): These are the command words which
command the 8259A to operate in various interrupt modes.
These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A anytime after initialization.
 INTERRUPT SEQUENCE
The events occur as follows in an MCS-80/85 system:

1. One or more of the INTERRUPT REQUEST lines (IR7±0) are raised high, setting the
corresponding IRR bit(s).
2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with an INTA pulse.
4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and
the corresponding IRR bit is reset. The 8259A will also release a CALL instruction code
(11001101) onto the 8-bitData Bus through its D7±0 pins.
5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A
from the CPU group.
6. These two INTA pulses allow the 8259A to release its preprogrammed subroutine
address onto the Data Bus. The lower 8-bit address is released at the first INTA pulse and the
higher 8-bitaddress is released at the second INTA pulse.
7. This completes the 3-byte CALL instruction released by the 8259A. In the AEOI
mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR bit remains set
until an appropriate EOI command is issued at the end of the interrupt sequence.
Initialization Sequence
 INITIALISATION COMMAND WORDS
ICW1
●A5±A15: Page starting address of service routines .In an MCS 80/85 system,
the 8 request levels will generate CALLs to 8 locations equally spaced in
memory. These can be programmed to be spaced at intervals of 4 or 8
memory locations, thus the 8 routines will occupy a page of 32 or 64 bytes,
respectively. The address format is 2 bytes long (A0±A15). When the routine
interval is 4, A0±A4 are automatically inserted by the 8259A, while A5±A15
are programmed externally. When the routine interval is 8, A0±A5 are
automatically inserted by the 8259A, while A6±A15 are programmed
externally.

●T: If LTIM is 1, then the 8259A will operate in the level interrupt mode. Edge
detect logic on the interrupt inputs will be disabled.

●ADI: CALL address interval. ADI = 1 then interval = 4; ADI e 0 then interval e
8.

●SNGL: Single. Means that this is the only 8259A in the system. If SNGL = 1 no
ICW3 will be issued.

IC4: If this bit is set ICW4 has to be read. If ICW4 is not needed, set IC4 = 0.
●
ICW 2
 ICW 3
This word is read only when there is more than one 8259A in the system and cascading is used, in
which case SNGL e 0. It will load the 8-bit slave register.
The functions of this register are:
● a. In the master mode (either when SP = 1, or in buffered mode when M/S = 1 in ICW4) a ``1''
is set for each slave in the system. The master then will release byte 1 of the call sequence
(for MCS- 80/85 system) and will enable the corresponding slave to release bytes 2 and 3 (for
8086 only byte 2) through the cascade lines.
● b. In the slave mode (either when SP e 0, or if BUF e 1 and M/S e 0 in ICW4) bits 2±0 identify
the slave. The slave compares its cascade input with these bits and, if they are equal, bytes 2
and 3 of the call sequence (or just byte 2 for 8086) are released by it on the Data Bus. d only
when there is more than one 8259A in the system and cascading is used, in which
If BUF=0,M/S is to be neglected.
Programmable Interval
Timer 8253
●The Intel 8253 is a programmable counter /
timer chip designed for use as an Intel
microcomputer peripheral. It uses N-MOS
technology with a single +5V supply and is
packaged in a 24-pin plastic DIP.
●It is organized as 3 independent 16-bit
counters, each with a counter rate up to 2 MHz .
All modes of operation are software
programmable.
●Clock This is the clock input for the counter.
The counter is 16 bits. The maximum clock
frequency is 1 / 380 nanoseconds or 2.6
megahertz. The minimum clock frequency is DC
or static operation.
●Out This single output line is the signal that is
the final programmed output of the device.
Actual operation of the out line depends on how
the device has been programmed.
●Gate This input can act as a gate for the clock
input line, or it can act as a start pulse,
depending on the programmed mode of the
counter.
Block diagram of 8253
Data Bus Buffer :
●This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to the
system data bus. The Data bus buffer has three basic functions.
1. Programming the modes of 8253/54.
2. Loading the count registers.
3. Reading the count values.
Read/Write Logic : The Read/Write logic has five signals : RD, WR, CS and the
●address lines A0 and A1. In the peripheral I/O mode, the RD, and WR signals are
connected to IOR and IOW, respectively. In memory-mapped I/O, these are connected
to MEMR and MEMW. Address lines A0 and A1 of the CPU are usually connected to
lines A0 and A1 of the 8253/54, and CS is tied to a decoded address. The control word
register and counters are selected according to the signals on lines A0 and A1.
Control Word Register :

This register is accessed when lines A0 and A1 are at logic 1. It is

used to write a command word which specifies the counter to be used
(binary or BCD), its mode, and either a read or write operation.

Counters :
These three functional blocks are identical in operation. Each counter
●consists of a single, 16 bit, pre-settable, down counter. The counter can

operate in either binary or BCD and its input, gate and output are configured
by the selection of modes stored in the control word register. The counters
are fully independent. The programmer can read the contents of any of the
three counters without disturbing the actual count in process.
Programming the 8253/54 :
●Each counter of the 8253/54 is individually programmed by writing a control word
into the control word register (A0 - A1 = 11).
WRITE Operation :

1. Write a control word into control register.

2. Load the low-order byte of a count in the counter register.
3. Load the high-order byte of count in the counter register.

READ Operation :
In some applications, especially in event counters, it is necessary to read the
value of the count in process. This can be done by two possible methods:
1.Simple Read :
It involves reading a count after inhibiting the counter by controlling the
gate input or the clock input of the selected counter, and two I/O read operations are
performed by the CPU. The first I/O operation reads the low-order byte, and the
second I/O operation reads the high order byte.
2. Counter Latch Command :
In the second method, an appropriate control word is written into the
control register to latch a count in the output latch, and two I/O read operations are
performed by the CPU. The first I/O operation reads the low-order byte, and the
second I/O operation reads the high order byte.
 MODES OF 8253
● Mode 0 : Interrupt on terminal count
● MODE 1 : Hardware Retrigger able One-shot
● MODE 2 : Rate generator
● MODE 3 : Square Wave Rate Generator
● MODE 4 : Software Triggered Strobe.
● MODE 5 : Hardware triggered strobe (Retrigger able).
 Mode 0 : Interrupt on terminal count

● 1) The output will be initially low after the mode set operation.
● 2) After the count is loaded into the selected count Register the output
will remain low and the counter will count.
● 3) When the terminal count is reached the output will go high and
remain high until the selected count is reloaded.
● 1)Gate = 1 enables counting.
● 2) Gate = 0 disables counting.
Operating Modes of 8254
Mode 0: Interrupt on terminal count
N=5

5 4 3 2 1 0

CLK
___
WR

GATE=1
OUT

N Clock Cycles

1. The GATE is held high.

2. When the count is written into the count register (CR) it will be loaded into the
count element (CE) in the next CLK pulse, and count down gets triggered. The
OUT goes low .
3. When the terminal count reaches (i.e., the count is zero), the OUT goes high.
4. If a new count is written to the count register, it will be loaded on the next CLK
pulse and counting will continue from the new count. This allows the counting
sequence to be synchronized by software
 MODE 1 : Hardware Retrigger able One-shot

a) Normal operation
1) The output will be initially high
2) The output will go low on the CLK pulse following the rising edge at the
gate input.
3) The output will go high on the terminal count and remain high until the
next rising edge at the gate input.
b) Retriggering
The one shot is retrigger able, hence the output will remain low for the
full count after any rising edge of the gate input.
c) New count
If the counter is loaded during one shot pulse, the current one shot is not
affected unless the counter is retriggered. If retriggered, the counter is
loaded with the new count and the one-shot pulse continues until the
new count expires.
Mode 1: Hardware Retriggerable One Shot
N=5

5 4 3 2 1 0

CLK
___
WR

GATE

OUT

N Clock Cycles

1. The GATE is initially low.

2. The count is written into the count register (CR). It will be loaded into the count
element (CE) when the GATE is made high, and count down gets triggered. The
OUT goes low.
3. When the terminal count reaches (i.e., the count is zero), the OUT goes high.
4. The one-shot pulse can be repeated at any time without rewriting the same count
into the counter by making the GATE 0-to-1 transition. This allows the counting
sequence to be synchronized by GATE hardware.
 MODE 2 : Rate generator
This mode functions like a divide by-N counter.
a) Normal Operation
1) The output will be initially high.
2) The output will go low for one clock pulse before the terminal count.
3) The output then goes high, the counter reloads the initial count and the
process is repeated.
4) The period from one output pulse to the next equals the number of input
counts in the count register.
b) Gate Disable
1) If Gate = 1 it enables a counting otherwise it disables counting (Gate = 0 ).
2) If Gate goes low during an low output pulse, output is set immediately
high. A trigger reloads the count and the normal sequence is repeated.
c) New count The current counting sequence does not affect when the new
count is written. If a trigger is received after writing a new count but
before the end of the current period, the new count will be loaded with
the new count on the next CLK pulse and counting will continue from the
new count. Otherwise, the new count will be loaded at the end of the
current counting cycle.
Mode 2: Periodic Interval Timer
N=4 reload reload
(4) (4)
4 3 2 1 0 3 2 1 0 3

CLK
___
WR

GATE=1
OUT

1 Clock Cycle 1 Clock Cycle

1. The GATE is held high.

2. When the count is written into the count register (CR) it will be loaded into the
count element (CE) in the next CLK pulse, and count down gets triggered. The
OUT goes high (or maintained at high if already high).
3. When the count reaches 1, the OUT goes low, and it goes high when the count
becomes 0. The count will get auto-reloaded and the cycle repeats.
4. The OUT is high for N-1 cycles and low for 1 cycle.
5. It is used as rate generator or divide-by-N counter.
Mode 3 Square Wave Rate Generator
a)Normal operation
1) Initially output is high.
2) For even count, counter is decremented by 2 on the falling edge of each clock pulse. When the
counter reaches terminal count, the state of the output is changed and the counter is reloaded
with the full count and the whole process is repeated.
3) If the count is odd and the output is high the first clock pulse (after the count is loaded)
decrements the count by 1. Subsequent clock pulses decrement the clock by 2. After timeout,
the output goes low and the full count is reloaded. The first clock pulse (following the reload)
decrements the count by 3 and subsequent clock pulse decrement the count by two. Then the
whole process is repeated. In this way, if the count is odd, the output will be high for (n+1)/2
counts and low for (n-1)/2 counts.
b) Gate Disable
If Gate is 1 counting is enabled otherwise it is disabled. If Gate goes low while output
is low, output is set high immediately. After this, When Gate goes high, the counter is loaded
with the initial count on the next clock pulse and the sequence is repeated.
c) New Count
The current counting sequence does not affect when the new count is written. If a
trigger is received after writing a new count but before the end of the current half-cycle of the
square wave, the counter will be loaded with the new count on the next CLK pulse and counting
will continue from the new count. otherwise, the new count will be loaded at end of the current
half-cycle.
Mode 3: Square Wave Generator
N=4 reload reload
(4) (4)
4 3 2 1 0 3 2 1 0 3

CLK
___
WR

GATE=1
OUT

N/2 Clock Cycles N/2 Clock Cycles

1. The GATE is held high.

2. When the count is written into the count register (CR) it will be loaded into the
count element (CE) in the next CLK pulse, and count down gets triggered. The
OUT goes high (or maintained at high if already high).
3. When the count reaches N/2, the OUT goes low, and it goes high when the count
becomes 0. The count will get auto-reloaded and the cycle repeats.
4. The OUT is high for N/2 cycles and low for N/2 cycle when N is even; and when N
is odd the OUT is high for (N+1)/2 cycles and low for (N-1)/2 cycles.
5. It is used as Baud rate generator.
 MODE 4 : Software Triggered Strobe
a) Normal operation
1) The output will be initially high
2) The output will go low for one CLK pulse after the terminal count (TC).
3) And become high again
b) Gate Disable
●If Gate is one the counting is enabled otherwise it is disabled. The Gate has

no effect on the output.

c) New count
●If a new count is written during counting, it will be loaded on the next CLK

pulse and counting will continue from the new count. If the count is two byte
then
1) Writing the first byte has no effect on counting.
2) Writing the second byte allows the new count to be loaded on the next CLK
pulse.
Mode 4: Software Triggered Strobe
N=5

5 4 3 2 1 0

CLK
___
WR

GATE=1
OUT

N Clock Cycles 1 Clock

Cycle
1. The GATE is held high.
2. When the count is written into the count register (CR) it will be loaded into the
count element (CE) in the next CLK pulse, and count down gets triggered. The
OUT goes high (or maintained at high if already high).
3. When the terminal count reaches (i.e., the count is zero), the OUT goes low for
one clock period.
4. If a new count is written to the count register, it will be loaded on the next CLK
pulse and counting will continue from the new count. This allows the counting
sequence to be `retriggered‘ (synchronized) by software.
 MODE 5 : Hardware triggered strobe
Retriggerable
a) Normal operation
●1) The output will be initially high.
●2) The counting is triggered by the rising edge of the Gate.
●3) The output will go low for one CLK pulse after the terminal count (TC).
b) Retriggering
If the triggering occurs on the Gate input during the counting, the initial
count is loaded on the next CLK pulse and the counting will be continued until the
terminal count is reached.
●c) New count
● If a new count is written during counting, the current counting sequence will
not be affected. If the trigger occurs after the new count is written but before the
terminal count, the counter will be loaded with the new count on the next CLK pulse
and counting will continue from there.
Mode 5: Hardware Triggered Strobe
N=5

5 4 3 2 1 0

CLK
___
WR

GATE
OUT

N Clock Cycles 1 Clock

Cycle
1. The GATE is initially low.
2. The count is written into the count register (CR). It will be loaded into the count
element (CE) when the GATE is made high, and count down gets triggered. The
OUT goes high (or maintained at high if already high).
3. When the terminal count reaches (i.e., the count is zero), the OUT goes low for
one clock period.
4. The above operation can be repeated at any time without rewriting the same
count into the counter by making the GATE 0-to-1 transition. This allows the
counting sequence to be synchronized (retriggered) by GATE hardware.
Programming Example:
Consider an 8254 interfaced with digital clock hardware as shown in Figure below.
1. In which mode the 8254 has to operate.
2. What is the count value required
3. Determine the control word required
4. And develop a program to generate the clock signal required.

1. Mode 3 (square wave generator)

2. Count= OUT 0 / CLK 0 input = = 2000 Decimal
= 07D0 H
3. Control word= 0 0 1 1 x 1 1 0=36h
4. Program
MOV DX, CON_REG_Address
MOV AL, 00110110B // control word
OUT DX,AL
MOV DX, COUNTER_0_Address
MOV AL, D0H // low byte of count
OUT DX,AL
MOV AL, 07H // high byte of count
OUT DX,AL
The 8253 cloak frequency is 1 MHz
MODE SET REGISTERS:
●It is a write only registers.
●It is used to set the operating modes.
●This registers is programmed after initialization of
DMA channel.
STATUS REGISTERS:
● It is read only registers.
● It is tell the status of DMA channels
● TC status bits are set when TC signal is activated for that channel.
● Update flag is not affected during read operation.
● The UP bit is set during update cycle . It is cleared after completion of
update cycle.
 Modes of Operation
● Rotating priority Mode:
● The priority of the channels has a circular sequence.
● Fixed Priority Rotating Mode:
● The priority is fixed.
● TC Stop Mode
● Auto Load mode
● Extended Write mode