STA INTRODUCTION

 What is STA?
 Static Timing Analysis (also referred as STA) is one of the many techniques
available to verify the timing of a digital design
 The STA is static since the analysis of the design is carried out statically and does
not depend upon the data values being applied at the input pins.
 WHY STA?
 Static timing analysis provides a faster and simpler way of checking and
analyzing all the timing paths in a design for any timing violations.

STA INTRO & WHY STA

DIFF BTW STA & DTA

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 INPUTS AND OUTPUTS OF STA

SDF

SDC

STATIC
.LIB TIMING TIMING REPORTS
ANALYSIS

SPEF

GATE LEVEL NETLIST

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 STA Flow
Inputs constraints

Perform STA

IF
NOT MET
Timing constraints
met??

Check for
optimized power

Timing reports
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 STA CHECKS IN ASIC FLOW

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 CLOCK
• A digital clock signal is basically a square
wave
• Generated by an oscillator
• Used to avoid glitches.

GLITCHES
• Glitch is an unwanted short pulse (unpredictable
output).
• If glitches are not eliminated, they will go to the
next stage of the circuit and generate more
unpredictable results.

CLASSIFICATION OF CLOCK
There are two types of clock: SYNC & ASYNC CLOCKS
1. SYNCHRONOUS CLOCK
2. ASYNCHRONOUS CLOCK

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 CLOCK JITTER
From cycle to cycle, the period and duty-cycle can
change slightly due to clock generation circuitry. This is
known as clock jitter.

CLOCK SKEW
The clock signal arrives at different components at different
times because of clock trees and buffers. The difference in
clock arrival times is known as clock skew

UNCERTAINITY
Uncertainty in the arrival of your clock edges adds pessimism to your design requirements. Thus a
combination of clock jitter and clock skew is used as a value for clock uncertainty.
Clock Uncertainty = Clock jitter + Worst clock skew (setup)
Clock Uncertainty = 0 + Best Clock Skew (Hold)

SKEW AND ITS TYPES What will be the impact of positive skew on
SKEW JITTER UNCERTAINITY the maximum operating frequency of
design?
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 LATENCY

SOURCE LATENCY
set_clock_latency 1.9 -source
[get_clocks SYS_CLK]

NETWORK LATENCY
set_clock_latency 0.8 [get_clocks
CLK_CONFIG]

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 TIMING ARC
• Timing Arc is defined as the path traversed by a Signal from the Input Pin of a Cell to its
Output Pin.
• For a Cell, there can be more than one Timing Arc
• Using the information of different Timing Arcs that exists for a Cell, we can calculate the
delay for each path that will help in Timing Analysis and Optimization.

Timing Arc

Cell Arc Net Arc

Combinational Arc Sequential Arc

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 CELL ARC
CELL ARCS
It is defined as a path traversed by a signal from the Input/Source pin of a
cell to the output/sink pin of the cell. It is of two types:

• COMBINATIONAL ARCS
The path is traversed by a Signal from Input Pin to Output Pin of a
combination cell.

• SEQUENTIAL ARCS
The path is traversed by a Signal from Clock Pin to the Output Pin or Clock
Pin to the Input Pin of a sequential cell.

NET ARC
The arc between the output pin of a cell and input pin of
another cell is known as Net Arcs
Net Arcs constitute to delay in the timing path this is the
reason why net arcs are always Delay Timing Arcs

TIMING ARC
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 STA
TERMINOLOGY

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 STA TERMINOLOGY

PULSE
DELAY SLEW STA TERMINOLOGY 1
WIDTH

COMMON CLOCK
CPPR STA TERMINOLOGY 2
PATH

TIMING DERATE CRPR STA TERMINOLOGY 3

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Setup time is the minimum amount of time the data signal should be held steady
before the clock event so that the data are reliably sampled by the clock.
Setup time Requirement = Required time – Arrival time
Hold time is the minimum amount of time the data signal should be held steady
after the clock event so that the data are reliably sampled. (independent of clock)
Hold time Requirement = Arrival time – Required time

SETUP & HOLD ADJUSTMENT

 EQUATIONS FOR ARRIVAL AND REQUIRED TIME
ARRIVAL TIME (AT) IS THE DATA PATH
REQUIRED TIME (RT) IS THE CLOCK PATH

SETUP: RT – AT
AT = T(launch) + T (CK to Q) + T (combo)
RT = T(capture) + T(clock period) - T(setup) – T(setup uncertainty) + CPPR

HOLD: AT - RT
AT = T(launch) + T (CK to Q) + T (combo)
RT = T(capture) + T(hold) + T(hold uncertainty) - CPPR

EQUATION OF SETUP & HOLD

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 CALCULATE THE SETUP AND HOLD TIME
FOR THE ABOVE DIAGRAM AND SAY
WHICH IS VIOLATED ?
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 OBSERVE BOTH THE
DIAGRAM FIRST
WHAT HAPPENS IF THE DIAGRAM 1
(TOP ONE) IS CHANGED TO DIAGRAM 2
(BOTTOM ONE)
WILL ANY VIOLATION OCCUR?

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 CELL DELAY
Each cell has one or more timing arcs, and every timing arc has a propagation delay.
Propagation delay is the time difference from the time when the input signal changes state to
the time when the output signal changes state. This is commonly referred to as cell delay.
Delay through a cell is determined by:
• The intrinsic delay
• The load that it is driving
• The input transition, also known as input slew

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 Types of cell delay

Transition is the time it takes for the pin to change state from low to high or high to low.

Intrinsic delay is defined as the delay in a cell when a signal with zero transition time is applied to
the input pin, and the output pin does not have any load.

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 TIME TAKEN FROM A TO B IS STA
S TA = A + X + D 1 + Y + D 2 + Z + B
X Y Z

OUTPUT
PORT
INPUT
PORT

U1 U2

A B

D1 D2

X , Y ,Z NET DELAY
D1 , D2 CELL DELAY
 IS IT USER INPUT OR TOOL CALCULATED??

POINTS USER INPUT / TOOL CALCULATED Tool calculated :

A,B User input [already exist] • Depending upon no. of driver and
X,Y,Z Tool Calculated
driver strength.
• How close is it with the source
D1 , D2 Tool Calculated
 HOW ARE THESE DELAY CALCULATED ?

PATHS DETAILS FILES WHERE IT IS

A,B SDC [Synopsis Design Constraint] .sdc
Constraint means condition , here the condition is given by the
user/client/spec.
X,Y,Z SPEF [Standard Parasitic Exchange Format ] .spef
Wire delay, net delay ,RC delay, interconnect delay
Parasitic indicates RLC, simplified RC
D1 , D2 Cell delay or internal cell delay .lib
U1 , U2 U1 , U2 = Cell (transistor)
A cell has delay and it consumes energy also ,it is called cell delay [comes from .lib]
 LIST THE PARAMETERS ON
WHICH CELL AND NET DELAY
WILL DEPEND?

WHAT HAPPENS WHEN

THERE ARE EXCESSIVE
DELAYS BETWEEN TWO
ASYNCHRONOUS CLOCKS?
STA MODES

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 GBA PBA

• Graph Based Analysis • Path Based Analysis

• Worst delay /slew is used in • Actual path specific
every cell delay/slew in every cell
• Pessimistic • Less pessimistic
• STA tool takes less time to • STA tool takes more time to
run (faster) run (slower)
• Less Accurate • Accurate

What analysis we use ? GBA OR PBA why?

If timing met in GBA is better or if timing met in PBA is better ?

GBA & PBA

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 ON CHIP VARIATION ADVANCED ON CHIP VARIATION PARAMETRIC ON CHIP VARIATION
• In OCV we need to add some • In case of OCV constant derates are • Below 10nm technologies AOCV cannot
pessimism in the timing of applied across the timing path. reduce pessimism hence to reduce the
standard cells. • In AOCV we multiply cell and wire pessimism at lower technology nodes
• We basically apply ±x% of delays with different derate factors POCV was introduced.
additional delay to all the depending on the distance and depth. • Here cell delay is calculated based on
standard cells which is called • AOCV is represented by a two delay variation of cell, delay variation
OCV derate. dimensional table: the derate value of a denoted by sigma and delay is denoted
• A fixed timing derate (OCV cell is determined by logic depth and by u.
Derate) factor is applied to the distance. • POCV models a cell delay using
delay of all the cells present in • For smaller path depths OCV gives Gaussian distribution directly, instead of
the design. optimistic results when compared to adding a derate value.
• By applying OCV, if any process AOCV. • Cell delay is calculated from a
variation affects the delay of any • For larger path depths OCV tends to be parameter, which is extracted from either
cells during the fabrication, it will more pessimistic than AOCV (AOCV library, or POCV table.
not affect the timing requirements gives accurate values).
and the chip will not fail after
fabrication.

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OCV AOCV SOCV
 TIMING PATHS

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 INPUT TO REGISTER

INPUT PORT

set_input_delay -clock [get_clocks <clk_name>

-add_delay <value> [get_ports <input_ports>]
INPUT TO REG
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 SDC CONSTRAINTS

create_clock -name VIRTUAL_CLKM -period 10 -waveform {0 5}

set_driving_cell -lib_cell BUFF \ -library lib013lwc [get_ports INA]

set_input_delay -clock VIRTUAL_CLKM \ set_input_delay -clock VIRTUAL_CLKM \

-max 2.55 [get_ports INA] -min 1.1 [get_ports INA]

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 REPORTS

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 REGISTER TO REGISTER
Combo
D1 Q1 Logic D2 Q2

F1 F2

CLK CK1 CK2

create_clock –name <clock_name> -period <value>

-waveform { } [get_ports <port_name>]

REG TO REG
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 SDC CONSTRAINTS

create_clock -name CLKM -period 10 -waveform {0 5} \

[get_ports CLKM]
set_clock_uncertainty -setup 0.3 [all_clocks]
set_clock_uncertainty -hold 0.5 [all_clocks]
set_clock_transition -rise 0.2 [all_clocks]
set_clock_transition -fall 0.15 [all_clocks]
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 WAVEFORM FOR TIME ANALSYSIS

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REPORTS
 REGISTER TO OUTPUT

set_output_delay -clock [get_clocks <clk_name> -

add_delay <value> [get_ports <output_ports>]
REG TO OUT
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 SDC CONSTRAINTS

set_load 0.02 [get_ports ROUT]

set_output_delay -clock VIRTUAL_CLKP \ set_output_delay -clock VIRTUAL_CLKP \

-max 5.1 [get_ports ROUT] -min 2.5 [get_ports ROUT]

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 REPORTS

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 INPUT TO OUTPUT

Input to output port through purely combinational logic.

set_max_delay →setup
set_min_delay →hold

SLACK FOR IN2REG , REG2OUT & IN2OUT

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 SDC CONSTRAINTS

set_output_delay -clock VIRTUAL_CLKM \ set_input_delay -clock VIRTUAL_CLKM \

-min 3.2 [get_ports POUT] -max 3.6 [get_ports INB]
set_input_delay -clock VIRTUAL_CLKM \ set_output_delay -clock VIRTUAL_CLKM \
-min 1.8 [get_ports INB] -max 5.8 [get_ports POUT]

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 REPORTS

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1. Which type of violation
does not depend upon
frequency of operation?

2. If a higher frequency is
applied than the calculated
max frequency of
operation, which violation
may come?

3. What type of designs are

prone to hold and setup
violation?
CLOCK DOMAIN CROSSING
CDC PART-1
CDC PART-2

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 SLOW TO FAST CLOCK

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 SLOW TO FAST CLOCK

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 SLOW TO FAST CLOCK

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 SLOW TO FAST CLOCK

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 FAST TO SLOW CLOCK

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 FAST TO SLOW CLOCK

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 STATIC
TIMING
ANALYSIS

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TIMING EXCEPTIONS
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 FALSE PATH
Path that never can be timed properly in actual circuit . we should avoid false path to save optimization

set_false_path -from [get_clocks clk1] -to [get_clocks clk2]

set_false_path -from regA -to regB FALSE PATH WITH EXAMPLE
FALSE PATH WITH CONSTRAINT
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 HALF CYCLE PATH
If a design has both negative edge triggered flip flop and positive edge triggered flip flop then there
exist half cycle path. The path can be from rising edge flip flop to falling edge flip flop

HALF CYCLE PATH WITH EXAMPLE

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 MULTICYCLE PATH
STA assumes all timing path will meet timings in one cycle , the paths that requires more than one
clock period of execution is called multicycle path

SETTING MULTICYCLE PATH

FOR SETUP

MCP WITH EXAMPLE

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 SETTING MULTICYCLE PATH
FOR HOLD

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 PROBLEMS

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Problem:

Setup timing Analysis Example

Clock Period = 1ns, Max_Combo_delay =
650ps, clock-to-q_delay = 120ps,
CkBuf_max_dealy = 25ps, CkBuf_min_dealy
= 15ps Tsu 180ps, Ts = 150ps
Setup Analysis:
Arrival time = Tlaunch + Tcq + Tcombo
Required time = Tcapture+ Tclk - Tsu - Ts + CPPR
RT = (25)*3 + 1000 - 180 - 150 + (25-15)*2
75 + 1000 – 180 -150 = 765
AT = (25)*3 + 120 + 650
75 + 120 + 650 = 845
Slack = RT - AT = 765 - 845
= -80 ps
Ways for setup fixing:
Setup Violations
P1: Vt Swap: Change to lower Vt cell
P1: Cell upsizing
P2: No Effect
P3: Decrease the delay (Early Clocking/Pull clock)
P4: Increase the delay (Late Clocking/push clock)
Problem:

Min_Combo_delay = 200ps, Tcq = 40 ps,

CkBuf_max_dealy =25ps, CkBuf_min_dealy =
Hold timing Analysis Example
15ps, THU 60ps, Thold = 140ps
Hold Analysis:
Arrival time = Tlaunch + Tcq + Tcombo
Required time = Tcapture + Thold + Thu - CPPR
AT = (15)*3 + 40 + 200
AT = 45 + 40 + 200 = 285
RT = (15)*5 + 140 + 60 + (25-15)*2
RT = 75 + 140 + 60 + 20 = 295
Slack = AT – RT = -10 ps
For fixing:
Hold Violations
P1: Buffer/delay cell addition
P1: Vt swap (higher Vt) or cell downsizing
P2: No Effect
P3: Increase the delay (Late Clocking/push
clock)
P4: Decrease the delay (Early Clocking/ pull
clock)
 Clock Period = 1.5ns , Max_Combo_delay = 850ps , clk-to-q_delay = 220ps ,
CkBuf_max_dealy = 40ps,
CkBuf_min_dealy = 23ps
Tsu 200ps, Ts = 170ps
Thu 100ps, Thold = 180ps
CALCULATE THE SETUP & HOLD TIME

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 PROBLEMS WITH DERATE AND CPPR
FOR SETUP
FOR HOLD

CALCULATE THE SETUP AND HOLD WITH DERATE AND WITHOUT DERATE

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THANK YOU

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