NCP4894

Audio Power Amplifier,

1.8 Watt, with Selectable
Shutdown
The NCP4894 is a differential audio power amplifier designed for
portable communication device applications. This feature and the http://onsemi.com
excellent audio characteristics of the NCP4894 are a guarantee of a
high quality sound, for example, in mobile phones applications. With a
MARKING
10% THD+N value the NCP4894 is capable of delivering 1.8 W of
DIAGRAMS
continuous average power to an 8.0 W load from a 5.5 V power
supply. With the same load conditions and a 5.0 V battery voltage, it
9−PIN FLIP−CHIP A3
ensures 1.0 W to be delivered with less than 0.01% distortion. xxxG
FC SUFFIX
The NCP4894 provides high quality audio while requiring few AYWW
1 CASE 499AL
external components and minimal power consumption. It features a C1
low−power consumption shutdown mode. A1
To be flexible, shutdown may be enabled by either a logic high or
low depending on the voltage applied on the SD MODE pin.
The NCP4894 contains circuitry to prevent from “pop and click” Micro−10 xxxx
noise that would otherwise occur during turn−on and turn−off 8 DM SUFFIX AYWG
transitions. CASE 846B G
For maximum flexibility, the NCP4894 provides an externally 1
controlled gain (with resistors), as well as an externally controlled turn
−on time (with bypass capacitor).
Due to its excellent PSRR, it can be directly connected to the DFN10 1
MN SUFFIX xxx
battery, saving the use of an LDO.
CASE 485C ALYWG
This device is available in 9−Pin Flip−Chip, Micro−10 and DFN10 G
1
3x3 mm packages.
Features xxxx = Specific Device Code
• Differential Amplification A = Assembly Location
• Shutdown High or Low Selectivity L
Y
= Wafer Lot
= Year
• 1.0 W to an 8.0 W Load from a 5.0 V Power Supply W, WW = Work Week
• Superior PSRR: Direct Connection to the Battery G = Pb−Free Package
• “Pop and Click” Noise Protection Circuit (Note: Microdot may be in either location)

• Ultra Low Current Shutdown Mode

• 2.2 V−5.5 V Operation ORDERING INFORMATION
• External Gain Configuration Capability See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
• External Turn−on Configuration Capability
• Thermal Overload Protection Circuitry
• Pb−Free Packages are Available
Typical Applications
• Portable Electronic Devices
• PDAs
• Mobile Phones

© Semiconductor Components Industries, LLC, 2007 1 Publication Order Number:

January, 2007 − Rev. 9 NCP4894/D
 NCP4894

Rf1

20 kW
VP

Cs 1 mF

Ci1 Ri1 VP
Negative Diff INM
− OUTA
Input from DAC 390 nF 20 kW +
BYPASS
VP

BYPASS
VMC
Cb BRIDGE
1 mF
RL
SHUTDOWN CONTROL 8W
SD MODE SD SELECT Status SD SELECT
0 0 Shutdown SHUTDOWN
0 1 On CONTROL
1 0 On
1 1 Shutdown SD MODE
Ci2 Ri2 BYPASS + OUTB
Positive Diff INP
−
Input from DAC
390 nF 20 kW VM

20 kW

Rf2

Figure 1. Typical NCP4894 Application Circuit with Differential Input

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 NCP4894

Rf2

20 kW
VP

Cs 1 mF

VP
Ci1 Ri1
Left Channel INM Co1
− OUTA 32W
Input
390nF 20 kW BYPASS + /
47uF
16W
VP

BYPASS
VMC
Cb 1 mF BRIDGE

Earpiece
SHUTDOWN CONTROL
SD MODE SD SELECT Status SD SELECT
0 0 Shutdown SHUTDOWN
0 1 On CONTROL
1 0 On SD MODE
1 1 Shutdown
Co2
Ci2 Ri2 BYPASS + 32W
Right Channel INP
− OUTB /
Input 47uF
390nF 20 kW 16W
VM

Rf1

20 kW
Figure 2. Typical NCP4894 Application Circuit for Driving Earpiece

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 NCP4894

PIN CONNECTIONS

9−Pin Flip−Chip Micro−10 DFN10

A1 A2 A3 SD SELECT 1 10 OUTA
SD SELECT 1 10 OUTA
INP BYPASS OUTB
INM 2 9 VP INM 2 9 VP
B1 B2 B3 SD MODE 3 8 NC
SD MODE 3 8 NC
VP SD MODE VM INP 4 7 VM
BYPASS 5 6 OUTB INP 4 7 VM
C1 C2 C3
(Top View) BYPASS 5 6 OUTB
INM SD SELECT OUTA
(Top View) (Top View)

PIN DESCRIPTION
9−Pin Flip−Chip Micro−10/DFN10 Type Symbol Description
A1 4 I INP Positive Differential Input
A2 5 O BYPASS Bypass Capacitor Pin which Provides the Common Mode Voltage
A3 6 I OUTB Negative BTL Output
B1 9 I VP Positive Analog Supply of the Cell
B2 3 I SD MODE Shutdown High or Low Selectivity (Note 1)
B3 7 I VM Ground
C1 2 I INM Negative Differential Input
C2 1 O SD SELECT (Note 1)
C3 10 I OUTA Positive BTL Output
1. The SD SELECT pin must be toggled to the same state as the SD MODE pin to force the device in shutdown mode.

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 NCP4894

MAXIMUM RATINGS (Note 2)

Rating Symbol Value Unit

Supply Voltage VP 6.0 V

Operating Supply Voltage Op VP 2.2 to 5.5 V −
Input Voltage Vin −0.3 to Vcc +0.3 V
Max Output Current Iout 500 mA
Power Dissipation (Note 3) Pd Internally Limited −
Operating Ambient Temperature TA −40 to +85 °C
Max Junction Temperature TJ 150 °C
Storage Temperature Range Tstg −65 to +150 °C
Thermal Resistance Junction−to−Air Micro−10 RqJA 200 °C/W
DFN 3x3 mm 70
9−Pin Flip−Chip (Note 4)

ESD Protection Human Body Model (HBM) (Note 5) − > 2000 V

Machine Model (MM) (Note 6) > 200
Latchup Current at TA = 85°C (Note 7) − 100 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C.
3. The thermal shutdown set to 160°C (typical) avoids irreversible damage on the device due to power dissipation. For further information see
page 7.
4. For the 9−Pin Flip−Chip CSP package, the RqJA is highly dependent of the PCB Heatsink area. For example, RqJA can equal 195°C/W with
50 mm2 total area and also 135°C/W with 500 mm2. For further information see page 10. The bumps have the same thermal resistance and
all need to be connected to optimize the power dissipation.
5. Human Body Model, 100 pF discharge through a 1.5 kW resistor following specification JESD22/A114.
6. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
7. Maximum ratings per JEDEC standard JESD78.

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 NCP4894

ELECTRICAL CHARACTERISTICS Limits apply for TA between −40°C to +85°C (Unless otherwise noted).
Min Max
Characteristic Symbol Conditions (Note 8) Typ (Note 8) Unit
Supply Quiescent Current Idd VP = 3.0 V, No Load − 1.9 − mA
VP = 5.0 V, No Load − 2.1 −

VP = 3.0 V, 8.0 W − 2.0 −

VP = 5.0 V, 8.0 W − 2.2 4.0

Common Mode Voltage Vcm − − VP/2 − V

Shutdown Current ISD For VP between 2.2 V to 5.5 V
SDM = SDS = GND
TA = 25°C − 20 600 nA
TA = −40°C to +85°C − − 2.0 mA
SD SELECT Threshold High VSDIH − 1.4 − − V
SD SELECT Threshold Low VSDIL − − − 0.4 V
Turning On Time (Note 10) TWU Cby = 1.0 mF − 140 − ms
Turning Off Time (Note 10) TSD − − 20 − ms
Output Swing Vloadpeak VP = 3.0 V, RL = 8.0 W − 2.5 − V
VP = 5.0 V, RL = 8.0 W (Note 9) V
TA = 25°C 4.0 4.3 −
TA = −40°C to +85°C 3.85 − −

Rms Output Power PO VP = 3.0 V, RL = 8.0 W − 0.39 − W

THD + N < 0.1%
VP = 3.3 V, RL = 8.0 W − 0.48 −
THD + N < 0.1%
VP = 5.0 V, RL = 8.0 W − 1.08 −
THD + N < 0.1%

Output Offset Voltage VOS For VP between 2.2 V −30 1.0 30 mV

to 5.5 V

Power Supply Rejection Ratio PSRR V+ G = 2.0, RL = 8.0 W dB

VPripple_pp = 200 mV
Cby = 1.0 mF
Input Terminated with 10 W

F = 217 Hz
VP = 5.0 V − −80 −
VP = 3.0 V − −80 −

F = 1.0 kHz
VP = 5.0 V − −85 −
VP = 3.0 V − −85 −
Efficiency h VP = 3.0 V, Porms = 380 mW − 64 − %
VP = 5.0 V, Porms = 1.0 W − 63 −

Thermal Shutdown Temperature Tsd − 160 − °C

Total Harmonic Distortion THD VP = 3.0 V, F = 1.0 kHz − − − %
RL = 8.0 W, AV = 2.0 − 0.007 −
PO = 0.32 W − − −

VP = 5.0 V, F = 1.0 kHz − − −

RL = 8.0 W, AV = 2.0 − 0.006 −
PO = 1.0 W − − −
8. Min/Max limits are guaranteed by design, test or statistical analysis.
9. This parameter is not tested in production for 9−Pin Flip−Chip CSP package in case of a 5.0 V power supply, however it is correlated based
on a 3.0 V power supply testing.
10. See page 12 for a theoretical approach of these parameters.

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 NCP4894

TYPICAL PERFORMANCE CHARACTERISTICS

0.100 0.100

VP = 5 V VP = 3 V
RL = 8 W RL = 8 W
Pout = 400 mW Pout = 250 mW
THD+N(%)

THD+N(%)
0.010 0.010

0.001 0.001
10 100 1000 10000 100000 10 100 1000 10000 100000
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 3. THDN versus Frequency Figure 4. THDN versus Frequency

0.100 0.100

VP = 2.6 V VP = 3.6 V
RL = 8 W RL = 4 W
Pout = 150 mW Pout = 300 mW
THD+N(%)

THD+N(%)

0.010 0.010

0.001 0.001
10 100 1000 10000 100000 10 100 1000 10000 100000
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 5. THDN versus Frequency Figure 6. THDN versus Frequency

10 10

VP = 5 V VP = 3 V
1 RL = 8 W 1 RL = 8 W
f = 1 kHz f = 1 kHz
THD+N(%)

THD+N(%)

0.1 0.1

0.01 0.01

0.001 0.001
0 200 400 600 800 1000 1200 0 100 200 300 400 500
OUTPUT POWER (mW) OUTPUT POWER (mW)

Figure 7. THDN versus Output Power Figure 8. THDN versus Output Power

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 NCP4894

TYPICAL PERFORMANCE CHARACTERISTICS

10 10

VP = 2.6 V VP = 3.6 V
1 RL = 8 W 1 RL = 4 W
f = 1 kHz f = 1 kHz

THD+N(%)
THD+N(%)

0.1 0.1

0.01 0.01

0.001 0.001
0 100 200 300 0 200 400 600 800 1000
OUTPUT POWER (mW) OUTPUT POWER (mW)

Figure 9. THDN versus Output Power Figure 10. THDN versus Output Power

2000 0
RL = 8 W VP = 5 V
1800 −10
f = 1 kHz RL = 8 W
1600 −20
OUTPUT POWER (mW)

Vripple = 200 mV pk−pk

1400 −30 Inputs grounded with 10 W
Av = 1
PSSR(dB)

1200 THD+N = 10% −40

Cb = 1 mF
1000 −50
800 THD+N = 1% −60
600 −70
400 −80
200 −90
0 −100
2.5 3.0 3.5 4.0 4.5 5.0 5.5 100 1000 10000 100000
POIWER SUPPLY (V) FREQUENCY (Hz)

Figure 11. THDN versus Output Power Figure 12. PSRR @ VP = 5 V

0 0
−10 VP = 3 V −10 VP = 2.2 V
RL = 8 W RL = 8 W
−20 −20
Vripple = 200 mV pk=pk Vripple = 200 mV pk−pk
−30 Inputs grounded with 10 W −30 Inputs grounded with 10 W
Av = 1 Av = 1
PSSR(dB)

PSSR(dB)

−40 −40
Cb = 1 mF Cb = 1 mF
−50 −50
−60 −60
−70 −70
−80 −80
−90 −90
−100 −100
100 1000 10000 100000 100 1000 10000 100000
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 13. PSRR @ VP = 3 V Figure 14. PSRR @ VP = 2.2 V

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 NCP4894

TYPICAL PERFORMANCE CHARACTERISTICS

0 0
−10 VP = 3 V −10 VP = 3 V
RL = 8 W RL = 8 W
−20 −20 Vripple = 200 mV pk−pk
Vripple = 200 mV pk−pk
−30 Inputs grounded with 10 W −30 Inputs grounded with 10 W
Av = 1

PSRR(dB)
PSSR(dB)

−40 −40 Av = 5
−50 −50
−60 Cb = 4.7 mF −60
−70 Cb = 1 mF −70
−80 −80
Av = 1
−90 −90
Cb = 0.47 mF
−100 −100
100 1000 10000 100000 100 1000 10000 100000
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 20. PSRR versus Cb @ VP = 3 V Figure 15. PSRR versus Av @ VP = 3 V

−20 −20

VP = 5 V VP = 3 V
RL = 8 W RL = 8 W
−30 Av = 1 −30 Av = 1
Cb = 1 mF Cb = 1 mF
CMRR(dB)
CMRR(dB)

−40 −40

−50 −50

−60 −60
100 1000 10000 100000 100 1000 10000 100000
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 16. CMRR @ VP = 5 V Figure 17. CMRR @ VP = 3 V

−20 100
OUTPUT NOISE VOLTAGE (mVrms)

VP = 2.2V VP = 3.6 V
RL = 8 W RL = 8 W
Av = 1 Av = 1 NCP4894 ON
−30
Cb = 1 mF Cb = 1 mF
CMRR(dB)

−40 10
NCP4894 OFF

−50

−60 1
100 1000 10000 100000 10 100 1000 10000 100000
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 18. CMMR @ VP = 2.2 V Figure 19. Noise Floor @ VP = 3.6 V

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 NCP4894

TYPICAL PERFORMANCE CHARACTERISTICS

Ch1 = OUTA Ch1 = OUTA

Ch2 = OUTB Ch2 = OUTB
Ch3 = Shutdown & Ch3 = Shutdown &
Math1 = OUTA−OUTB Math1 = OUTA−OUTB
Figure 21. Turning−on Sequence Figure 22. Turning−on Sequence Zoom
@ VP = 5 V and f = 1 kHz @ VP = 5 V and f = 1 kHz

Ch1 = OUTA Ch1 = OUTA

Ch2 = OUTB Ch2 = OUTB
Ch3 = Shutdown & Ch3 = Shutdown &
Math1 = OUTA−OUTB Math1 = OUTA−OUTB
Figure 23. Turning−off Sequence Figure 24. Turning−off Sequence Zoom
@ VP = 5 V and f = 1 kHz @ VP = 5 V and f = 1 kHz

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 NCP4894

TYPICAL PERFORMANCE CHARACTERISTICS

0.7 0.3

PD, POWER DISSIPATION (W)

PD, POWER DISSIPATION (W)

0.6
0.25

0.5
0.2
0.4
0.15
0.3 VP = 5 V VP = 3.3 V
RL = 8 W RL = 8 W
F = 1 kHz 0.1
0.2 F = 1 kHz
THD + N < 0.1% THD + N < 0.1%
0.1 0.05

0 0
0 0.2 0.4 0.6 0.8 1 1.2 0 0.1 0.2 0.3 0.4 0.5
Pout, OUTPUT POWER (W) Pout, OUTPUT POWER (W)

Figure 25. Power Dissipation versus Output Figure 26. Power Dissipation versus Output
Power Power

0.25 0.4

0.35
PD, POWER DISSIPATION (W)

PD, POWER DISSIPATION (W)

0.2 RL = 4 W
0.3

0.25
0.15
VP = 3 V 0.2 RL = 8 W
RL = 8 W
0.1 0.15
F = 1 kHz
THD + N < 0.1%
0.1 VP = 2.6 V
0.05
F = 1 kHz
0.05
THD + N < 0.1%
0 0
0 0.1 0.2 0.3 0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Pout, OUTPUT POWER (W) Pout, OUTPUT POWER (W)

Figure 27. Power Dissipation versus Output Figure 28. Power Dissipation versus Output
Power Power

700 180
Maximum Die Temperature 150°C
PD, POWER DISSIPATION (mW)

AMBIENT TEMPERATURE 25°C

600 PCB Heatsink Area 160

DIE TEMPERATURE (°C) @

200 mm2
500 140 VP = 5 V
50 mm2 500 mm2
400 120
VP = 4.2 V
300 100

200 80 VP = 3.3 V
PDmax = 633 mW
100 for VP = 5 V, 60
RL = 8 W VP = 2.6 V
0 40
0 20 40 60 80 100 120 140 160 50 100 150 200 250 300
TA, AMBIENT TEMPERATURE (°C) PCB HEATSINK AREA (mm2)

Figure 29. Power Derating − 9−Pin Flip−Chip CSP Figure 30. Maximum Die Temperature versus
PCB Heatsink Area

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 NCP4894

APPLICATION INFORMATION
Detailed Description During the shutdown state, the DC quiescent current has a
The NCP4894 audio amplifier can operate under 2.6 V typical value of 10 nA.
until 5.5 V power supply. It delivers 320 mW rms output Current Limit Circuit
power to 4.0 W load (VP = 2.6 V) and 1.0 W rms output The maximum output power of the circuit
power to 8.0 W load (VP = 5.0 V). (Porms = 1.0 W, VP = 5.0 V, RL = 8.0 W) requires a peak
The structure of the NCP4894 is basically composed of current in the load of 500 mA.
two identical internal power amplifiers. Both are externally In order to limit the excessive power dissipation in the
configurable with gain−setting resistors Rin and Rf (the load when a short−circuit occurs between both outputs, the
closed−loop gain is fixed by the ratios of these resistors). current limit in the load is fixed to 800 mA.
The load is driven differentially through OUTA and OUTB
outputs. This configuration eliminates the need for an Thermal Overload Protection
output coupling capacitor. Internal amplifiers are switched off when the
temperature exceeds 160°C, and will be switched on again
Internal Power Amplifier only when the temperature decreases below 140°C.
The output PMOS and NMOS transistors of the amplifier The NCP4894 is unity−gain stable and requires no
were designed to deliver the output power of the external components besides gain−setting resistors, an
specifications without clipping. The channel resistance input coupling capacitor and a proper bypassing capacitor
(Ron) of the NMOS and PMOS transistors does not exceed in the typical application.
0.6 W when they drive current. Both internal amplifiers are externally configurable (Rf
The structure of the internal power amplifier is and Rin) with gain configuration.
composed of three symmetrical gain stages, first and The differential−ended amplifier presents two major
medium gain stages are transconductance gain stages to advantages:
obtain maximum bandwidth and DC gain. − The possible output power is four times larger (the
output swing is doubled) as compared to a single−ended
Turn−On and Turn−Off Transitions
amplifier under the same conditions.
A cycle with a turn−on and turn−off transition is
illustrated with plots that show both single ended signals on − Output pins (OUTA and OUTB) are biased at the same
potential VP/2, this eliminates the need for an output
the previous page.
coupling capacitor required with a single−ended
In order to eliminate “pop and click” noises during
amplifier configuration.
transitions, output power in the load must be slowly
The differential closed loop−gain of the amplifier is
established or cut. When logic high is applied to the
Rf V
shutdown pin, the bypass voltage begins to rise given by Avd + * + orms . Vorms is the rms value of
Rin Vinrms
exponentially and once the output DC level is around the
the voltage seen by the load and Vinrms is the rms value of
common mode voltage, the gain is established slowly
the input differential signal.
(20 ms). Using this turn−on mode, the device is optimized
Output power delivered to the load is given by
in terms of rejection of “pop and click” noises.
(Vopeak)2
A theoretical value of turn−on time at 25°C is given by Porms + (Vopeak is the peak differential
the following formula. 2 * RL
Cby: bypass capacitor output voltage).
R: internal 150 k resistor with a 25% accuracy When choosing gain configuration to obtain the desired
Ton = 0.95 * R * Cby output power, check that the amplifier is not current limited
The device has the same behavior when it is turned−off or clipped.
by a logic low on the shutdown pin. During the shutdown The maximum current which can be delivered to the load
Vopeak
mode, amplifier outputs are connected to the ground. is 500 mA Iopeak + .
However, to totally cut the output audio signal, you only RL
need to wait for 20 ms.

Shutdown Function
The device enters shutdown mode once the SD SELECT
and SD MODE pins are in the same logic state. This brings
flexibility to the design, as the SD MODE pin must be
permanently connected to VP or GND on the PCB. If the
SD SELECT pin is not connected to the output of a
microcontroller or microprocessor, it’s not advisable to let
it float. A pulldown or pullup resistor is then suitable.

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 NCP4894

Gain−Setting Resistor Selection (Rin and Rf) The size of the capacitor must be large enough to couple
Rin and Rf set the closed−loop gain of both amplifiers. in low frequencies without severe attenuation. However a
In order to optimize device and system performance, the large input coupling capacitor requires more time to reach
NCP4894 should be used in low gain configurations. its quiescent DC voltage (VP/2) and can increase the
The low gain configuration minimizes THD + noise turn−on pops.
values and maximizes the signal to noise ratio, and the An input capacitor value between 0.1 m and 0.39 mF
amplifier can still be used without running into the performs well in many applications (With Rin = 22 kW).
bandwidth limitations.
A closed loop gain in the range from 2 to 5 is Bypass Capacitor Selection (Cby)
recommended to optimize overall system performance. The bypass capacitor Cby provides half−supply filtering
An input resistor (Rin) value of 22 kW is realistic in most and determines how fast the NCP4894 turns on.
applications, and doesn’t require the use of a very large This capacitor is a critical component to minimize the
capacitor Cin. turn−on pop. A 1.0 mF bypass capacitor value
(Cin = < 0.39 mF) should produce clickless and popless
Input Capacitor Selection (Cin) shutdown transitions. The amplifier is still functional with
The input coupling capacitor blocks the DC voltage at a 0.1 mF capacitor value but is more susceptible to “pop and
the amplifier input terminal. This capacitor creates a click” noises.
high−pass filter with Rin, the cut−off frequency is given by Thus, a 1.0 mF bypassing capacitor is recommended.
fc + 1 .
2 * P * Rin * Cin

R4
J1 VP
20 kW
VP

C4 1 mF
GND

C2 R2 VP
INM
− OUTA
1 mF 20 kW BYPASS +
VP

BYPASS
VMC
C3 1 mF BRIDGE J3
J2 VP
RL
8W
100 kW R3 J5 J4
SD SELECT
SHUTDOWN
CONTROL
SD MODE
C1 R1 BYPASS + OUTB
INP
−
1 mF 20 kW VM

J10 20 kW

R5

Figure 31. Demonstration Board Schematic

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 NCP4894

Silkscreen Layer

Top Layer Bottom Layer

Figure 32. Demonstration Board for 9−Pin Flip−Chip CSP Device − PCB Layers

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 NCP4894

BILL OF MATERIAL
PCB Manufacturer
Item Part Description Ref Footprint Manufacturer Reference

1 NCP4894 Audio Amplifier − − ON Semiconductor NCP4894

2 SMD Resistor 100 kW R3 0603 Vishay−Draloric CRCW0603 Series
3 SMD Resistor 20 kW R1, R2 0603 Vishay−Draloric CRCW0603 Series
R4, R5

4 Ceramic Capacitor 1.0 mF 6.3 V X5R C1, C2 0603 Murata GRM188 Series
C3, C4

5 Jumper Header Vertical Mount, 2*1, 100 mils J4, J5 − − −

6 Jumper Connector, 400 mils J10 − − −
7 I/O Connector. It can be plugged by J2 − Phoenix Contact MC−1,5/3−G
MC−1,5/3−ST−3,81 (Phoenix Contact Reference)

8 I/O Connector. It can be plugged by BLZ5.08/2 J1, J3 − Weidmüller SL5.08/2/90B

(Weidmüller Reference)

ORDERING INFORMATION
Device Marking Package Shipping†
NCP4894FCT1 MAI 9−Pin Flip−Chip 3000 / Tape & Reel
NCP4894FCT1G MAI 9−Pin Flip−Chip 3000 / Tape & Reel
(Pb−Free)

NCP4894DMR2 MAK Micro−10 4000 / Tape & Reel

NCP4894DMR2G MAK Micro−10 4000 / Tape & Reel
(Pb−Free)

NCP4894MNR2 4894 DFN10 3000 / Tape & Reel

NCP4894MNR2G 4894 DFN10 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NOTE: This product is offered with either autectic (SnPb−tin/lead) or lead−free solder bumps (G suffix) depending on the PCB assembly
process. The NCP4894FCT1G, NCP4894DMR2G, NCP4894MNR2G version requires a lead−free solder paste and should not be
used with a SnPb solder paste.

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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

DFN10, 3x3, 0.5P

CASE 485C
ISSUE F
SCALE 2:1 DATE 16 DEC 2021

GENERIC
MARKING DIAGRAM*

XXXXX
XXXXX
ALYWG
G
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
*This information is generic. Please refer to
Y = Year
device data sheet for actual part marking.
W = Work Week Pb−Free indicator, “G” or microdot “G”, may
G = Pb−Free Package or may not be present. Some products may
(Note: Microdot may be in either location) not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON03161D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: DFN10, 3X3 MM, 0.5 MM PITCH PAGE 1 OF 1

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

9 PIN FLIP−CHIP 1.45x1.45x0.596

CASE 499AL
ISSUE A
DATE 21 JUN 2022

GENERIC
MARKING DIAGRAM*
A3
A1
AYWW
XXXX

C1

XXXX = Specific Device Code

A = Assembly Location
Y = Year
WW = Work Week
G or G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON19548D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: 9 PIN FLIP−CHIP 1.45x1.45x0.596 PAGE 1 OF 1

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

Micro10
CASE 846B−03
ISSUE D
DATE 07 DEC 2004
SCALE 2:1

−A− NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
K −B− MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
PIN 1 ID D 8 PL INTERLEAD FLASH OR PROTRUSION
G SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
0.08 (0.003) M T B S A S 5. 846B−01 OBSOLETE. NEW STANDARD
846B−02

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
0.038 (0.0015) C A 2.90 3.10 0.114 0.122
−T− SEATING L B 2.90 3.10 0.114 0.122
PLANE H J C 0.95 1.10 0.037 0.043
D 0.20 0.30 0.008 0.012
G 0.50 BSC 0.020 BSC
H 0.05 0.15 0.002 0.006
SOLDERING FOOTPRINT J 0.10 0.21 0.004 0.008
K 4.75 5.05 0.187 0.199
L 0.40 0.70 0.016 0.028
1.04 0.32
10X 10X
0.041 0.0126 GENERIC
MARKING DIAGRAM*

xxxx
AYW
3.20 4.24 5.28
0.126 0.167 0.208

xxxx = Device Code

A = Assembly Location
Y = Year
W = Work Week
G = Pb−Free Package
0.50
8X
0.0196
SCALE 8:1 ǒinches
mm Ǔ
*This information is generic. Please refer to
device data sheet for actual part marking.
Micro10 Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON03799D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: Micro10 PAGE 1 OF 1

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2000 www.onsemi.com

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