Scribd
Upload
12 views

Week 12 A

Uploaded by

Gqgqg
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
12 views

Week 12 A

Uploaded by

Gqgqg
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 19

Lecture 20

Power Optimization (Part 1)

Xuan ‘Silvia’ Zhang


Washington University in St. Louis

http://classes.engineering.wustl.edu/ese461/
Power Dissipation

• Dynamic power consumption


– switching current
• Static power consumption
– short-circuit current
– leakage current

Pavg = Pdyn + Pshort + Plkg + Pstatic


2
Dynamic Power

• Switching current
– energy dissipated in half a cycle

1/( 2 f ) VDD
⎛ dV ⎞ 1 2
∫ CV ⎜ ⎟dt = ∫ CVdV = CVDD
0 ⎝ dt ⎠ 0
2

– dynamic power expression


– α is the average number of rising transitions in one
cycle

2
Pdyn = αC V out DD f

3
Static Power

• Short-circuit currents
– β is the gain factor of s MOSFET
– Vth is the threshold voltage
– τ is the rise/fall time

β
Pshort = α (VDD − 2Vth )3 fτ
12

4
Static Power

• Leakage currents

Plkg = ( I diode + I subthresho ld ) ⋅VDD


• Other static power
– current flow from VDD to GND during idle time
– historically, NMOS circuits has high static power
– CMOS static power should be 0
– might result from bus conflict where multiple drivers
attempt to drive a signal to different logic values

5
Low Power Design Methodologies

• Adapt process technology


– reduce capacitance
– Cfo is the input capacitance of fan-out gates
– Cw is the wire capacitance
– Cp is the parasitic capacitance

Cout = C fo + Cw + C p
– reduce leakage current
– reduce supply voltage

CoutVDD CoutVDD
Td = =
I ⎛W ⎞
η ⎜ ⎟(VDD − Vth )2
⎝L⎠

6
Low Power Design Methodologies

• Reduce switch activity


– minimize glitches

– nodes logically deeper more prone to signal glitches

7
Low Power Design Methodologies

• Reduce switch activity


– minimize glitches
– minimize number of operations
– example: vector quantization (VQ) algorithm
– Xi are the elements of the input vector
– Cij are the elements of the codebook vector

8
Low Power Design Methodologies

• Reduce switch activity


– minimize glitches
– minimize number of operations
– low power bus

• Examples
– one-hot coding
– gray coding
– bus-inversion coding

9
Minimize Data Transition on Bus

10
Bus Coding

11
Bus Invert Coding

12
Low Power Design Methodologies

• Reduce switch activity


– minimize glitches
– minimize number of operations
– low power bus (state machine encoding)
– scheduling and binding optimization

control-data-flow graph (CDFG)

13
Low Power Design Methodologies

• Power down modes


– clock gating

– enabled flip-flops
– memory partitioning
– power gating

14
How Effective is Clock-Gating?

• 90% FF clock-gated
• 70% power reduction

15
Low Power Design Methodologies

• Voltage optimization and scaling


– multi-Vth optimization

16
Low Power Design Methodologies

• Voltage optimization and scaling


– multi-voltage domain
– dynamic voltage frequency scaling

17
Resource Sharing

• Save area and power

18
Questions?

Comments?

Discussion?

19

You might also like