Department of Electronics and Communication Engineering

Laboratory Manual

Subject: Linear Integrated Circuits

Subject Code: 20EC410L

Lab location: AB201

Prepared by:

Dr. U B Mahadevaswamy Prof. Supreetha M

Professor Assistant Professor
Dept. of ECE Dept. of ECE

2021-2022
Vision statement of the JSS Science and Technology University

 Advancing JSS S&T University as a leader in education, research and technology on the
International arena.
 To provide the students a universal platform to launch their careers, vesting the industry and research
community with skilled and professional workforce.
 Accomplishing JSS S&T University as an epicenter for innovation, centre of excellence for research
with state of the art lab facilities.
 Fostering an erudite, professional forum for researchers and industrialist to coexist and to work
cohesively for the growth and development of science and technology for betterment of society.

Mission statement of the JSS Science and Technology University

1. Education, research and social outreach are the core doctrines of JSS S&T University that are
responsible for accomplishment of in-depth knowledge base, professional skill and innovative
technologies required to improve the socio economic conditions of the country.
2. Our mission is to develop JSS S&T University as a global destination for cohesive learning
of engineering, science and management which are strongly supported with
interdisciplinary research and academia.
3. JSS S&T University is committed to provide world class amenities, infrastructural and
technical support to the students, staff, researchers and industrial partners to promote and
protect innovations and technologies through patents and to enrich entrepreneurial endeavors.
4. JSS S&T University core mission is to create knowledge led economy through appropriate
technologies, and to resolve societal problems by educational empowerment and ethics for
better living.
JSS MAHAVIDYAPEETHA
JSS SCIENCE AND TECHNOLOGY UNIVERSITY

SRI JAYACHAMARAJENDRA COLLEGE OF ENGINEERING

 Constituent College of JSS Science and Technology University
 Approved by A.I.C.T.E
 Governed by the Grant-in-Aid Rules of Government of Karnataka
 Identified as lead institution for World Bank Assistance under TEQIP Scheme

Vision statement of the department of E&CE

Be a leader in providing globally acceptable education in electronics and communication engineering with

emphasis on fundamentals-to-applications, creative-thinking, research and career- building.

Mission statement of the department of E&CE

1. To provide best infrastructure and up-to-date curriculum with a conducive learning

environment.

2. To enable students to keep pace with emerging trends in Electronics and Communication

Engineering.

3. To establish strong industry participation and encourage student entrepreneurship.

4. To promote socially relevant eco-friendly technologies and inculcate inclusive innovation

activities.
Program Outcomes (POs)

1. Engineering Knowledge: Apply knowledge of mathematics, science, engineering fundamentals

and an engineering specialization to the solution of complex engineering problems.

2. Problem Analysis: Identify, formulate, research literature and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences
and engineering sciences

3. Design/ Development of Solutions: Design solutions for complex engineering problems and design
system components or processes that meet specified needs with appropriate consideration for public
health and safety, cultural, societal and environmental considerations.

4. Conduct investigations of complex problems: Using research based knowledge and research
methods including design of experiments, analysis and interpretation of data and synthesis of
information to provide valid conclusions.

5. Modern Tool Usage: Create, select and apply appropriate techniques, resources and modern
engineering and IT tools including prediction and modeling to complex engineering activities with
an understanding of the limitations

6. The Engineer and Society: Apply reasoning informed by contextual knowledge to assess societal,
health, safety, legal and cultural issues and the consequent responsibilities relevant to professional
engineering practice.

7. Environment and Sustainability: Understand the impact of professional engineering solutions in

societal and environmental contexts and demonstrate knowledge of and need for sustainable
development.

8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of engineering practice.

9. Individual and Team Work: Function effectively as an individual, and as a member or leader in
diverse teams and in multidisciplinary settings.
 10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as being able to comprehend and
write effective reports and design documentation, make effective presentations and give
and receive clear instructions.

11. Lifelong Learning: Recognize the need for and have the preparation and ability to engage
in independent and lifelong learning in the broadest context of technological change.

12. Project Management and Finance: Demonstrate knowledge and understanding of

engineering and management principles and apply these to one’s own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.

Program Specific Outcomes (PSOs)

1. Analyze, design and provide engineering solutions in the areas of electronic circuits and
systems.

2. Demonstrate the mathematical modeling techniques, nurture analytical and computational

skills to provide engineering solutions in the areas of electronics and communication.

3. Ability to address multidisciplinary research challenges and nurture entrepreneurship

Program Educational Objectives (PEOs)

1. To enable the graduates to have strong Engineering fundamentals in Electronics &

Communication, with adequate orientation to mathematics and basic sciences.

2. To empower graduates to formulate, analyze, design and provide innovative solutions in

Electronics & Communication, for real life problems.

3. To ensure that graduates have adequate exposure to research and emerging technologies
through industry interaction and to inculcate professional and ethical values.

4. To nurture required skill sets to enable graduates to pursue successful professional career
in industry, higher education, competitive exams and entrepreneurship.
 JSS MAHAVIDYAPEETHA: JSS SCIENCE AND TECHNOLOGY UNIVERSITY
RECORD OF CIE FOR PERFORMANCE IN THE LAB CLASSES
Section Batch Group Number
Staff in Charge Day Timings

Sl.
USN Name of The Student AC1: Preparedness (8M) SUBJECT:
No.
AC2: Conduction (8M) Linear
1.
AC3: Viva (8M) Integrated
AC4: Report Writing (8M) Circuits Lab
2.
AC5: Result Interpretation (8M) (20EC410L)
3. T: Total (40M)

Sl. Date Experiment Student-1 Student-2 Student-3 Remarks

No. AC AC AC AC AC T AC AC AC AC AC T AC AC AC AC AC T
1 2 3 4 5 1 2 3 4 5 1 2 3 4 5

1. AC and DC Amplifiers
2. Op-Amp DC Applications
3. Op-amp Integrator and
Differentiator
4. Butterworth low pass and high
pass Filters
5. Band pass and Band reject
filters
6. *SLE component

Event –II
CIE from experiments 1 to 6(20 Marks)
 Sl. Date Experiment Student-1 Student-2 Student-3 Remarks
No. AC AC AC AC AC T AC AC AC AC AC T AC AC AC AC AC T
1 2 3 4 5 1 2 3 4 5 1 2 3 4 5

7. Schmitt Trigger
8. Square wave & Triangular
wave generator
9. Astable Multivibrator using
555 timer
10. Voltage Regulator using
IC723
11. Simulation experiments
12. *SLE component
(Lab Test)
Event –IV
CIE from experiments 7 to 12
(20 Marks)

Student-1 Student-2 Student-3

Attendance (percentage)
Event II
Event IV

Signature of the Staff in Charge: Signature of the Lab in Charge:

1.

2.
 CONTENTS
Sl.
Date Name of the Experiment
No.
1. AC and DC Amplifiers

2. Op-Amp DC Applications

3. Op-amp Integrator and Differentiator

4. Butterworth low pass and high pass Filters

5. Band pass and Band reject filters

6. Schmitt Triggers

7. Square wave & Triangular wave generator

8. Astable Multivibrator using 555 timer

9. Voltage Regulator using IC723

Simulation experiments:
i. State variable and switched capacitor filter
ii. Switching voltage regulator
iii. Precision rectifiers
10.
iv. Instrumentation amplifiers
v. Amplitude modulation using analog multiplier
Note: Design and simulate the opamp applications using
appropriate tools.
 CONTENTS

Sl.
Date Name of the Experiment
No.
1. AC and DC Amplifiers

2. Op-Amp DC Applications

3. Op-amp Integrator and Differentiator

4. Butterworth low pass and high pass Filters

5. Band pass and Band reject filters

6. Schmitt Triggers

7. Square wave & Triangular wave generator

8. Astable Multivibrator using 555 timer

9. Voltage Regulator using IC723

Simulation experiments:
i. State variable and switched capacitor filter
ii. Switching voltage regulator
iii. Precision rectifiers
10.
iv. Instrumentation amplifiers
v. Amplitude modulation using analog multiplier
Note: Design and simulate the opamp applications using
appropriate tools.
 Experiment – I

Design and testing of Op-amp AC and DC amplifiers

Aim: To design and test the following Op-Amp AC and DC amplifiers:

1. Inverting amplifier
2. Non-inverting amplifier
3. Voltage Follower
Components required:
Components/Equipment’s
Sl.No Specifications Quantity
Required
1. Op-amp µA741 1
2. Resistors As per the design As required
3. Capacitors As per the design As required
4. DC regulated power supply 0-15V 1
5. CRO - 1
6. Signal generator - 1
7. Breadboard - 1
8. Connecting wires - As required

Pre-requisites:
1. Op-amp basics.
2. Op-amp AC and DC amplifiers.
3. Pin details and power supply connection for µA741.
4. Working of Op-amp as Zero Crossing Detector (ZCD).
5. Frequency response.
6. Mathematical relations for gain, input impedance and bandwidth.

2
Zero Crossing Detector(ZCD) circuit diagram:

Figure 1.1(a) Pin diagram (b) Circuit for testing Op-amp as ZCD.

Procedure:
1. The circuit is set-up as shown in figure1.1. The supply voltage ±VCC is set at ±14V.
2. Apply the sinusoidal input signal with 100mV(p-p) amplitude with 1kHz frequency to the inverting
input terminal.
3. Observe the output at pin 6 of the µA741 opamp. We observe the square wave which has the
amplitude equal to ±Vsat.
4. Theoretical ±Vsat has to be calculated using ±Vsat = 90% of VCC.
5. The Op-amp circuit in figure 1.1 can be tested as non-inverting ZCD by interchanging the
connections at the terminals pin 2 & 3.

Observations & Calculations:

3
1. Inverting Amplifiers

1.1 DC Amplifier

Circuit Design:

Fig 1.2: Inverting DC amplifier

Design Specifications:
AF = -5
−𝑅𝑓
Let AF = = -5
𝑅
−𝑅𝑓
-5 = 𝑅

Choose R1 and calculate RF

RF =
R1 =

Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is set-up as shown in figure 1.2. The supply voltage ±VCC is set at ±14V.
3. For different value of DC regulated power supply voltage Vin, note down the corresponding
output voltage.
4. Tabulated the readings and then compare with the calculated theoretical values.

4
Tabular Column:
Table 1.1: Op-amp as Inverting DC amplifier

Vin in volts Vo(th) in volts Vo(practical) in volts

Observations & Calculations:

2. Non-Inverting Amplifier

Circuit Design:

Fig 1.3: Op-amp as non-inverting DC amplifier

Design Specifications:

AF = 20

5
Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is set-up as shown in figure 1.3. The supply voltage ±VCC is set at ±14V.
3. For different value of DC regulated power supply voltage Vin, note down the corresponding output
voltage.
4. Tabulate the readings, then compare with the calculated theoretical values.

Tabular Column:

Table 1.2: Op-amp as Non-Inverting DC amplifier

Vin in volts Vo(th) in volts Vo(practical) in volts

Observations & Calculations:

6
 Voltage Follower

Circuit Design:

Fig 1.4: Op-amp Voltage follower

Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is set-up as shown in figure 1.4. The supply voltage ±VCC is set at ±14V.
3. For different value of DC regulated power supply voltage Vin, note down the corresponding output
voltage.
4. Tabulated the readings, then compare with the calculated theoretical values.

Observations & Calculations:

Table 1.3: Op-amp as Voltage follower

Vin in volts Vo(th) in volts Vo(practical) in volts

7
Observations & Calculations:

1.2 AC Amplifier
Inverting AC amplifier

Circuit Design:

Fig 1.5: Op-amp Inverting AC amplifier

8
Design Specifications:

a) Without CF:
b) With CF:
Let |AVf|(mid) = -10
To fix FH = _____
Zif = _____
1
FH = 2𝜋𝑅
FL = _____ 𝐹 𝐶𝐹

CF = _____

Zif = R = _____
−𝑅𝑓
|AVf|(mid) = -10 = 𝑅

Rf = _____
1
FL = 2𝜋𝑅𝐶, C = ______
106
FH = |Avf|(mid) = ______

Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is setup as shown in figure 1.5. The supply voltage (±VCC) is set at ±15V. The input to
the circuit is 1V(p-p) AC supply.
3. Vary the frequency of the input ac voltage source and note down the corresponding output voltage
reading (VO(P-P)).
4. Tabulate the readings from the results obtained, plot the frequency response of the circuit.
5. After tabulation, measure the values of mid-band gain, input and output impedances and bandwidth.
Then, compare the results with the corresponding theoretical values calculated.

9
Tabular Column:

Table 1.4: Frequency response of Op-Amp inverting AC amplifier without CF

Vi = ____
𝑉𝑜 𝑉𝑜
Frequency (Hz) V0 (p-p) (V) Gain ( 𝑉𝑖 ) |AV| = 20log 𝑉𝑖 in dB

Table 1.5: Comparison of parameters: Inverting AC amplifier without CF

SL.NO Parameter Theoretical values Practical Values

1. |AVf|(mid)
2. Zif
3. FL
4. FH

10
Table 1.6: Frequency response of Op-Amp inverting AC amplifier
Vi = 1V(p-p)
𝑉𝑜 𝑉𝑜
Frequency (Hz) V0 (p-p) (V) Gain ( 𝑉𝑖 ) |AV| = 20log 𝑉𝑖 in dB

Table 1.7: Comparison of parameters: Inverting AC amplifier with CF

SL.NO Parameter Theoretical values Practical Values

1. |AVf|(mid)
2. Zif
3. FL
4. FH

Observations and calculations:

11
 Non-Inverting AC Amplifier
Circuit Diagram:

Fig 1.6: Op-Amp as Non-Inverting AC amplifier

Design:
a) Without CF: b) With CF:
Let |AVf|(mid) = _____
To fix FH =
Zif = _____ 1
FH = 2𝜋𝑅
FL = _____ 𝐹 𝐶𝐹

Zif = Rcomp = _____ CF = _____

Rcomp = Rf||R
𝑅𝑓
|AVf|(mid) = _____ = 1 + 𝑅

Rf = ______
R = ______
1
FL = 2𝜋𝑅𝐶, C = ______
106
FH = |Avf|(mid) = ______

Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is setup as shown in figure 1.6. The supply voltage (±VCC) is set at ±15V. The input to the
circuit is 1V(p-p) AC supply.
3. Vary the frequency of the input ac voltage source and note down the corresponding output voltage
reading (VO(P-P)).
4. Tabulate the readings from the results obtained, plot the frequency response of the circuit.

12
5. After tabulation, measure the values of mid-band gain, input and output impedances and bandwidth.
Then, compare the results with the corresponding theoretical values calculated.

Tabular Column:

Table 1.8: Frequency response of Op-Amp Non-inverting AC amplifier without CF

Vi = ______
𝑉𝑜 𝑉𝑜
Frequency (Hz) V0 (p-p) (V) Gain ( 𝑉𝑖 ) |AV| = 20log 𝑉𝑖 in dB

Table 1.9: Comparison of parameters: Non-Inverting AC amplifier without CF

SL.NO Parameter Theoretical values Practical Values
1. |AVf|(mid)
2. Zif
3. FL
4. FH

13
Table 1.10: Frequency response of Op-Amp Non-inverting AC amplifier with CF
Vi = 1V(p-p)
𝑉𝑜 𝑉𝑜
Frequency (Hz) V0 (p-p) (V) Gain ( 𝑉𝑖 ) |AV| = 20log 𝑉𝑖 in dB

Table 1.11: Comparison of parameters: Non-Inverting AC amplifier with CF

SL.NO Parameter Theoretical values Practical Values
1. |AVf|(mid)
2. Zif
3. FL
4. FH

Observations & Calculations:

14
 AC Voltage follower

Circuit Diagram:

Fig 1.7: Op-Amp as AC voltage follower

Design:
1
Set FL = ______ = 2𝜋𝑅𝐶

Let C = ______
R = ______
106
FH = |Avf|(mid) = ______ ( as |Avf| = 1)

Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is setup as shown in figure 1.7. The supply voltage (±VCC) is set at ±15V. The input to
the circuit is 1V(p-p) AC supply.
3. Vary the frequency of the input ac voltage source and note down the corresponding output voltage
reading (VO(P-P)).
4. Tabulate the readings from the results obtained, plot the frequency response of the circuit.
5. After tabulation, measure the values of mid-band gain, input and output impedances and bandwidth.
Then, compare the results with the corresponding theoretical values calculated.

15
Tabular Column:

Table 1.12: Frequency response of Op-Amp AC voltage follower

Vi = ______
𝑉𝑜 𝑉𝑜
Frequency (Hz) V0 (p-p) (V) Gain ( 𝑉𝑖 ) |AV| = 20log 𝑉𝑖 in dB

Table 1.13: Comparison of parameters: AC Voltage follower

SL.NO Parameter Theoretical values Practical Values
1. |AVf|(mid)
2. Zif
3. FL
4. FH

Observations & Calculations:

16
Inference:

Advantages:

Applications:

17
 Experiment – II

Design and testing of Op-amp DC Circuits

Aim:

To design and test the following Op-Amp DC circuits:

1. Inverting Adder circuit.
2. Inverting Averager
3. Inverting addition with scaling circuit
4. Non-inverting summer circuit
5. Non-inverting averager
6. Difference amplifier
7. Subtractor circuit

Components required:
Components/Equipment’s
SL.NO Specifications Quantity
Required
1. Op-amp µA741 1
2. Resistors As per the design As required
3. DC regulated power supply 0-15V 1
4. CRO - 1
5. Signal generator - 1
6. Breadboard - 1
7. Connecting wires - As required

Pre-requisites:
1. Op-amp basics.
2. Op-amp DC circuits.
3. Pin details and power supply connection for µA741.
4. Working of Op-amp as ZCD.

18
 Inverting Adder Circuit
Circuit Diagram:

Fig 2.1: Op-amp as inverting Adder

Design:
We have V0 = -[av1 + bV2]
𝑅 𝑅
Where a = 𝑅𝑓 , b = 𝑅𝑓
1 2

If we take a = b =1
V0 = -[V1 + V2]
Select R1, R2 and RF suitably.
R1 = ____
R2 = ____
RF = ____

Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is set-up as shown in figure 2.1. The supply voltage ±VCC is set at ±12V.
3. For different value of DC regulated power supply voltage Vin, note down the corresponding output
voltage.
4. Tabulate the readings, then compare with the calculated theoretical values calculated using the
formula V0 = -[V1 + V2].

19
Tabular Column:
Table 2.1: Op-amp as Inverting DC amplifier

V1 in volts V2 in volts Vo(th) in volts Vo(practical) in volts

Observations & Calculations:

Inverting DC Averager
Circuit Diagram:

Fig 2.2: Op-amp as Inverting DC averager

20
Design:
We have V0 = -[av1 + bV2]
𝑅 𝑅
Where a = 𝑅𝑓 , b = 𝑅𝑓
1 2

1
If we take a = b = 2
1
V0 = -2 [V1 + V2]

Select R1, R2 and RF suitably.

R1 = _____
R2 = _____
RF = _____

Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is set-up as shown in figure 2.2. The supply voltage ±VCC is set at ±12V.
3. For different value of DC regulated power supply voltage Vin, note down the corresponding output
voltage.
4. Tabulate the readings, then compare with the calculated theoretical values calculated using the
1
formula V0 = -2 [V1 + V2].

Tabular Column:
Table 2.2: Op-amp as Inverting DC averager

V1 in volts V2 in volts Vo(th) in volts Vo(practical) in volts

Observations & Calculations:

21
 Inverting DC adder with scaling

Circuit Diagram:

Fig 2.3: Op-amp as Inverting DC adder with scaling

Design:
We have V0 = -[av1 + bV2]
𝑅 𝑅
Where a = 𝑅𝑓 , b = 𝑅𝑓
1 2

If we take a = b =
V0 = -2 [V1 + V2]
Select R1, R2 and RF suitably.
R1 = _____
R2 = _____
RF = _____

Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is set-up as shown in figure 2.3. The supply voltage ±VCC is set at ±12V.
3. For different value of DC regulated power supply voltage Vin, note down the corresponding output
voltage.
4. Tabulate the readings, then compare with the calculated theoretical values calculated using the
formula V0 = -2[V1 + V2].

22
Tabular Coulmn:
Table 2.3: Op-amp as Inverting DC adder with scaling

V1 in volts V2 in volts Vo(th) in volts Vo(practical) in volts

Observations & Calculations:

Non-Inverting DC adder circuit

Circuit Diagram:

Fig 2.4: Non-inverting DC adder circuit

23
Design:
1 𝑅
We have V0 = 2 [V1 + V2](1+𝑅𝑓 )
1

𝑅
Where (1+𝑅𝑓 ) = 2
1

V0 = [V1 + V2]
Select R1, R2 and RF suitably.
R = _____
R1 = _____
RF = _____

Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is set-up as shown in figure 2.4. The supply voltage ±VCC is set at ±12V.
3. For different value of DC regulated power supply voltage Vin, note down the corresponding output
voltage.
4. Tabulate the readings, then compare with the calculated theoretical values calculated using the
formula V0 = [V1 + V2].

Tabular Column:
Table 2.4: Op-amp as Non-Inverting DC adder

V1 in volts V2 in volts Vo(th) in volts Vo(practical) in volts

Observations & Calculations:

24
 Non-Inverting DC average

Circuit Diagram:

Fig 2.5: Op-amp as Non-inverting DC Averager

Design:
1 𝑅
We have V0 = 2 [V1 + V2](1+𝑅𝑓 )
1

𝑅
Where (1+𝑅𝑓 ) = 1
1

1
V0 = 2 [V1 + V2]

Select R, short Pin 2&6.

R = _____

Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is set-up as shown in figure 2.5. The supply voltage ±VCC is set at ±12V.
3. For different value of DC regulated power supply voltage Vin, note down the corresponding output
voltage.
4. Tabulate the readings, then compare with the calculated theoretical values calculated using the
1
formula V0 = 2 [V1 + V2].

25
Tabular Column:
Table 2.5: Op-amp as Non-Inverting DC averager
V1 in volts V2 in volts Vo(th) in volts Vo(practical) in volts

Observations & Calculations:

Difference Amplifier
Circuit Diagram:

Fig 2.6: Op-amp as Difference amplifier

26
Design:
𝑅 𝑅
We have, VO = - 𝑅𝑓 V1 + 𝑅3V2
1 2

𝑅 𝑅
If 𝑅𝑓 = 𝑅3
1 2

𝑅
Then VO = 𝑅𝑓 [V2 – V1] = Ad
1

Choose RF and R1 for Ad =

RF = _____
R1 = _____
R2 = _____
R3 = _____
Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is set-up as shown in figure 2.6. The supply voltage ±VCC is set at ±12V.
3. For different value of DC regulated power supply voltage Vin, note down the corresponding output
voltage.
4. Tabulate the readings, then compare with the calculated theoretical values calculated using the
𝑅
formula V0 = 𝑅𝑓 [V2 – V1].
1

Tabular Column:
Table 2.6: Op-amp as Difference Amplifier
V1 in volts V2 in volts Vo(th) in volts Vo(practical) in volts

Observations & Calculations:

27
 Subtractor circuit
Circuit Diagram:

Fig 2.7: Subtractor circuit

Design:
𝑅 𝑅
We have, VO = - 𝑅𝑓 V1 + 𝑅3V2
1 2

𝑅 𝑅
If 𝑅𝑓 = 𝑅3
1 2

Then VO = [V2 – V1] = Ad

Choose RF and R1 for Ad =
RF = ____
R1 = ____
R2 = ____
R3 = ____

Procedure:
1. The Op-amp is tested for ZCD.
2. The circuit is set-up as shown in figure 2.7. The supply voltage ±VCC is set at ±12V.
3. For different value of DC regulated power supply voltage Vin, note down the corresponding output
voltage.
4. Tabulate the readings, then compare with the calculated theoretical values calculated using the
formula V0 = [V2 – V1].

28
Tabular Column:
Table 2.7: Op-amp as Difference Amplifier

V1 in volts V2 in volts Vo(th) in volts Vo(practical) in volts

Observations & Calculations:

Inference:

Advantages:

Applications:

29
 Experiment – III

Design and testing of Op-amp Integrator & Differentiator

Aim:
To design and test Op-amp Integrator & Differentiator
1. Obtain its frequency response.
2. Find salient frequencies f1 & f2.
3. Find | AF(𝜔)| and 𝜃(𝜔) at the frequencies f < f1, f = f1, f > f1.

Components Required:

Components/Equipment’s
SL.NO Specifications Quantity
Required
1. Op-amp µA741 1
2. Resistors As per the design As required
3. Capacitors As per the design As required
DC regulated power
4. 0-15V 1
supply
5. CRO - 1
6. Signal generator - 1
7. Breadboard - 1
8. Connecting wires - As required

Pre-requisites:
1. Operation of basic Op-amp Integrator, Differentiator and its drawbacks.
2. Operation of practical Integrator & Differentiator
3. Response of Integrator and Differentiator for square wave input.
4. Concept of poles and zeros.

30
Circuit Diagram:

Fig 3.1: Op-amp Integrator

Design Specifications:
|Af| = ____ = DC gain Choose, Cf = _____,
To integrate all frequencies ≥ 1kHz Rf = ________.

Design Procedure: 𝑅𝑓
|Af| = =
𝑅
Lowest frequency to be integrated, fmin = ______
For proper integration, f1 < fmin
R = _________
RCOMP = R1||Rf
f
Let f1 = min = _____
10 RCOMP = _______

1 1
f1 = f2 = = _____
2𝜋𝑅𝐹 𝐶𝐹
2𝜋𝑅𝐶𝐹
Procedure:
1. Test the Op-Amp as ZCD.
2. Setup the circuit as shown in figure 3.1.
3. Obtain frequency and phase responses.
4. Compute and compare the magnitude and phase values with the corresponding theoretical values
for at least five frequencies.

31
5. The output with square wave input is observed, compare the theoretical and practical voltage for at
least five frequencies.

Table 3.1: Frequency of Op-amp Integrator Vi = ______

𝑉𝑜
Frequency (Hz) VO(P-P) (V) Gain (VO/Vi) |AV| = 20log 𝑉𝑖 in dB

Table 3.2: Phase response Vi = _____

𝑌
Frequency (Hz) Y-Intercept H-Intercept 𝜃(practical) = 180º - sin-1(𝐻)

32
Table 3.3: Comparison of Practical and theoretical values of |AV| and 𝜃.

𝑹𝒇/𝑹𝟏 𝒇
|AV| = 𝜽(th) = 180º - tan-1(𝒇𝟏)
𝟐
√𝟏+( 𝒇 )
𝒇𝟏

Frequency 𝜃(practical) 𝜃(theoretical) |AV|(practical) |AV|(theoretical)

Table 3.4: Response for Square wave input [ f<f1, f=f1, f>f1 ]
𝑉
Vi = _______ VO (P-P) (theoretical) =
4𝑓𝑅𝐶𝐹

Frequency Vo (p-p) (practical) Vo (p-p) (theoretical)

Table 3.5: Comparison of practical and theoretical values of f1 & f2.

SL.NO Parameter Theoretical values Practical values

1. |Af|(DC)

2. f1

3. f2

33
Lissajious patter for six different frequencies [ f<f1, f=f1, f>f1 ]
1. f = 2. f =

3. f = 4. f =

5. f= 6. f =

34
Square wave response for six different frequencies [Plot output waveforms super imposed on the
input waveforms]

1. f = 2. f =

3. f = 4. f =

5. f= 6. f =

35
Observations & calculations:

36
3.2: Differentiator
Circuit Diagram:

Fig 3.1: Op-amp as a Differentiator

Design Specifications:

To differentiate all frequencies ≤ 1kHz 1

f1 = ,
2𝜋𝑅𝐹 𝐶1
Let us keep f1 < fmax, Take f1 =
fmax
,
Design Procedure: 5
Highest frequency to be differentiated, fmax = _____ f1 = ______

C1 = _____
For proper differentiation, fmax < f2
Let f2 = 5*fmsx, f2 = ______
1 1 W.k.t RfCf = R1C1, R1 = ________
f2 = 2𝜋𝑅 = 2𝜋𝑅
𝐹 𝐶𝐹 1 𝐶1
RCOMP = R1||Rf

Choose, Cf = _____, RCOMP = ______

Rf = ______.

37
Procedure:
1. The Op-amp is tested as ZCD.
2. Setup the circuit as shown in figure 3.1.
3. Obtain frequency and phase responses.
4. Compute and compare the magnitude and phase values with the corresponding theoretical values
for at least five frequencies.
5. The output with square wave input is observed, compare the theoretical and practical voltage for at
least five frequencies.

Observations & calculations:

Table 3.6: Frequency of Op-amp Differentiator Vi = 1V(p-p)

𝑉𝑜
Frequency (Hz) VO(P-P) (V) Gain (VO/Vi) |AV| = 20log 𝑉𝑖 in dB

38
Table 3.7: Phase response Vi = ______
𝑌
Frequency (Hz) Y-Intercept H-Intercept 𝜃(practical) = 180º - sin-1(𝐻)

Table 3.8: Comparison of Practical and theoretical values of |AV| and 𝜃.

𝒇
|AV| = 𝝎RFC1 𝜽(th) = -90º - 2tan-1(𝒇𝟐)

Frequency 𝜃(practical) 𝜃(theoretical) |AV|(practical) |AV|(theoretical)

Table 3.9: Response for Square wave input [ f<f1, f=f1, f1<f<f2]

Vi = ________ VO (P-P) (theoretical) = Vsat

Frequency Vo (p-p) (practical) Vo (p-p) (theoretical)

39
Table 3.10: Comparison of practical and theoretical values of f1 & f2.

SL.NO Parameter Theoretical values Practical values

1. f1

2. f2

Lissajious patter for six different frequencies [ f<f1, f=f1, f>f1 ]

1. f = 2. f =

3. f = 4. f =

5. f= 6. f =

40
Square wave response for six different frequencies [Plot output waveforms super imposed on the
input waveform.

1. f = 2. f =

3. f = 4. f =

5. f= 6. f =

41
Inference:

Advantages:

Disadvantages:

Application

42
 Experiment – IV

Design and testing of Butterworth low pass and high pass filters

Aim:
To design and test Butterworth low pass and high pass filters,
1. Obtain their frequency response
2. Find the cut-off frequencies.
3. Find band pass gain.
4. Find the roll-off.

Components required:
Components/Equipment’s
SL.NO Specifications Quantity
Required
1. Op-amp µA741 1
2. Resistors As per the design As required
3. Capacitors As per the design As required
DC regulated power
4. 0-15V 1
supply
5. CRO - 1
6. Signal generator - 1
7. Breadboard - 1
8. Connecting wires - As required

Pre-requisites:
1. Advantages of active filters.
2. Poles of normalised Butterworth low pass and high pass filter.
3. Transfer function of low pass and high pass filters.
4. Relation between order of filter, Roll-off and number of poles.

43
 Second order Butterworth low pass filter

Circuit Diagram:

Fig 4.1: Second order Butterworth low pass filter

Design Specifications:

Cut-off frequency, fc = ______

Design Procedure:

1
Fc = 2𝜋𝑅𝐶

Choose, C = ______,
R = _______

For second order Butterworth filter: Sn2 + 1.414Sn + 1

𝛼 = ______ 𝑅𝑓
A0 = 1 +
𝑅1
𝑅𝑓
𝛼 = 3-A0 = _______
𝑅1
A0 = _______

Rf = _______
R1 = _______
1.586
HLPF(s) = 𝑺𝟐 + 𝟏.𝟒𝟏𝟒𝑺
𝒏 𝒏 +𝟏

44
Observations & Calculations:

Table 4.1: Frequency response of Second order Butterworth low pass filter Vi = _____

𝑉𝑜 𝑉𝑜
Frequency (Hz) V0 (p-p) (V) Gain ( 𝑉𝑖 ) |AV| = 20log 𝑉𝑖 in dB

45
 Fourth order Butterworth low pass filter

Circuit Diagram:

Fig 4.2: Fourth order Butterworth low pass filter

Design Specifications:

Cut-off frequency, fc = 4kHz

Design Procedure:

1
Fc = 2𝜋𝑅𝐶

Choose, C = _______
R = _______

For fourth order Butterworth filter:

(Sn2 + 0.765Sn + 1) (Sn2 + 1.848Sn + 1)
𝛼 1 = ______ 𝛼 2 = ______

𝛼 = 3-A0
𝛼 = 3-A0 A0 = ______
A0 = ________ 𝑅𝑓2
A0 = 1 +
𝑅2

𝑅𝑓2
𝑅𝑓1 = ______
A0 = 1 + 𝑅2
𝑅1
𝑅𝑓1 Rf2 = ______
= ______
𝑅1 R2 = ______

46
Rf1 = _______
R1 = _______

2.235 1.152
HLPF(s) = 𝑺𝟐 + 𝟎.𝟕𝟔𝟓𝑺 x 𝑺𝟐 + 𝟏.𝟖𝟒𝟖𝑺
𝒏 𝒏+𝟏 𝒏 𝒏 +𝟏

Observations & Calculations:

Table 4.2: Frequency response of Fourth order Butterworth low pass filter Vi = ______

𝑉𝑜 𝑉𝑜
Frequency (Hz) V0 (p-p) (V) Gain ( ) |AV| = 20log in dB
𝑉𝑖 𝑉𝑖

47
Comparison of practical and theoretical values of cut-off frequency, pass band gain and roll-off
for low pass filter:

Second order Fourth order

SL.NO Parameter
Theoretical Practical Theoretical Practical
1. Pass band gain
2. Cut-off frequency
3. Roll-off

Second order Butterworth high pass filter

Circuit Diagram:

Fig 5.3: Second order Butterworth high pass filter

Design Specifications:

Cut-off frequency, fc = _____

Design Procedure:

1
Fc = 2𝜋𝑅𝐶

Choose, C = ______,
R = ______

For second order Butterworth filter: Sn2 + 1.414Sn + 1

48
𝛼 = ________
𝛼 = 3-A0
A0 = ________
𝑅𝑓
A0 = 1 + 𝑅1

𝑅𝑓
= _______
𝑅1

Rf = _______
R1 = _______
1.586
HLPF(s) = 𝑺𝟐
𝒏 + 𝟏.𝟒𝟏𝟒𝑺𝒏 + 𝟏

Observations & Calculations:

Table 4.3: Frequency response of Second order Butterworth high pass filter Vi = _____

𝑉𝑜 𝑉𝑜
Frequency (Hz) V0 (p-p) (V) Gain ( 𝑉𝑖 ) |AV| = 20log 𝑉𝑖 in dB

49
 Third order Butterworth high pass filter

Circuit Diagram:

Fig 4.4: Third order Butterworth high pass filter

Design Specifications:

Cut-off frequency, fc = _____

Design Procedure:

1
Fc = 2𝜋𝑅𝐶

Choose, C = ______
R = ______

For fourth order Butterworth filter:

(Sn2 + 1) (Sn2 + Sn + 1)

Total Gain = ____ 𝛼2 = 1

Hence, for first order filter gain is ____ 𝛼 = 3-A0

A0 = __
A0 = ___
𝑅𝑓2
A0 = 1 + 𝑅2
𝑅𝑓1
A0 = 1 + 𝑅𝑓2
𝑅1 = _____
𝑅2
𝑅𝑓1
= ____
𝑅1 Rf2 = _____
R2 = _____

Rf1 = ______
R1 = ______

50
 5 2
HLPF(s) = x
𝑺𝒏 + 𝟏 𝑺𝟐𝒏 + 𝑺𝒏 + 𝟏

Procedure:
1. Test the Op-Amp as ZCD.
2. Set up the circuits as shown in figure 4.1 to 4.4
3. Obtain the frequency response.
4. Compute the cut-off frequency, pass band gain and roll-off for each circuit and compare with the
corresponding theoretical values.

Observations & Calculations:

Table 4.4: Frequency response of Third order Butterworth high pass filter Vi = ______

𝑉𝑜 𝑉𝑜
Frequency (Hz) V0 (p-p) (V) Gain ( 𝑉𝑖 ) |AV| = 20log 𝑉𝑖 in dB

51
Comparison of practical and theoretical values of cut-off frequency, pass band gain and roll-off
for high pass filter:
Second order Third order
SL.NO Parameter
Theoretical Practical Theoretical Practical

1. Pass band gain

2. Cut-off frequency

3. Roll-off

Inference:

Advantages:

Disadvantages:

Applications:

52
 Experiment – V

Design and testing of Narrow Band pass and Band elimination

Aim:
To design and test Narrow band pass and band elimination filters and
1. Obtain their Frequency response.
2. Find the cut-off frequencies and Bandwidth.
3. Find band pass gain.
4. Find the roll-off.

Components required:
Components/Equipment’s
SL.NO Specifications Quantity
Required
1. Op-amp µA741 1
2. Resistors As per the design As required
3. Capacitors As per the design As required
DC regulated power
4. 0-15V 1
supply
5. CRO - 1
6. Signal generator - 1
7. Breadboard - 1
8. Connecting wires - As required

Pre-requisites:
1. Operation of BPF and BEF.
2. Realization of BPF and BEF using LPF and HPF.
3. Difference between Narrow and Wide band pass filter.
4. Applications of BPF and BEF.

53
 Second order Narrow Band pass filter

Circuit Diagram:

Fig 5.1: Second order Narrow band pass filter

Design Specifications:
Center frequency, f0 = ______
Quality Factor, Q0 = _____
Gain at resonance, |A0| = ___

Design Procedure:
𝑄𝑜
R1 = 𝜔𝑜𝐶 |𝐴𝑜| ----- 7.1

Choose, C = _____

2𝑄𝑜
R5 = 𝜔𝑜𝐶 ------- 7.2

R5 = ______

𝑄𝑜
R4 = – 7.3
𝜔𝑜𝐶 [ 2𝑄 −|𝐴
2 |]
0
0

C
C
Pass band gain, A0 = ___
Calculate R4, Make sure that 2Q02 > |A0|
R4 = ______

54
Observations & Calculations:
Table 5.1: Frequency Response of the Narrow Band pass filter
Vi = ______
𝑉𝑜
Frequency (Hz) VO(P-P) (V) Gain (VO/Vi) |AV| = 20log 𝑉𝑖 in dB

Table 5.2: Comparison of practical and theoretical values for Narrow band pass filter

SL.NO Parameter Theoretical Practical

1. Gain at Resonance, |A0|

2. Center frequency, f0

3. Bandwidth, BW

4. Quality Factor, Q0

5. Lower cut-off frequency, fL

6. Upper cut-off frequency, fH

7. Roll-off

55
Theoretical Equations in terms of circuit components:

𝜔0 𝐶
Q0 = 2 𝐺5

1
BW = 𝜋 𝐶 𝑅
5

1
fH = 2𝜋𝐶
1𝑅 1

1
fL = 2𝜋𝐶
2𝑅 2

Narrow Band elimination filter (Notch filter)

Circuit Diagram:

Fig 5.3: Narrow Band elimination filter (Notch filter)

Design Specifications:
Notch frequency, fN = ______
Quality factor, Q0 = ____

56
Design Procedure:

1
fN = 2 𝜋𝑅𝐶

Choose, C = ______
R = ______

1
Q0 = 4(1−𝐾)

𝑅2
K= 𝑅1 + 𝑅2

Calculate R1 and R2
R1 = _____
R2 = _____

Procedure:
1. Test the Op-Amp as ZCD.
2. Setup the circuits as shown in figure 5.1 and 5.3
3. Obtain frequency response
4. Compute the frequencies 𝜔0, 𝜔1, 𝜔2, Bandwidth, Quality factor and gain at resonance for each
circuit and compare with the corresponding theoretical values.

57
Table 5.3: Frequency Response of the Narrow Band reject filter
Vi = 1V (p-p)

𝑉𝑜
Frequency (Hz) VO(P-P) (V) Gain (VO/Vi) |AV| = 20log 𝑉𝑖 in dB

Table 5.4: Comparison of practical and theoretical values for Narrow band reject filter

SL.NO Parameter Theoretical Practical

1. Notch frequency, fN

2. Bandwidth, BW

3. Quality Factor, Q0

4. Lower cut-off frequency, 𝜔L

5. Upper cut-off frequency, 𝜔H

58
Theoretical Equations in terms of circuit components:

1
Q0 = 4(1−𝐾)

BW = 4(1-K)f0

𝜔H = 𝜔0*[ √1 + 4(1 − 𝑘)2 + 2(1-k)]

𝜔L = 𝜔0*[ √1 + 4(1 − 𝑘)2 - 2(1-k)]

Inference:

Advantages:

Applications:

59
 Experiment – VI

Design and testing of Inverting and Non-inverting Schmitt triggers

Aim:
To design and test Op-amp inverter and non-inverter, Schmitt trigger and
i) Calculate the lower and upper trip point voltages.
ii) Observe transfer characteristics and calculate the hysteresis.

Components required:
Components/Equipment’s
SL.NO Specifications Quantity
Required
1. Op-amp µA741 1
2. Resistors As per the design As required
3. Zener Diode 1N4733A 2
DC regulated power
4. 0-15V 1
supply
5. CRO - 1
6. Signal generator - 1
7. Breadboard - 1
8. Connecting wires - As required

Pre-requisites:
1. Op-amp as comparator.
2. Problems with basic comparator.
3. Operation of inverting and non-inverting Schmitt triggers with relevant design equations.
4. Amplitude limiter in Schmitt trigger.
5. Applications of comparator circuit and Schmitt trigger.

60
 Inverting Schmitt trigger

Circuit Diagram:

Fig 6.1: Inverting Schmitt trigger

Design Specifications:
VUTP = _____
VLTP = _____

Design Procedure:
𝑉𝑅 𝑅2 𝑉𝑠𝑎𝑡 𝑅1
VUTP = + ----- 7.1
𝑅1 +𝑅2 𝑅1 +𝑅2

𝑉𝑅 𝑅2 𝑉𝑠𝑎𝑡 𝑅1
VLTP = - ----- 7.2
𝑅1 +𝑅2 𝑅1 +𝑅2

2 𝑉𝑠𝑎𝑡 𝑅1
VH = --------------- 7.3
𝑅1 +𝑅2

Using the given specifications, design the values of VR, R1 and R2.

R1 = ______
R1 = ______
VR = ______

Amplitude limiting circuit:

Design amplitude limiter circuit for V0 = _______

61
Procedure:
1. Test the Op-Amp as ZCD.
2. Setup the circuits as shown in Fig. 6.1 and 6.4.
3. Apply the sinusoidal input of frequency 1KHz and peak value, Vm > max { |VUTP|, |VLTP|}
4. The output waveform on CRO is observed, measure VUTP VLTP and VH.
5. plot the transfer characteristics. Measure VUTP VLTP and VH on transfer characteristics and cross
check.
6. Repeat steps 3-5 with VR = 0.
7. Also observe output waveform and input waveform with transistor.

Comparison of practical and theoretical values (VR ≠ 0)

Inverting Schmitt trigger

SL.NO Quantity
Theoretical Practical
1. VUTP
2. VLTP
3. VH
4. V0
5. V0’

Comparison of practical and theoretical values (VR = 0)

Inverting Schmitt trigger
SL.NO Quantity
Theoretical Practical
1. VUTP
2. VLTP
3. VH
4. V0
5. V0’

62
Observed output waveforms and transfer characteristics for inverting Schmitt trigger (VR ≠ 0)

Observed output waveforms and transfer characteristics for inverting Schmitt trigger (VR = 0)

Observed output waveforms and transfer characteristics for inverting Schmitt trigger with triangular
waveform (VR ≠ 0)

63
Observed output waveforms and transfer characteristics for inverting Schmitt trigger with triangular
waveform (VR = 0)

Non-Inverting Schmitt trigger

Circuit Design:

Fig 6.4: Non-inverting Schmitt trigger

Design Specifications:
VUTP = _______
VLTP = _______

Design Procedure:
𝑉𝑅 𝑅1 +𝑅2 𝑉𝑠𝑎𝑡 𝑅1
VUTP = + ----- 7.4
𝑅2 𝑅2

64
 𝑉𝑅 𝑅1 +𝑅2 𝑉𝑠𝑎𝑡 𝑅1
VLTP = - ----- 7.5
𝑅2 𝑅2

2 𝑉𝑠𝑎𝑡 𝑅1
VH = --------------- 7.6
𝑅2

Using the given specifications, design the values of VR, R1 and R2.

R1 = ______
R2 = ______
VR = ______

Amplitude limiting circuit:

Design amplitude limiter circuit for V0 =

Comparison of practical and theoretical values (VR ≠ 0)

Non-Inverting Schmitt trigger

SL.NO Quantity
Theoretical Practical
1. VUTP
2. VLTP
3. VH
4. V0
5. V0’

Comparison of practical and theoretical values (VR = 0)

Non-Inverting Schmitt trigger
SL.NO Quantity
Theoretical Practical
1. VUTP
2. VLTP
3. VH
4. V0
5. V0’

65
Observed output waveforms and transfer characteristics for Non-inverting Schmitt trigger (VR ≠ 0)

Observed output waveforms and transfer characteristics for Non-inverting Schmitt trigger (VR = 0)

Observed output waveforms and transfer characteristics for Non-inverting Schmitt trigger with
triangular waveform (VR ≠ 0)

66
Observed output waveforms and transfer characteristics for Non-inverting Schmitt trigger with
triangular waveform (VR = 0)

Inference:

Advantages:

Applications:

67
 Experiment – VII

Design and testing of Op-Amp Square wave and Triangular Wave generator

Aim:
To design and test Op-amp square wave and triangular wave generator and
i) Study variable Duty cycle operation at a constant frequency.
ii) Study Variable frequency operation at a duty cycle.

Components Required:
Components/Equipment’s
SL.NO Specifications Quantity
Required
1. Op-amp µA741 1
2. Resistors As per the design As required
3. Capacitors As per the design As required
4. DC regulated power supply 0-15V 1
5. CRO - 1
6. Signal generator - 1
7. Breadboard - 1
8. Connecting wires - As required
9. Diode 1N3909 2

Pre-requisites:
1. Astable and Monostable multivibrators.
2. Operation of square wave generator.
3. Operation of triangular wave generator.
4. Variable duty cycle and variable frequency operation of square wave and triangular wave
generators.

68
Circuit Diagram:

Fig 7.1: Op-Amp Square wave and triangular wave generator

Design Specifications:
Peak-to-peak value of triangular waveform : _____
Frequency Range :200Hz to 2000Hz
Duty Cycle : 20% to 80%
±Vcc : ±12𝑉

Design Procedure:

TON = (R6 + R5a + R3)C ------------ 7.1

TOFF = (R6 + R5b + R3)C ------------ 7.2
T = (2R6 + R5 + 2R3)C ------------- 7.3

𝑇𝑜𝑛 𝑅 +𝑅 +𝑅
D= = 2𝑅6 + 𝑅5𝑎+ 2𝑅3 ------------7.4
𝑇 6 5 3

2𝑉𝑠𝑎𝑡 𝑅1
V0(p-p) = -------------7.5
𝑅2

Using equations (7.1) to (7.5), design the component values for the given specifications.

Let V0(p-p) =______

Vsat = ______

69
 Using equation 7.5,
R1 = _______ ; R2 = _______

Let f = 2kHz, T = 0.5ms, C = 0.01µF

Using equation 8.3,

R5 = ______
R6 = ______
R3 = ______

Expected waveforms of VO and VO’:

Fig 7.2: Expected Waveforms of Vo’ and Vo

(Drawn on same time scale)

Procedure:
1. Setup the circuit as shown in Figure 7.1.
2. Set R6 = 0, keep R5a = R5b = R5/2
3. Observe the waveforms of Vo’ and Vo. Measure frequency and duty cycle.
4. Vary R5 to adjust duty cycle and record observations in Table 7.1.
5. Study variable frequency operation by adjusting R6 and record observations in Table 7.2 to 7.4.

Observations & Calculations:

Table 7.1: Variable duty cycle operation (R6 = 0)

70
 SL.N
R5 D f Vo’(p-p) Vo(p-p)
O
Theoretic Practica Theoretica Practica Theoretica Practica Theoretic Practica
1. R5a = 0
al l l l l l al l
2. R5a = R5/4
3. R5a = R5/2
4. R5a = 3R5/4
5. R5a = R5
Table 7.2: Variable duty cycle operation (R5a = R5/2)

SL.N
R6 D f Vo’(p-p) (V) Vo(p-p) (V)
O
Theoretic Practica Theoretica Practica Theoretica Practica Theoretic Practica
1. R6 = 0
al l l l l l al l
2. R6 = R6/4
3. R6 = R6/2
4. R6 = 3R6/4
5. R6 = R6

Waveforms for Vo’ and Vo for the observations in 7.1:

71
Waveforms for Vo’ and Vo for the observations in 7.2:

Inference:

Advantages:

Applications:

72
 Experiment – VIII

Design and testing of Astable Multi-vibrator using 555 Timer.

Aim:
To design Astable Multi-vibrator using 555 Timer and
iii) Study variable Duty cycle operation.
iv) Study Variable frequency operation.

Components Required:
Components/Equipment’s
SL.NO Specifications Quantity
Required
1. Timer 555 1
2. Resistors As per the design As required
3. Capacitors As per the design As required
4. DC regulated power supply 0-15V 1
5. CRO - 1
6. Signal generator - 1
7. Breadboard - 1
8. Connecting wires - As required
9. Diode 1N3909 2
10. Zener Diode 1N4733A 1
11. Potentiometer 12.025kΩ 1

Pre-requisites:
1. Functional block of 555 timer.
2. Operation of 555 timer as Astable Multivibrator.
3. Variable frequency and Duty cycle operation.

73
 Circuit Diagram:

Fig 8.1: Pin Diagram of 555 timer.

Fig 8.2: Astable Multivibrator using 555 timer.

1. Design Specifications:
Output Amplitude : ______
Frequency Range :500Hz to 5000Hz
Duty Cycle : 20% to 80%
±Vcc : ±12𝑉

Design Equations:

TON = (R1 + R3a + R4)C ------------8.1

TOFF = (R1 + R3b + R4)C ------------8.2
T = (2R1 + R3 + 2R4)C -------------8.3

74
 𝑇𝑜𝑛 𝑅 +𝑅 +𝑅
D= = 2𝑅1 + 𝑅3𝑎+ 2𝑅4 ----------8.4
𝑇 1 3 4

Design Procedure:

Calculate the values of R1, R3, R4 and C using the given specifications. Also design the limiting circuit.

Using equation 8.1,

R1 = _______
R4 = _______

Let f = 2kHz, T = 0.5ms, C = 0.01µF

R3 = _______
Expected waveforms of V0, V0’, VC:

Procedure:

1. Setup the circuit as shown in Figure 8.2.

2. Set R4 = 0, keep R3a = R3b = R3/2.
3. Observe the waveforms of Vo, Vo’ and VC. Measure frequency and duty cycle.
4. Vary R5 to adjust duty cycle and record observations in Table 8.1.
5. Study variable frequency operation by adjusting R6 and record observations in Table 8.2.

75
Table 8.1: Variable duty cycle operation (R4 = 0)
D f Vo’(p-p) (V) Vo(p-p) (V)
SL.N
R5 Theoretic Practica Theoretica Practica Theoretica Practica Theoretic Practica
O
al l l l l l al l
1. R3a = 0
2. R3a = R3/4
3. R3a = R3/2
4. R3a = 3R3/4
5. R3a = R3

Table 8.2: Variable frequency operation (R3a = R3/2)

D f Vo’(p-p) (V) Vo(p-p) (V)
SL.N
R4 Theoretic Practica Theoretica Practica Theoretica Practica Theoretic Practica
O
al l l l l l al l
1. R4 = 0
2. R4 = R4/4
3. R4 = R4/2
4. R4 = 3R4/4
5. R4 = R4

Table 8.3: Variable duty cycle operation (R4 = 0)

VC(p-p) (V)
SL.N
R5 Theoretic Practica
O
al l
1. R3a = 0
2. R3a = R3/4
3. R3a = R3/2
4. R3a = 3R3/4
5. R3a = R3

76
Table 8.4: Variable frequency operation (R3a = R3/2)
VC(p-p) (V)
SL.N
R4 Theoretic Practica
O
al l
1. R4 = 0
2. R4 = R4/4
3. R4 = R4/2
4. R4 = 3R4/4
5. R4 = R4

Waveforms for Vo’, Vo and VC for the observations in 8.1 & 8.3:

Waveforms for Vo’, Vo and VC for the observations in 8.2 & 8.4:

77
Inference:

Advantages:

Disadvantages:

Applications:

78
 Experiment – IX

Design and testing of Voltage Regulator using 723

Aim:
1. To design low voltage regulator using 723 and obtain load & line regulations.
2. To design high voltage regulator using 723 and obtain load & line regulations.

Components Required:
Components/Equipment’s
SL.NO Specifications Quantity
Required
1. Voltage Regulator IC IC 723 1
2. Resistors As per the design As required
3. Capacitors As per the design As required
4. DC regulated power supply 0-15V 1
5. CRO - 1
6. Signal generator - 1
7. Breadboard - 1
8. Connecting wires - As required
9. Decade resistance box - 1

Pre-requisites:
4. Need for voltage regulator, load and line regulations.
5. Functional Block diagram of 723.
6. Low and high voltage regulators using 723.
7. Current limiting, current boosting, fold back current limiting.

79
 Low Voltage Regulator

Circuit Diagram:

Fig 9.1: Pin Diagram of IC 723. Fig 9.2: Circuit Connection for testing IC 723.

VCC

Fig 9.3: Low voltage Regulator using IC 723.

Design Specifications:
VO = 15V
IL = 100mA
Vin = 10V±20%

80
Design Procedure:

𝑅2
V0 = Vref [𝑅 ]
1 + 𝑅2

Vref = _____
Assume R1 and calculate R2.
R1 = _____
R2 = _____

R3 = R1||R2
R3 = _____

𝑉𝑜
RL(min) = [𝐼 ]
𝐿(𝑚𝑎𝑥)

5𝑉
= [100𝑚𝐴]

= _____

Procedure:
1. Setup the circuit as shown in Figure 9.2. Apply DC voltage, V = 10V ( > Vref). Check voltage at pin
6. A voltage of 7.15V at this pin ensures that 723IC is intact.
2. Now connect the circuit as shown in Figure 9.3. Set the DC voltage Vin at 10V ( > Vref) and adjust
the RL at 1KΩ. Measure IL & Vo.
3. Vary RL in suitable steps from 1kΩ to 50Ω (RL(min)). At each step note down IL and Vo. Record
observations in Table 9.1.
1 1
4. Set RL for IL(MAX), 2 IL(MAX) and 4 IL(MAX), and at each step note down the corresponding VO.
1
5. Now set RL such that IL = 2 IL(MAX), with Vin unaltered at 10V. Then by varying Vin from 8V to 12V

in suitable steps note down Vin and VO. Record observations in Table 9.2.
6. Now connect the circuit as shown in Figure 93. Set the DC voltage Vin at 20V ( >Vo) and adjust the
RL at 1KΩ. Measure IL and Vo.
7. Repeat steps 3,4 and 5 and record observations in Table 9.3 and 9.4

81
Table 9.1: Load Regulation for low voltage regulator.
SL.NO RL (Ω) IL(mA) VO(V)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.

𝑉𝑁𝐿 − 𝑉𝐿𝑜𝑎𝑑
% load regulation = [ ] x 100.
𝑉𝐿𝑜𝑎𝑑

VNL = Vo when RL = ∞ (IL = 0).

1 1
VLoad = VO when IL = IL(MAX) or 2 IL(MAX) or 4 IL(MAX).

Calculate load regulation at each of these loads.

Calculation of % load regulation:

82
Table 9.2: Line Regulation for low voltage regulator.
SL.NO Vin(V) VO(V)
1.
2.
3.
4.
5.
6.
7.
8.
9.

∆𝑉
% line regulation = [∆𝑉 𝑜 ] x 100.
𝑖𝑛

Calculate line regulation for 3 sets of ∆ 𝑉𝑜 and ∆𝑉𝑖𝑛 .

83
 High Voltage Regulator

Circuit Diagram:

Fig 9.3: High Voltage Regulator using IC723.

Design Specifications:
VO = 15V
IL = 100mA
Vin = 20V±20%

Design Procedure:
𝑅1
V0 = Vref [1 + ]
𝑅2

Vref = _______
Assume R1 and calculate R2.
R1 = _______
R2 = _______

R3 = R1||R2
R3 = _______

𝑉𝑜
RL(min) = [𝐼 ]
𝐿(𝑚𝑎𝑥)

15𝑉
= [100𝑚𝐴]

= _____

84
Table 9.3: Load Regulation for high voltage regulator.
SL.NO RL(Ω) IL(mA) VO(V)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

𝑉𝑁𝐿 − 𝑉𝐿𝑜𝑎𝑑
% load regulation = [ ] x 100.
𝑉𝐿𝑜𝑎𝑑

VNL = Vo when RL = ∞ (IL = 0).

1 1
VLoad = VO when IL = IL(MAX) or 2 IL(MAX) or 4 IL(MAX).

Calculate load regulation at each of these loads.

Calculation of % load regulation:

85
Table 9.4: Line Regulation for low voltage regulator.
SL.NO Vin(V) VO(V)
1.
2.
3.
4.
5.
6.
7.
8.
9.

∆𝑉
% line regulation = [∆𝑉 𝑜 ] x 100.
𝑖𝑛

Calculate line regulation for 3 sets of ∆ 𝑉𝑜 and ∆𝑉𝑖𝑛 .

Inference:

Advantages:

86
Disadvantages:

Applications:

87