Introduction to

CMOS VLSI
Design

CMOS Transistor Theory

 Outline
❑ Introduction
❑ nMOS I-V Characteristics
❑ pMOS I-V Characteristics
❑ Gate and Diffusion Capacitance
❑ Pass Transistors
❑ RC Delay Models

MOS devices CMOS VLSI Design Slide 2

 Introduction
❑ Integrated circuits: many transistors on one chip.
– Very Large Scale Integration (VLSI): very many

❑ Metal Oxide Semiconductor (MOS) transistor

– Fast, cheap, low-power transistors
– Complementary: mixture of n- and p-type leads to
less power

❑ CMOS – CoMplementary Oxide Semiconductor

Fabrication and Layout CMOS VLSI Design Slide 3

 Silicon Lattice
❑ Transistors are built on a silicon substrate
❑ Silicon is a Group IV material
❑ Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

Fabrication and Layout CMOS VLSI Design Slide 4

 Dopants
❑ Silicon is a semiconductor
❑ Pure silicon has no free carriers and conducts poorly
❑ Adding dopants increases the conductivity
❑ Group V: extra electron (n-type)
❑ Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

Fabrication and Layout CMOS VLSI Design Slide 5

 p-n Junctions
❑ A junction between p-type and n-type semiconductor
forms a diode.
❑ Current flows only in one direction

p-type n-type

anode cathode

Fabrication and Layout CMOS VLSI Design Slide 6

 Review: Reverse Bias Diode
❑ The ideal diode equation (for both forward
and reverse-bias conditions) is
+
ID = IS(e VD/ T – 1)
VD
-
where VD is the voltage applied to the junction
– a forward-bias lowers the potential barrier
allowing carriers to flow across the 2.5

diode junction
– a reverse-bias raises the 1.5

potential barrier and the

diode becomes nonconducting 0.5

T = kT/q = 26mV at 300K

IS is the saturation current of the diode -0.5
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1

VD (V)

CMOS VLSI Design

Review: Design Abstraction Levels

SYSTEM

MODULE
+
GATE

CIRCUIT
Vin Vout

DEVICE
G
S D
n+ n+

CMOS VLSI Design

The MOS Transistor
Polysilicon
Aluminum

CMOS VLSI Design

 The NMOS Transistor Cross Section

n areas have been doped with donor ions (arsenic) of concentration ND -

electrons are the majority carriers
Gate oxide
Polysilicon
W Gate
Source Drain Field-Oxide
n+ n+ (SiO2)
L

p substrate
p+ stopper

Bulk (Body)
p areas have been doped with acceptor ions (boron) of
concentration NA - holes are the majority carriers

CMOS VLSI Design

Switch Model of NMOS Transistor

| VGS | Gate

Source Drain
(of carriers) (of carriers)

Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’)

Ron

| VGS | < | VT | | VGS | > | VT |

CMOS VLSI Design

Switch Model of PMOS Transistor
Gate
| VGS |

Source Drain
(of carriers) (of carriers)

Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’)

Ron

| VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| |

CMOS VLSI Design

 Terminal Voltages
❑ Mode of operation depends on Vg, Vd, Vs Vg

– Vgs = Vg – Vs Vgs
+ +
Vgd
– Vgd = Vg – Vd - -

– Vds = Vd – Vs = Vgs - Vgd Vs

-
Vds +
Vd

❑ Source and drain are symmetric diffusion terminals

– By convention, source is terminal at lower voltage
– Hence Vds  0
❑ nMOS body is grounded. First assume source is 0 too.
❑ Three regions of operation
– Cutoff
– Linear
– Saturation

MOS devices CMOS VLSI Design Slide 13

 nMOS Cutoff
❑ No channel
❑ Ids = 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

MOS devices CMOS VLSI Design Slide 14

 nMOS Linear
❑ Channel forms
❑ Current flows from d to s
V > Vt
– e from s to d Vgd = Vgs
gs
- + g +
- -
❑ Ids increases with Vds s d
Vds = 0
n+ n+
❑ Similar to linear resistor p-type body
b

The current is a linear Vgs > Vt

Vgs > Vgd > Vt
+ g +
function of both VGS and - -
s Ids
d
VDS
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

MOS devices CMOS VLSI Design Slide 15

 I-V Characteristics
❑ In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

MOS devices CMOS VLSI Design Slide 16

 Carrier velocity
❑ Charge is carried by e-
❑ Carrier velocity v proportional to lateral E-field
between source and drain
❑ v = mE m called mobility
❑ E = Vds/L
❑ Time for carrier to cross channel:
– t=L/v

MOS devices CMOS VLSI Design Slide 17

 nMOS Linear I-V
❑ Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds =
t
= mCox
W  V − V − Vds V
 gs  ds
 2 
t
L
W
=   Vgs − Vt − ds  Vds
V  = mCox
 2 L

MOS devices CMOS VLSI Design Slide 18

Voltage-Current Relation: Linear Mode

For long-channel devices (L > 0.25 micron)

❑ When VDS  VGS – VT
ID = k’n W/L [(VGS – VT)VDS – VDS2/2]
where
k’n = mnCox = mnox/tox = is the process transconductance
parameter (mn is the carrier mobility (m2/Vsec))
kn = k’n W/L is the gain factor of the device
For small VDS, there is a linear dependence between VDS and
ID, hence the name resistive or linear region

CMOS VLSI Design

 nMOS Saturation
❑ Channel pinches off Vgs > Vt
g Vgd < Vt
+ +
❑ Ids independent of Vds -
s
-
d Ids

❑ We say current saturates n+ n+

Vds > Vgs-Vt
p-type body
❑ Similar to current source b

VGS
G VDS
S
D ID

n+ - + n+
VGS - VT

Pinch-off
VDS > VGS - VT

B
MOS devices CMOS VLSI Design Slide 20
 nMOS Saturation I-V
❑ If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
❑ Now drain voltage no longer increases current

I ds =   Vgs − Vt − dsat V
V
 dsat
 2 

( − Vt )
2
= V gs
2

MOS devices CMOS VLSI Design Slide 21

 Voltage-Current Relation: Saturation Mode

For long channel devices

❑ When VDS  VGS – VT
ID’ = k’n/2 W/L [(VGS – VT) 2]

since the voltage difference over the induced channel (from the
pinch-off point to the source) remains fixed at VGS – VT
❑ However, the effective length of the conductive channel is
modulated by the applied VDS, so
ID = ID’ (1 + VDS)
where  is the channel-length modulation (varies with the inverse of
the channel length)

CMOS VLSI Design

 Current Determinates
❑ For a fixed VDS and VGS (> VT), IDS is a function of
– the distance between the source and drain – L
– the channel width – W
– the threshold voltage – VT
– the thickness of the SiO2 – tox
– the dielectric of the gate insulator (e.g., SiO2) – ox
– the carrier mobility
• for nfets: mn = 500 cm2/V-sec
• for pfets: mp = 180 cm2/V-sec

CMOS VLSI Design

 The Threshold Voltage
VT = VT0 + (|-2F + VSB| - |-2F|)
where
VT0 is the threshold voltage at VSB = 0 and is mostly a function of the
manufacturing process
Difference in work-function between gate and substrate material, oxide
thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of
implanted ions, etc.

VSB is the source-bulk voltage

F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at 300K is the thermal
voltage; NA is the acceptor ion concentration; ni  1.5x1010 cm-3 at 300K is the
intrinsic carrier concentration in pure silicon)

 = (2qsiNA)/Cox is the body-effect coefficient (impact of changes in VSB)

(si=1.053x10-10F/m is the permittivity of silicon; Cox = ox/tox is the gate oxide
capacitance with ox=3.5x10-11F/m)

CMOS VLSI Design

 The Body Effect
0.9
0.85 VSB is the substrate
0.8
bias voltage (normally
0.75
0.7 positive for n-channel
0.65 devices with the body
0.6 tied to ground)
0.55
0.5
0.45
A negative bias
0.4 causes VT to increase
-2.5 -2 -1.5 -1 -0.5 0 from 0.45V to 0.85V
VBS (V)

CMOS VLSI Design

 Example
❑ Example: a 0.6 mm process from AMI semiconductor
– tox = 100 Å
– m = 350 cm2/V*s 2.5
V =5
– Vt = 0.7 V
gs

2
❑ Plot Ids vs. Vds 1.5 V =4

Ids (mA)
gs

– Vgs = 0, 1, 2, 3, 4, 5 1
– Use W/L = 4/2  0.5
V =3 gs

Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
W  3.9 • 8.85  10 −14   W  W Vds
 = m Cox = ( 350 )  −8   = 120 m A /V 2
L  100  10  L  L

MOS devices CMOS VLSI Design Slide 26

 Long Channel I-V Plot (NMOS)
X 10-4

6
VDS = VGS - VT VGS = 2.5V
5
2.07V
4 1.57V VGS = 2.0V
3 Linear Saturation

2 VGS = 1.5V
1 1.07V VGS = 1.0V
0 0.57V
0 0.5 1 1.5 2 2.5
cut-off
VDS (V)
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.43V
CMOS VLSI Design
 nMOS I-V Summary
❑ Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds =    Vgs − Vt −  ds linear
 2 
ds dsat

 
(Vgs − Vt )
2
 Vds  Vdsat saturation
2

MOS devices CMOS VLSI Design Slide 29

 pMOS I-V
❑ All dopings and voltages are inverted for pMOS
– Source is the more positive terminal
❑ Mobility mp is determined by holes
– Typically 2-3x lower than that of electrons mn
– 120 cm2/V•s in AMI 0.6 mm process
0

❑ Thus pMOS must be wider to

Vgs = -1
Vgs = -2

-0.2
provide same current Vgs = -3

– In this class, assume

Ids (mA)
-0.4
Vgs = -4

mn / mp = 2 -0.6

Vgs = -5
-0.8
-5 -4 -3 -2 -1 0
Vds

3: CMOS Transistor Theory CMOS VLSI Design 30