[EE1-02]

SOLUTIONS
Question 1

(a)
𝐴 + 𝐴̅𝐵 = (𝐴 + 𝐴𝐵) + 𝐴̅𝐵 = 𝐴 + 𝐵(𝐴 + 𝐴̅) = 𝐴 + 𝐵
[4]
(b)
(i)
𝐵 + (𝐶⨁𝐵&)(𝐴𝐵 + 𝐶̅ ) = 𝐵 + (𝐶𝐵 + 𝐶& 𝐵
*)(𝐴𝐵 + 𝐶̅ ) = 𝐵 + 𝐴𝐵𝐶 + 𝐶& 𝐵
*

= 𝐵 + 𝐶& 𝐵
* = 𝐵 + 𝐶&
[4]
(ii)

***********
𝐴𝐵 + 𝐴𝐶 + 𝐴 + **** ****
𝐵 𝐶 = 𝐴𝐵 𝐴𝐶 + 𝐴 +
𝐵 𝐶 = (𝐴̅ + 𝐵*)(𝐴̅ + 𝐶̅ ) + 𝐴 +
𝐵𝐶

= 𝐴̅ + +𝐵 𝐶̅ + 𝐴 +𝐵 𝐶 = 𝐴̅ + 𝐵
* (𝐶̅ + 𝐴𝐶) = 𝐴̅ + 𝐵* (𝐶̅ + 𝐴) = 𝐴̅ + 𝐵* 𝐶̅ + 𝐴𝐵+

= 𝐴̅ + 𝐵* + 𝐵* 𝐶̅ = 𝐴̅ + 𝐵*
[4]

(c)
𝑓 = 𝐴̅𝐵𝐶̅ 𝐷 + 𝐴𝐵*𝐶𝐷 + 𝐴̅𝐵𝐶 + 𝐴𝐵
* 𝐶 + 𝐴𝐵*𝐶̅ 𝐷

𝑓 = 𝐴̅𝐵𝐷 + 𝐴̅𝐵𝐶 + 𝐴𝐵*𝐷 + 𝐴𝐵*𝐶

= (𝐴̅𝐵 + 𝐴𝐵
* )𝐷 + (𝐴̅𝐵 + 𝐴𝐵*)𝐶
= (𝐴⨁𝐵)(𝐶 + 𝐷)

Here, 1 mark for the Karnaugh map, 2 for the correct values and grouping in the map, and
1 for the SOP final expression (first line in Boolean expression above). Remaining 2 marks
for converting to a form using one XOR gate (final expression).
[4 + 2]

(d)

Decimal Hexadecimal Signed binary (8 bits wide) Octal

254 375
-17 1110 1111
197 627

Give 2 marks per answer.

[6]

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 [EE1-02]

(e)

Z X Y D = next Z
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

Give 2 marks for correct form of truth table, 4 marks for D = next Z

(f)
With two N bit numbers multiplied together, the result has the range:

−(2!"#! − 2"#$ ) 𝑡𝑜 2!"#!

2 marks for the correct range

This needs 2N bits. Note that it nearly fits into 2N-1 bits, whose range extends to 22N-2 -
1. Give 2 marks for this part.
[4]

g)
𝑓 = 𝐴̅ 𝐵* + 𝐴𝐵 + 𝐴̅𝐶

This gives the truth table:

A B C f
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

As BC must be used on the select lines of the 4 ´ 1 MUX, we draw a table with BC
arranged along the rows and A along the columns. Furthermore, we choose to connect
C = S0 and B = S1.

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 [EE1-02]

S1 S0

BC
A 00 01 11 10
0 1 1 1 0

1 0 0 1 1
I0 I1 I3 I2
=A =A =1 =A
2 marks up to this stage

This gives the following implementation:

C 0 0
G
B 1 3

MUX
A 0
A 1 f
A 2

1 3

2 marks for this.

Note: An alternative solution has B = S0 and C = S1. We would then have I0 = A(bar), I1
= A, I3 = 1, and I2 = A(bar).
[4]

(ii) Using two 2 ´ 1 MUXs, we first need to rearrange the given function in the form of the
Boolean function for the output Z for a 2 ´ 1 MUX, with select input S:

𝑍 = 𝑆̅𝐼0 + 𝑆𝐼1

For the given function, we then have:

𝑓 = 𝐴̅ 𝐵* + 𝐴𝐵 + 𝐴̅𝐶 = 𝐴̅(𝐵* + 𝐶) + 𝐴𝐵

Comparison with the expression for Z gives:

𝐼0 = (𝐵* + 𝐶) = 𝑔, 𝐼1 = 𝐵, 𝑆 = 𝐴

Give 2 marks upto this stage.

We then need to implement B + C using a second 2 ´ 1 MUX. Choosing C for the select
line (the alternative of B on the select line is also fine) and inspecting the following map:

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 [EE1-02]

C
B 0#######1

0 1 1

1 0 1
I0& I1
=&B =1

This gives the implementation of the second 2 ´ 1 MUX, with I0 = B(bar) and I1 = 1. The
final implementation is given below (2 marks). Note that other solutions are also possible,
full marks should be given for any working solution using the two multiplexers and if
needed, some inverters):

C G1

A G1
MUX
B 1
g MUX
1 1 1
f
B 1

[4]

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 [EE1-02]

Question 2

1. (a) Using the states S0, S1, S2 and S3 to define the FSM, the following state diagram can
be obtained. Note that as there are two inputs X1, X2, each state has 22 = 4 transitions
possible. Furthermore, a sequence of two input combinations, one after the other, is needed
to change the output. For example, for the sequence X1X2 = 11, 10, the first part, X1X2 =
11 causes a transition from S0 to S1, and the second part, X1X2 = 10, causes a transition
from S1 to S2, and Z = 0 to Z = 1.

Give 2 marks for identifying this reasoning.

01,10

11,00
10
11,00
01,00
01

01,00
10

11
11,10

Give 2 marks for showing four states, 4 for the correct interconnections, and 4 for the correct
input/output values.
[12]

(b) Using the encoding system given, the state diagram can be converted into the following
table, with Q3Q2Q1Q0 as the present state of the FSM, and Q3+Q2+Q1+Q0+ as the next state:

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 [EE1-02]

Q3 Q2 Q1 Q0 X1 X2 Q3+ Q2+ Q1+ Q0+ Z

0 0 0 1 0 0 0 0 1 0 0
0 0 0 1 0 1 0 0 0 1 0
0 0 0 1 1 0 0 0 0 1 0
0 0 0 1 1 1 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 0
0 0 1 0 0 1 0 1 0 0 0
0 0 1 0 1 0 0 0 0 1 0
0 0 1 0 1 1 0 0 1 0 0
0 1 0 0 0 0 1 0 0 0 1
0 1 0 0 0 1 1 0 0 0 1
0 1 0 0 1 0 0 1 0 0 1
0 1 0 0 1 1 0 1 0 0 1
1 0 0 0 0 0 1 0 0 0 1
1 0 0 0 0 1 1 0 0 0 1
1 0 0 0 1 0 0 0 0 1 1
1 0 0 0 1 1 0 1 0 1 1

Give 0.5 marks for each row.

[8]

(c) As the FSM states are encoded using 1-hot encoding, the Boolean equations can be written
directly by inspection:

****𝑋2 + 𝑄0𝑋1𝑋2
𝑄0% = 𝑄0𝑋1 **** + 𝑄3𝑋1𝑋2
**** + 𝑄3𝑋1𝑋2 = 𝑄0𝑋1
****𝑋2 + 𝑄0𝑋1𝑋2
**** + 𝑄3𝑋1

**** ****
𝑄1% = 𝑄0𝑋1 **** 𝑋2
𝑋2 + 𝑄0𝑋1𝑋2 + 𝑄1 𝑋1 **** + 𝑄1𝑋1𝑋2

****𝑋2 + 𝑄2 𝑋1 𝑋2
𝑄2% = 𝑄1𝑋1 **** + 𝑄2𝑋1𝑋2 + 𝑄3𝑋1𝑋2 = 𝑄1𝑋1
****𝑋2 + 𝑄2 𝑋1 + 𝑄3𝑋1𝑋2

**** 𝑋2
𝑄3% = 𝑄2𝑋1 **** + 𝑄2 𝑋1
**** 𝑋2 + 𝑄3𝑋1
**** 𝑋2
**** + 𝑄3𝑋1
**** 𝑋2 = 𝑄2 𝑋1
**** + 𝑄3𝑋1
****

𝑍 = 𝑄3 + 𝑄2

Give 2 marks for each Boolean expression.

[10]

Page 6 of 10
3. Figure 3.2 shows the datapath of a new CPU DECA21 comprising a register file RF1,
a binary adder, and other logic. The datapath implements the ALU instructions shown
in Figure 3.3. The format of the ALU instructions is shown in Figure 3.1. OP, OPC,
d,m,n in Figure 3.2 refer to the unsigned binary values of bit fields OP, OPC, D, M, N in
Figure 3.1. Other instructions, not shown here, are executed when OP=1. The W input
to RF1 in Figure 3.2 is 1 during every cycle in which the ALU instructions are executed.
W may also be 1 when other instructions are executed. Cycles with W=0 do not change
any of the datapath registers.
a) For DECA21 state, giving reasons, the number of operands of the Figure 3.3
instructions, the data word size, and number of datapath registers. Discuss
whether the architecture is von Neumann, or Harvard, or could be either. [4]

Analysis of a new example. 3 operands: because the three IW fields d,n,m each specifying

S
registers). 8 bit data word size because ALU and register databuses are all 8 bits.The register
operands are 6 bits wide =¿ 64 registers. It must be Harvard architecture because the instruc-
tion word is different size from the data word. (I will allow an argument that says it could
possibly also be von Neumann only if it is stated that this is unlikely).

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b) State two distinct types of necessary instructions not shown here that would be
expected in any CPU. [2]
 
bookwork. Jump instructions and memory load/store instructions
 
c) State the largest positive and negative two’s complement values in 8 bits. An
8 bit two’s complement subtraction A := B - C is defined to overflow if and
SW
only if the following condition holds:
z(A(7:0)) 6= z(B(7:0)) − z(C(7:0))
where z(x) is the two’s complement interpretation of a binary field x. State the
boolean condition on the bits of A, B, C that computes overflow. [4]
 
calculated example and bookwork. +127 -128. We require output sign to be different from
that of both of the two inputs: (A7 ⊕ B7).(A7 ⊕ C7).
 
N

d) Using the instructions from Figure 3.3 write in mnemonic form a sequence of
instructions that will implement R0 := 15×R1. Credit will be given for code
that changes the minimum number of registers and uses the minimum number
of instructions. [4]
 
A

design.
ADD R0, R1, R1
ADD R0,R0, R0
ADD R0, R0, R0
ADD R0, R0, R0
SUB R0, R0, R1
deduct one mark if other registers change. deduct 2 marks if more than 5 instructions.
 
e) Write in mnemonic form a sequence of two ARM data processing instructions
together implementing R0 := 1023×R1 + 0x0850000. For each instruction
state the precise shift or rotate operation used in the ARM Op2 logic. [4]

Digital Electronics and Computer Architecture ©Imperial College London 7/10

  
calculated example. RSB R0, R1, R1, LSL #10 logical shift left by 10 - to implement X1024.
ADD R0, R0, #0x085000 the op2 number is generated by rotating right 0x85 12 bits.
 
f) State how input busses A1,A2,A3 in Figure 3.2 are connected to the instruction
word bits IW(21:0). [2]
 
analysis. A3=D, A1=N, A2=M. IW Bit fields as shown in Figure 3.1.
 
g) Derive a boolean expression for FF1.EN, from IW(21:0) and W, implementing
Figure 3.3. [2]

FF1 is used to save carry (C) from one addition to be used in the next one. FF1.EN =

S
W.not(IW21).not(IW20.not(IW19).not(IW18)). 1 mark deducted if W is not correctly in-
cluded.

h) Figure 3.4 shows the logic function of block BX. Write a truth table implement-

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ing the instructions in Figure 3.3 with OPC as input and B1, B0, MUX1.sel,
MUX1.0 outputs. Outputs in your truth table which are don’t care must be
marked X. [8]
 

OPC B(1:0) MUX1.0 MUX1.sel

000 00 0 0
001 01 1 0
SW
010 00 X 1
Design. 011 01 X 1
100 10 0 0
101 10 X 1
110 10 1 0
111 11 0 0
Also allow B(1:0)=11, MUX1.0=1, MUX1.sel=0 as alternative for MOV.
 
N

Field OP OPC D M N
A

Bits used IW21 IW(20:18) IW(17:12) IW(11:6) IW(5:0)

Figure 3.1: Fields in a 22 bit Instruction Word (IW)

Digital Electronics and Computer Architecture ©Imperial College London 8/10

 A2 B(1:0) FF1.EN

EN
2
D Q
6 B FF1
Addr2
A3 Port2 8 8
Dout2 IN OUT
RF1 BX1
Register File 8 Cout
W 6 P
Addr3 8 MEM.Din
Wen3 Port3 adder Sum
Din3 8 8
8 Dout1 Q Cin
Port1

S
Addr1
6
MUX1.sel
sel MUX1
MUX2.sel 0 1
A1

ER
MUX1.0

MUX2 sel
8

0
8 MEM.Dout
1

Figure 3.2: Datapath Block Diagram

SW
N
A

Digital Electronics and Computer Architecture ©Imperial College London 9/10

 Mnemonic Form OP OPC Operation C
ADD Rd, Rn, Rm 0 000 Rd := Rn + Rm write C
SUB Rd, Rn, Rm 0 001 Rd := Rn - Rm write C
ADC Rd, Rn, Rm 0 010 Rd := Rn + Rm + C write C
SBC Rd, Rn, Rm 0 011 Rd := Rn - Rm + C - 1 write C
MOV Rd, Rn 0 100 Rd := Rn hold C
MOVC Rd, Rn 0 101 Rd := Rn + C write C
MOVP Rd, Rn 0 110 Rd := Rn + 1 write C
MOVN Rd, Rn 0 111 Rd := Rn - 1 write C

Figure 3.3: DECA21 Instructions: C is written with carry out from the adder where shown, no other
instruction writes C

S
B1 B0 BX.IN BX.OUT
0 0 a a

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0 1 a a with bits inverted
1 0 X 00000000
1 1 X 11111111

Figure 3.4: Block BX operation

SW
N
A

Digital Electronics and Computer Architecture ©Imperial College London 10/10