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Module 2

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14 views

Module 2

Uploaded by

ajithstephen11
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BASIC PHYSICAL DESIGN AN OVERVIEW

INTRODUCTION

• When the devices are represented using different layers, we call it physical design.
• When we draw the layout from the schematic, we are taking the first step towards the physical design.
• Layout is representation of a schematic into layered diagram. This diagram reveals the different layers
like ndiff, polysilicon etc that go into formation of the device.
• The simplest way to begin a layout representation is to draw the stick diagram, but as the complexity
increases it is not possible to draw the stick diagrams.
• For beginners it easy to draw the stick diagram and then proceed with the layout for the basic digital gates.
• In the schematic representation lines drawn between device terminals represent interconnections.
• But in layout designs interconnection of different layers is not done just by simply drawing one layer
above the other because of the different characters of each layer.
• Contacts have to be made whenever such interconnection is required.
• The power and the ground connections are made using the metal and the common gate connection using
the polysilicon.
• The metal and the diffusion layers are connected using contacts.
The crossing over of layers is another aspect
1. Poly crossing diffusion makes a transistor
2. Metal of the same kind crossing causes a short.
3. Poly crossing a metal causes no connection between them unless a contact is made.
Different design tricks need to be used to avoid unknown creations. Like a combination of metal1 and metal2 can
be used to avoid short. Usually metat2 is used for the global vdd and vss lines and metal1 for local connections.
Set of guidelines to be followed while drawing stick diagram

• Metal (blue) may cross over diffusion (green n-diffusion /yellow p-diffusion) or polysilicon (red)
without a connection as shown in fig a.
• An n-mos is formed when ever poly (red) crosses over n-diffusion (green) as shown in fig b.
• An p-mos is formed when ever poly (red) crosses over p-diffusion (yellow) and this must be placed in n-
well boundary this well is indicated using a demarcation line (brown) as shown in fig c.
• We use via to connect two different metal layers as shown in fig d.
• Connections between layers are specified by x or dot as shown in fig e.

• The first step in stick diagram is to draw the metal (blue) Vdd and Vss rails in parallel and creation of a
(imaginary) demarcation line in between these two lines.
• The N-FET are placed below the demarcation line and above Vss, while the P-FET are placed above the
demarcation line and below Vdd line.
• The n and p transistors are then connected using metal and contacts as shown n below fig.
• Finally, the remaining interconnections are made and appropriate control signals and data inputs are
added.
Designing using CMOS logic:
Construction of stick diagram for the NMOS logic schematic:
Complex Logic Gate with CMOS logic:
Design of FET Array:

Lambda Based Design Rules:


• Design rules are set of guidelines that specify the minimum dimension and spacing allowed in the layout
drawing.
• Violating a design rule may result in a non-functional circuit, so these set of rules are important in
improving the die yield.
Types of design rules:
• Minimum width
• Minimum spacing
• Overlap(surround)
• Extension.
Lambda based design rules for conducting path (wires):

Lambda based design rules for Transistor:


Lambda based design rules for Contact Cuts:
Burried, Butting & VIA Contact:
SCHEMATIC AND LAYOUT OF BASIC GATES using CMOS logic
Schematic, Stick, Layout diagram of NAND GATE using CMOS logic:
Schematic, Stick, Layout diagram of NOR GATE using CMOS logic:

Schematic, Stick, Layout diagram of TRANSMISSION GATE:


DELAY UNIT:
Time constant is one standard gate area capacitance being charged through one future size square of nmos
resistance.

• Transit time is the time taken by the signal to reach from 0 to 63% of VDD

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