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Unit 2

Coa by Preet Raj

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9 views

Unit 2

Coa by Preet Raj

Uploaded by

preetraj710
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Unit -2

In ripple carry adders, for each adder block, the two bits that are to be added are
available instantly. However, each adder block waits for the carry to arrive from
its previous block. So, it is not possible to generate the sum and carry of any
block until the input carry is known. The ith block waits for the i-1 block to
produce its carry. So there will be a considerable time delay which is carry
propagation delay.
Here a carry signal will be generated in two cases:
1. Input bits A and B are 1
2. When one of the two bits is 1 and the carry-in is 1.

Consider the above 4-bit ripple carry adder. The sum S3 is produced by the
corresponding full adder as soon as the input signals are applied to it. But the
carry input C1 is not available on its final steady-state value until carry C3 is
available at its steady-state value. Similarly C3 depends on C2 and C1.
Therefore, though the carry must propagate to all the stages in order that
output S3 and carry C4 settle their final steady-state value.

Carry Look-ahead Adder :

A carry look-ahead adder reduces the propagation delay by introducing more


complex hardware. In this design, the ripple carry design is suitably transformed
such that the carry logic over fixed groups of bits of the adder is reduced to two-
level logic. Let us discuss the design in detail.
Consider the full adder circuit shown above with corresponding truth table. We
define two variables as ‘carry generate’ Gi and ‘carry propagate’ Ci then,
The sum output and carry output can be expressed in terms of carry generate Gi
and carry propagate Pi as

From the above Boolean equations we can observe that C4 does not have to wait
for C3 and C2 to propagate but actually C4 is propagated at the same time as C3
and C2.

BOOTH ALGORITHM:
Multiply the two numbers 23 and -9 by using the Booth's multiplication
algorithm.

Array multiplier
Shift Micro-Operations

Shift micro-operations are those micro-operations that are used for serial transfer
of information. These are also used in conjunction with arithmetic micro-
operation, logic micro-operation, and other data-processing operations.
There are three types of shifts micro-operations:
1. Logical :
It transfers the 0 zero through the serial input. We use the symbols shl for logical
shift-left and shr for shift-right.
Logical Shift Left

Right Logical Shift

2. Arithmetic :

This micro-operation shifts a signed binary number to the left or to the right
position. In an arithmetic shift-left, it multiplies a signed binary number by 2 and
In an arithmetic shift-right, it divides the number by 2.

Left Arithmetic Shift

Right Arithmetic Shift


3. Circular :

The circular shift circulates the bits in the sequence of the register around the
both ends without any loss of information.

Left Circular Shift

Right Circular Shift


Hardware Implementation Of Unsigned Binary Multiplication:

Multiplying Positive Numbers:

M=11(1011)

Q=13(1101)
Binary Adder-Subtractor

A Binary Adder-Subtractor is one which is capable of both addition and


subtraction of binary numbers in one circuit itself. The operation being
performed depends upon the binary value the control signal holds. It is one of the
components of the ALU (Arithmetic Logic Unit).
This Circuit Requires prerequisite knowledge of Exor Gate, Binary Addition and
Subtraction, Full Adder.
Lets consider two 4-bit binary numbers A and B as inputs to the Digital Circuit
for the operation with digits
o When the mode input (M) is at a low logic, i.e. '0', the circuit act as an adder
and when the mode input is at a high logic, i.e. '1', the circuit act as a
subtractor.
o The exclusive-OR gate connected in series receives input M and one of the
inputs B.
o When M is at a low logic, we have B⊕ 0 = B.
The full-adders receive the value of B, the input carry is 0, and the circuit
performs A plus B.
o When M is at a high logic, we have B⊕ 1 = B' and C0 = 1.
The B inputs are complemented, and a 1 is added through the input carry. The
circuit performs the operation A plus the 2's complement of B.
Restoring Division Algorithm For Unsigned Integer

Perform Division Restoring Algorithm


Dividend = 11
Divisor = 3

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