Programming Microprocessor –

Instruction Set Architecture III

CS2053 Computer Architecture
Computer Science & Engineering
University of Moratuwa

Sulochana Sooriyaarachchi
Chathuranga Hettiarachchi

Slides adopted from Dr.Dilum Bandara

Encoding Instructions
 Various instruction types
 Limited word size for registers, addresses, and
instructions
◼ Consider 32bit words in RV32I
◼ All the instructions are 32bits
◼ Example : If we need to load an immediate value to
32-bit register, how to fit all opcode and operands
within 32-bit instruction?
 Work with small numbers
 Make compromises

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Instruction Formats(Types)

 Fields
◼ Opcode : 7bits
◼ funct 3 : 3 bit function
◼ funct 7 : 7 bit function
◼ rs1, rs2 : two source registers (5 bits each)
◼ rd : destination register (5 bits)
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Instruction Formats (6 Types)
 R-Format: instructions using 3 register inputs
– add, xor, mul —arithmetic/logical ops
 I-Format: instructions with immediates, loads
– addi, lw, jalr, slli

 S-Format: store instructions: sw, sb

◼ SB-Format: branch instructions: beq, bge
 U-Format: instructions with upper immediates
– lui, auipc —upper immediate is 20-bits
◼ UJ-Format: jump instructions: jal

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 Instruction Format-Register Type

(Register Type)

For the complete standard specifications:

https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf 5
Instruction Format-Immediate Type

(Immediate Type)

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Instruction Format-Upper Immediate

Load Upper Immediate (lui)

lui t1,0x70070
Fill up the upper 20 bits of destination register with immediate value
Add Upper Immediate value and Program Counter (auipc)
auipc a0,0x2
Fill the upper 20 bits of destination register with immediate value
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Some RISC V Pseudo Instructions

Some more are available…

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 Memory Architectures

Source: Introduction to PIC Microcontroller – Part 1 by Khan Wahid

Von Neumann vs. Harvard
Architecture

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 Memory Addressing
 Place an
address on
address bus
 Read or write
operation
 Data placed on
data bus

Source: www.alf.sd83.bc.ca/courses/It12/using_it/processor_speed.htm

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Memory Addressing (Cont.)
9

No of words

Address Data

Word

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Addressing Modes
 It is the way microprocessor:
◼ Identifies location of data
◼ Access data

 Absolute address
◼ Actual physical address
◼ Direct addressing

 Relative address
◼ Address relative to a known reference
◼ Indirect addressing 13
Load and Store Instructions

Load: copy a value from memory to register rd : (Immediate type)

Source is a memory address
Store: copy the value in register rs2 to memory : (Store type)

Need the proper 32bit address

(Immediate type and Store type)

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Activity
 Try the following
program with RIPES
.data and explain the machine
A: .word 0x1F2F3F4F
.text code
.globl main
main:
la a0, A
la a0, A  What is the machine
la a0, A
ret code of la a0, A ?
.end
 Try to add a nop before
first la and revisit
machine code 15
la (Load Address) pseudo instruction

.data
A: .word 0x1F2F3F4F 000000d8 <main>:
.text d8: 00002517 auipc a0,0x2
dc: 0b050513 addi a0,a0,176 # 2188 <A>
.globl main e0: 00002517 auipc a0,0x2
main: e4: 0a850513 addi a0,a0,168 # 2188 <A>
la a0, A e8: 00002517 auipc a0,0x2
la a0, A ec: 0a050513 addi a0,a0,160 # 2188 <A>
la a0, A f0: 00008067 ret
ret
.end

 We wrote the same instruction, but it is converted

to different immediate values by assembler 16
Branching Instructions

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Branching Instructions
(Branch type)

 Change the Program Counter

 Change the Program Flow

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Branching Instructions

 Need to specify an address to go to

 Also take two registers to compare
◼ Conditional branch
 Doesn’t write into a register (similar to stores)
(destination register rd is not required)
 How to encode label, i.e., where to branch to?
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Branching Instructions -Addressing

 PC-relative addressing
◼ Use immediate field 12 bits as a two’s complement
offset to PC.
◼ Branches generally change the PC only by a small
amount. But what is the reach?
◼ Can specify [-211 , 211) address offsets from the PC

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Branching Instructions -Addressing
 Recall: RISCV uses 32-bit addresses, and
memory is byte-addressed
 Instructions are “word-aligned”: Address is
always a multiple of 4 (in bytes)
◼ Previous instruction offset : -4 bytes
◼ Next instruction offset : 4 bytes
◼ Only if compressed instructions (16 bytes) are used, it
could be multiple of 2 (in bytes) as well
 PC ALWAYS points to an instruction
◼ PC is typed as a pointer to a word
◼ can do C-like pointer arithmetic
Branching Instructions -Addressing
 Only 12 bits available for immediate offset
 Offset Range [-211 , 211) Ignore the lsb,
always zero
1 1 1 1 1 1 1 1 1 1 1 0 0 (only 12 bits)
Offset : -4
1 1 1 9 8 7 6 5 4 3 2 1 0
2 1 0
12 bit Immediate field Provision for compressed instructions
(Two’s complement) (For normal instructions, this also will be
always zero)

 Offset Range [-212 , 212)

We don’t
Offset : -4 1 1 1 1 1 1 1 1 1 1 1 1 0 0 do this
12 bit Immediate field 13 12 11 10 9 8 7 6 5 4 3 2 1 0
If we ignore both lsb’s we will have more reach, but 22
compressed instructions cannot be accommodated
Branch Calculation
 If we don’t take the branch:
◼ PC = PC+4 = next instruction
 Assume we have only normal 32bit instructions
 If we do take the branch:
◼ PC = PC + (immediate field *2)
 If we assume we only have normal 32bit instructions, lsb of
immediate field must be zero. If its one, there will be an error,
by PC pointing to a middle of the instruction

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 Branching Instructions (B type)
main: bne x5,x6,repeat
addi t0,zero,10 Offset : -4 = -000100
add t1,zero,zero bne t0,t1,repeat = 111011 +1
repeat:
= 111100 (Sign extended)
addi t1,t1,1
bne t0,t1,repeat 1 1 1 1 1 1 1 1 1 1 1 0 0
ret 1 1 1 9 8 7 6 5 4 3 2 1 0
.end 2 1 0

31 20 19 15 14 12 11 7 6 0

Imm[12|10:5] rs2 rs1 funct3 Imm[4:1|11] opcode

Immediate offset rs2 rs1 funct3 Immediate B type branch

[12|10:5] sw offset [4:1|11]
0 0 1 1 1 0 0 0 1 1
1 1 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 1 1 1 0 1
1 1 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 0 0 1 1
f e 6 2 9 e e 3

Machine Instruction: 0xFE629EE3 24

https://stackoverflow.com/questions/58414772/why-are-risc-v-s-b-and-u-j-instruction-types-encoded-in-this-way
Branching Instructions -Addressing

 S type and B type immediate value bits are

aligning well.
Imm[12:5] rs2 rs1 funct3 Imm[4:0] S type

Imm[12|10:5] rs2 rs1 funct3 Imm[4:1|11] B type

Zero except for branching to a compressed

Sign Bit instruction Extra bit in B type 25
 Branching Instructions -Addressing
 Pseudo Assembly /Disassembly

main:
addi t0,zero,10
add t1,zero,zero
repeat:
addi t1,t1,1
bne t0,t1,repeat
ret
.end

Remember
bne t0,t1,repeat
Machine Instruction: 0xFE629EE3
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Jump Instructions

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Jump Instructions

Jump to anywhere in memory

Need the proper 32bit address

Store a return address in a register (rd), so that you can come back
to original flow
Known as “Linking”
(Jump type and Immediate type)

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Jump Instructions
 For branches, we assumed that we won’t
want to branch too far, so we can specify a
change in the PC
 For (jalr) jumps, we may jump to
anywhere in code memory
◼ Ideally, we would specify a 32-bit memory address
to jump to
◼ Unfortunately, we can’t fit both a 7-bit opcode
and a 32-bit address into a single 32-bit word
◼ Also, when linking we must write to an rd register

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jal Instruction and j pseudo
instruction
 jal saves PC+4 in register rd (the return
address)
 Set PC = PC + offset (PC-relative jump)
 Target somewhere within ±219 locations, 2 bytes
apart
 “j” jump is a pseudo-instruction—the assembler
will instead use jal but sets rd=x0 to discard
return address
 Immediate encoding optimized similarly to
branch instruction to reduce hardware cost 30
jal Instruction Encoding
jal x1,-12 -12 = -001100
jal ra,myfunction = 110011 +1
= … 1111 1111 1111 0100
31 20 19 15 14 12 11 7 6 0

Imm [20|10:1|11|19:12] rd opcode

Immediate offset [20|10:1|11|19:12] Register for J type jump

return jal
address
1 1 0 1 1 1 1
1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1
0 0 0 0 1 1 1 0 1 1 1 1
F F 5 F F 0 E F

Machine Instruction: 0xFF5FF0EF 31

Re-ordering bits in J type
31 20 19 15 14 12 11 7 6

imm[11:0] rs1 funct3 rd I Type

Upper Imm[31:12] rd U type

Imm[20|10:1|11|19:12] rd J type

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jal Instruction Usage
.globl main
myfunc:
addi t0, zero, 1
ret

main:
addi t0, zero, 0
jal ra,myfunc
ret
.end

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jalr instruction (I type)
 Jump and link register jalr to address given in
rs1 register + imm offset

RISCV Instructions:
# ret and jr psuedo-instructions
ret = jr ra = jalr x0, ra, 0

# Call function at any 32-bit absolute address

lui x1, <hi 20 bits>
jalr ra, x1, <lo 12 bits>

# Jump PC-relative with 32-bit offset

auipc x1, <hi 20 bits>
jalr x0, x1, <lo 12 bits>
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jalr Instruction encoding

jalr x1, x1, 0

jalr ra, ra, 0

imm[11:0] rs1 funct3 rd Opcode (jalr)

0 0 0 1 1 0 0 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1
0 0 0 0 8 0 E 7

Machine Instruction: 0x000080E7 35

Linking Multiple Functions

.globl main
myfunc:
addi t0, zero, 1
ret

main:
addi t0, zero, 0
la ra,myfunc
jalr ra,ra,0
ret
.end

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.globl main
myfunc:
addi t0, zero, 1
ret

main:
addi t0, zero, 0
la ra,myfunc
jalr ra,ra,0
ret
.end

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Summary

 The Stored Program concept is very powerful

◼ Instructions can be treated and manipulated the
same way as data in both hardware and software
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Thank you.

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Example – Logic Operations
 Write an assembly program to convert a given
character from uppercase to lowercase & vice
versa
 If we consider ASCII, this can be achieved by
changing the 5th bit
◼ A = 65 =0x41 = 01000001
◼ a = 97 =0x61 = 01100001

 Get XOR with 00100000 = 32 = 0x20

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Homework
 Write an assembly program to multiply 3 & 4
 Steps:
◼ How many registers?
◼ What registers to use?
◼ What instructions to use?

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Exercise
 Which mask or filter value would you use, and
what operation would you perform to make the
2nd & 4th bits one (1) no matter what they were
before?

 Which mask or filter value would you use, and

what operation would you perform to flip the 2nd
& 4th bits no matter what they were before?

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Exercise: Convert to Assembly
int total = 0;
for (int i=10 ; i!=0; i--)
{
total += i;
}

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Exercise
 Write a program to calculate the total of all
integers from 1 to 10
 High-level program

int total = 0;
for (int i=1 ; i<=10; i++)
{
total += i;
}

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Exercise (Cont.)
 Steps
◼ Are there any conditions/loops?
◼ How many registers?
◼ What registers to use?
◼ What instructions to use?

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Summary
 Instruction Set Architecture (ISA) is the layer between
hardware & software
 Specific to a given chip unless standardized
◼ Defines registers it contain
◼ Micro-operations performed on data stored on those registers
 Typical Assembly instructions for
◼ Register operations
◼ Memory access (Load/Store)
◼ Upper immediates and Address calculations
◼ Branching
◼ Jump and Link
 Assembler translates human readable Assembly
code to machine code 46
Sign extended immediate values
 addi t1, t1, -0xFFFFFFFF # = 1 # ||
 addi t1, t1, -0xFFFFFFFE # = 2 # ||
 addi t1, t1, -0xFFFFFFFD # = 3 # ||
 addi t1, t1, -0xFFFFF801 # = 2047 # ||
 # addi t1, t1, -0xFFFFF800 # = 2048 (Out of range)
 # addi t1, t1, -0xFFFFF7FF # = 2049 (Out of range)
 # addi t1, t1, -0x00000801 # = -2049 (Out of range)
 addi t1, t1, -0x00000800 # = -2048 # ||
 addi t1, t1, -0x000007FF # = -2047 # ||
 addi t1, t1, -0x00000001 # = -1 # ||
 addi t1, t1, 0x00000000 # = 0 # ||
 addi t1, t1, 0x00000001 # = 1 # ||
 addi t1, t1, 0x000007FF # = 2047 # ||
 # addi t1, t1, 0x00000800 # = 2048 (Out of range)
 # addi t1, t1, 0x00000801 # = 2049 (Out of range)
 # addi t1, t1, 0xFFFFF7FF # = -2049 (Out of range)
 addi t1, t1, 0xFFFFF800 # = -2048
 addi t1, t1, 0xFFFFFFFE # = -2
 addi t1, t1, 0xFFFFFFFF # = -1

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Thank you!

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(Compare with RISC-V Instructions)

F→ file register
W→ working register
B→ bit
L→ literal (number)
Z→ conditional
execution
d→ destination bit
d=0 store in W
d=1 store in f
use , w or ,f instead

Source: Makis Malliris &

Sabir Ghauri, UWE

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