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Design Test1

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232 views4 pages

Design Test1

Uploaded by

gowthamasenthur
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Design_test

www.maven-silicon.com
VLSI Training Services
Setting standards in VLSI Design

Table of Contents

Part- 1: Digital ....................................................................................................................................... 3


Part- 2: Verilog...................................................................................................................................... 4

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VLSI Training Services
Setting standards in VLSI Design

Part- 1: Digital(25 Maks)

1. How many 2:4 decoders are used to implement 10:1024 decoder. (3M)

2. For the circuit given below, find the output Y and design a simpler circuit that has the
same output using only NAND gate. (4M)

3. Design a counter which counts the sequence 192,160,144,136,132,130,129 and repeat.


Note that this counter should be designed using only flip-flops. You are not allowed to
use any other logic componants. (7M)

4. The 3 DFF is given in the circuit. Initially Y2Y1Y0 = 111. what is the sequence for
Y0Y1Y2 at 237th clock cycle? (5M)

5. Design a sequence detector in Moore Model that receives binary data stream at its input,
X and signals when a combination '10101' arrives at the input by making its output to
be toggled. Assume overlapping sequence. (6M)

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VLSI Training Services
Setting standards in VLSI Design

Part- 2: Verilog(25 marks)

1. Draw the waveform for the following piece of Verilog code: (5 M)

2. Display the console output for the below code: (5 M)

3. Define $strobe & $monitor. Explain each of them with one example. (5M)

4. Derive a minimal state table for an FSM that acts as a 3bit parity generator. For every
3 bits observed on the input ′w′ during 3 consecutive cycles, the FSM generates the
parity p=1 if and only if the no. of 1s is odd.
[A] Draw the Mealy FSM as an overlapping sequence. (2 M)
[B] Write the RTL code for the design. (4 M)
[C] Write the TB and verify the RTL. (4 M)

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