Soham Bhattacharya

(+1)609-666-9725 | [email protected] | LinkedIn | GitHub | ResearchGate

Result-driven Ph.D. candidate seeking internship roles in computer hardware domains, with 5+ years of experience in
digital RTL and SoC design.

Education
Rowan University Glassboro, NJ
Doctor of Philosophy in Electrical and Computer Engineering, Major in Computer Architecture Jan. 2022 – Present
• GPA: 3.758/4.00 (Till ‘Spring 2024)
• Area of Focus : Computer Architecture | RISC-V-based hardware accelerator design | System-on-chip design | Digital
logic design and verification.
Heritage Institute of Technology Kolkata, WB
Master of Technology in VLSI Sep. 2018 – Sep. 2020
• GPA: 9.41/10.00

• Area of Focus : Reversible computing | VLSI | Computer Architecture | Digital logic design.
Heritage Institute of Technology Kolkata, WB
Bachelor of Technology in Electronics and Communication Engineering Aug. 2014 – Aug, 2018
• GPA: 6.89/10.00

Experience
Graduate Research Fellow Jan. 2022 – Present
Rowan University Glassboro, NJ
• Designed and deployed equation-based hardware accelerators using HDL languages for ODEs solvers on Zynq-7000 FPGA

EDA toolkit.
• Guided graduate and undergraduate projects as ECE Department representative.

• Responsible for mentoring undergraduate and professional groups in India on VLSI projects that might result in publications.

Graduate Teaching Fellow Sep. 2023 – Dec. 2023

Rowan University Glassboro, NJ
• Assisted 25+ students in designing, debugging, and analyzing the hardware components of a RISC-V processor using the

Verilog and VHDL languages in Xilinx Vivado and Intel Quartus Prime software environments.
Entrepreneurial Lead Sep. 2022 – May 2023
National Science Foundation Glassboro, NJ (Remote)
• Conducted interviews with over 15 customers, obtaining a $3,000 grant from the NSF I-Corps Regional Program to develop

the business model and study product-market fit.

• Engaged with over 100 professionals, securing a $50,000 grant from the NSF I-Corps National Program for customer

discovery and exploring knowledge transfer into processes and products for societal benefit.
VLSI Engineer Mar. 2021 – May 2021
Dxcorr Design Inc. Bangalore, Karnataka
• Involved in generating physical designs for multiple complex projects utilizing the Cadence Virtuoso Tool, targeting 90nm

and 45nm technology nodes.

Subject Matter Expert Apr. 2021 – Aug. 2021
Chegg Part-Time : Remote
• Answered Mathematics questions posted online by students from the US and worldwide on the platform.

Intern, Embedded Systems and IoT Dec. 2018 – Jan. 2019

Spatez Technology LLP. Thrissur, Kerala
• Involved in hands-on experience on different projects related to Embedded systems and IOT, starting from the projects of

LEDs, automatic railway systems, and the usefulness of the sensors, using the Arduino Uno microcontroller board based on
the ATmega328P.
Projects
SOC Design and Analysis for FPU-Based Adam-Bashforth Hardware Accelerator 2024 – Present
Rowan University Glassboro, NJ
• Currently developing a system-on-chip (SOC) with Xilinx Vivado and VHDL language, prioritizing parallel processing for

solving ordinary differential equations, enabling concurrent handling of multiple input sources.
Product-Based RISC-V Skilling Program 2024 – Present
VLSI System Design Remote
• Exploring RISC-V’s history, architecture, and Verilog simulations and unlocking processor functionalities with hands-on

exercises.
• Delving into Verilog code analysis and advanced instructions and mastering I/Os with practical, real-world implementations.

• Enhancing programming with C code and inline assembly and learning testbench strategies and functional simulation

techniques. (Web) (Github)

Hardware accelerator design-space exploration for FPU-Based RK solvers. 2022 – 2023
Rowan University Glassboro, NJ
• Designed RISC-V hardware accelerators for second, third, and fourth-order Runge-Kutta ODE solvers.

• Experimental findings published in IEEE ICECCE 2023 and IEEE ICEACE 2023 highlighted increased power consumption

with the fourth-order solver, especially at clock frequencies up to 100 MHz.

• Research includes detailed evaluations of power, FPGA resource utilization, and comprehensive summaries through

design-space exploration. (GitHub) (IEEE ICECCE 2023) (IEEE ICECACE 2023)

Hardware Acceleration for Euler, Modified Euler ODE solvers. 2022 – 2023
Rowan University Glassboro, NJ
• Utilizing single-precision floating-point IP support, power, and timing analyses were conducted for both the accelerators and

were deployed on the Zynq ZC702 FPGA evaluation board at a clock frequency of 2.85 MHZ.
• The total on-chip power consumed by the hardware accelerator for the Euler method is 0.191W, whereas, for the modified

Euler method, it slightly increases to 0.192W, indicating slightly higher power consumption for the latter. The accelerator for
the Euler method utilizes 9 percent of LUTs, while the modified Euler method utilizes 13 percent of LUTs.
• Accepted IEEE CSCI 2023 publication. (GitHub)
An Optimized Low-Cost 4x4 Multiplier circuit using Reversible Logic Gates. 2023
Rowan University Glassboro, NJ
• Proposed a low-cost 4 × 4 multiplier circuit module that showcases advancements in gate counts, garbage outputs, constant

inputs, and quantum cost, offering potential applications in nanotechnology systems. RTL design implemented on the Artix-7
FPGA board, simulation, and Xilinx ISE 14.7 software tool evaluation demonstrate its effectiveness.
• Published IN SPRINGER conference. (Springer)
Complex Reversible Combinational and Sequential Circuits 2019 – 2021
Heritage Institute of Technology Kolkata, WB
• Developed and analyzed several complex adders, multiplexers, decoders, and parity generators using reversible gates. Power

consumption and performance have been evaluated using VHDL and Verilog languages, resulting in several publications.

Skills
Hardware Description Languages: VHDL, Verilog, System Verilog, Chisel (Working Language).
Programming Languages: C, C++.
Software Tools: Xilinx Vivado, Xilinx SOC, Xilinx ISE Design Suite, Intel Quartus Prime.
Utilities: riscv-objdump.
Simulators: Vivado Simulator, Spike, Icarus Verilog, Modelsim, VCS (Synopsys)
Synthesis Tools: Yosys, Vivado Synthesis, DC
Developer Tools: Git, VS Code, Atom.
Layout design tool: Cadence Virtuoso Design Environment.
Debugging tools, Place & Route tools, Static Analysis tools : Verdi, ICC2, PT
Other: GTKWave, Cameo System Modeler, Arduino, GitHub, MS Office.
OS: Ubuntu, Kali Linux, Windows.
Other skills: LateX, Problem-Solving, Critical Thinking, Research and Development, Technical Writing, Public Speaking,
Interviewing, Team Player, leading several research groups, Mentoring.
Academic Publications: 10+ papers in international Conferences and Journals.
Technical Articles: 3 articles in electronic magazines.
Honors and Awards
• Graduate Research and Teaching Fellowship Award in the Department of ECE, Rowan University.
• Dean’s List Award for Exceptional Performance in 2022 (Spring & Fall Semesters).
• Reviewer for IEEE Access and Journal of Supercomputing.
• Editor Recognition for a published book “Futuristic Trends In Artificial Intelligence”: IIP Proceedings, Volume 2, 2022.
• Expert Talk on ‘Introduction to Digital VLSI IC Design’ by Department of Artificial Intelligence, Sri Sairam Engineering
College, India associated with IEEE.
• Bronze Medalist in M.Tech (VLSI).
• ‘InSc Young Researcher Award’ from the Institute of Scholars, India.