The Microprocessor and Its Architecture

INTRODUCTION
Here we present the microprocessor as a programmable device by first looking at its internal
programming model and then how its memory space is addressed. The architecture of the
family of Intel microprocessors is presented simultaneously, as are the ways that the family
members address the memory system.
The addressing modes for this powerful family of microprocessors are described for the real,
protected, and flat modes of operation. Real mode memory (DOS memory) exists at locations
00000H–FFFFFH, the first 1M byte of the memory system, and is present on all versions of the
microprocessor. Protected mode memory (Windows memory) exists at any location in the entire
protected memory system, but is available only to the 80286–Core2, not to the earlier 8086 or 8088
microprocessors. Protected mode memory for the 80286 contains 16M bytes; for the 80386–
Pentium, 4G bytes; and for the Pentium Pro through the Core2, either 4G or 64G bytes. With the
64-bit extensions enabled, the Pentium 4 and Core2 address 1T byte of memory in a flat memory
model. Windows Vista or Windows 64 is needed to operate the Pentium 4 or Core2 in 64-bit mode
using the flat mode memory to access the entire 1T byte of memory.

INTERNAL MICROPROCESSOR ARCHITECTURE

Before a program is written or any instruction investigated, the internal configuration of the micro-
processor must be known. This section of the chapter details the program-visible internal architec-
ture of the 8086–Core2 microprocessors. Also detailed are the function and purpose of each of these
 internal registers. Note that in a multiple core microprocessor each core contains the same program-
ming model. The only difference is that each core runs a separate task or thread simultaneously.

The Programming Model

The programming model of the 8086 through the Core2 is considered to be program visible
because its registers are used during application programming and are specified by the instructions.
Other registers, detailed later in this chapter, are considered to be program invisible because they
are not addressable directly during applications programming, but may be used indirectly during
system programming. Only the 80286 and above contain the program-invisible registers used to
control and operate the protected memory system and other features of the microprocessor.
Figure 2–1 illustrates the programming model of the 8086 through the Core2 microproces-
sor including the 64-bit extensions. The earlier 8086, 8088, and 80286 contain 16-bit internal

FIGURE 2–1 The programming 64-bit Names 32-bit Names 16-bit Names 8-bit Names
model of the 8086 through the
Core2 microprocessor including
the 64-bit extensions. RAX EAX AX AH AL
RBX EBX BX BH BL
RCX ECX CX CH CL
RDX EDX DX DH DL
RBP EBP BP

RSI ESI SI

RDI EDI DI

RSP ESP SP

64 bits
32 bits
16 bits

R8

R9

R10

R11

R12

R13

R14

R15

RFLAGS EFLAGS FLAGS

RIP EIP IP

CS

DS

ES

SS

FS

GS
 architectures, a subset of the registers shown in Figure 2–1. The 80386 through the Core2
microprocessors contain full 32-bit internal architectures. The architectures of the earlier 8086
through the 80286 are fully upward-compatible to the 80386 through the Core2. The shaded areas
in this illustration represent registers that are found in early versions of the 8086, 8088, or 80286
microprocessors and are provided on the 80386–Core2 microprocessors for compatibility to the
early versions
The programming model contains 8-, 16-, and 32-bit registers. The Pentium 4 and Core2
also contain 64-bit registers when operated in the 64-bit mode as illustrated in the programming
model. The 8-bit registers are AH, AL, BH, BL, CH, CL, DH, and DL and are referred to when
an instruction is formed using these two-letter designations. For example, an ADD AL,AH
instruction adds the 8-bit contents of AH to AL. (Only AL changes due to this instruction.) The
16-bit registers are AX, BX, CX, DX, SP, BP, DI, SI, IP, FLAGS, CS, DS, ES, SS, FS, and GS.
Note that the first 4 16 registers contain a pair of 8-bit registers. An example is AX, which con-
tains AH and AL. The 16-bit registers are referenced with the two-letter designations such as
AX. For example, an ADD DX, CX instruction adds the 16-bit contents of CX to DX. (Only DX
changes due to this instruction.) The extended 32-bit registers are EAX, EBX, ECX, EDX, ESP,
EBP, EDI, ESI, EIP, and EFLAGS. These 32-bit extended registers, and 16-bit registers FS and
GS, are available only in the 80386 and above. The 16-bit registers are referenced by the desig-
nations FS or GS for the two new 16-bit registers, and by a three-letter designation for the 32-bit
registers. For example, an ADD ECX, EBX instruction adds the 32-bit contents of EBX to ECX.
(Only ECX changes due to this instruction.)
Some registers are general-purpose or multipurpose registers, while some have special
purposes. The multipurpose registers include EAX, EBX, ECX, EDX, EBP, EDI, and ESI. These
registers hold various data sizes (bytes, words, or doublewords) and are used for almost any pur-
pose, as dictated by a program.
The 64-bit registers are designated as RAX, RBX, and so forth. In addition to the renam-
ing of the registers for 64-bit widths, there are also additional 64-bit registers that are called
R8 through R15. The 64-bit extensions have multiplied the available register space by more
than 8 times in the Pentium 4 and the Core2 when compared to the original microprocessor
architecture as indicated in the shaded area in Figure 2–1. An example 64-bit instruction is
ADD RCX, RBX, instruction, which adds the 64-bit contents of RBX to RCX. (Only RCX
changes due to this instruction.) One difference exists: these additional 64-bit registers (R8
through R15) are addressed as a byte, word, doubleword, or quadword, but only the rightmost
8 bits is a byte. R8 through R15 have no provision for directly addressing bits 8 through 15 as
a byte. In the 64-bit mode, a legacy high byte register (AH, BH, CH, or DH) cannot be
addressed in the same instruction with an R8 through R15 byte. Because legacy software does
not access R8 through R15, this causes no problems with existing 32-bit programs, which
function without modification.
Table 2–1 shows the overrides used to access portions of a 64-bit register. To access the
low-order byte of the R8 register, use R8B (where B is the low-order byte). Likewise, to access
the low-order word of a numbered register, such as R10, use R10W in the instruction. The letter
D is used to access a doubleword. An example instruction that copies the low-order doubleword
from R8 to R11 is MOV R11D, R8D. There is no special letter for the entire 64-bit register.

TABLE 2–1 Flat

mode 64-bit access to Register Size Override Bits Accessed Example
numbered registers.
8 bits B 7–0 MOV R9B, R10B
16 bits W 15–0 MOV R10W, AX
32 bits D 31–0 MOV R14D, R15D
64 bits — 63–0 MOV R13, R12
Multipurpose Registers
RAX RAX is referenced as a 64-bit register (RAX), a 32-bit register
(accumulator) (EAX), a 16-bit register (AX), or as either of two 8-bit registers (AH
and AL). Note that if an 8- or 16-bit register is addressed, only that
portion of the 32-bit register changes without affecting the remaining
bits. The accumulator is used for instructions such as multiplication,
division, and some of the adjustment instructions. For these
instructions, the accumulator has a special purpose, but is generally
considered to be a multipurpose register. In the 80386 and above, the
EAX register may also hold the offset address of a location in the
memory system. In the 64-bit Pentium 4 and Core2, RAX holds a 64-
bit offset address, which allows 1T (terra) byte of memory to be
accessed through a 40-bit address bus. In the future, Intel plans to
expand the address bus to 52 bits to address 4P (peta) bytes of memory.
RBX RBX is addressable as RBX, EBX, BX, BH, or BL. The BX register
(base index) sometimes holds the offset address of a location in the memory
system in all versions of the microprocessor. In the 80386 and
above, EBX also can address memory data. In the 64-bit Pentium 4
and Core2, RBX can also address memory data.
RCX RCX, which is addressable as RCX, ECX, CX, CH, or CL, is a
(count) general-purpose register that also holds the count for various
instructions. In the 80386 and above, the ECX register also can hold
the offset address of memory data. In the 64-bit Pentium 4, RCX can
also address memory data. Instructions that use a count are the
repeated string instructions (REP/REPE/REPNE); and shift, rotate,
and LOOP/LOOPD instructions. The shift and rotate instructions use
CL as the count, the repeated string instructions use CX, and the
LOOP/LOOPD instructions use either CX or ECX. If operated in the
64-bit mode, LOOP uses the 64-bit RCX register for the loop counter.
RDX RDX, which is addressable as RDX, EDX, DX, DH, or DL, is a
(data) general-purpose register that holds a part of the result from a
multiplication or part of the dividend before a division. In the 80386
and above, this register can also address memory data.
RBP RBP, which is addressable as RBP, EBP, or BP, points to a memory
(base pointer) location in all versions of the microprocessor for memory data transfers.
RDI RDI, which is addressable as RDI, EDI, or DI, often addresses
(destination index) string destination data for the string instructions.
RSI RSI is used as RSI, ESI, or SI. The source index register often
(source index) addresses source string data for the string instructions. Like RDI,
RSI also functions as a general-purpose register. As a 16-bit
register, it is addressed as SI; as a 32-bit register, it is addressed as
ESI; and as a 64-bit register, it is addressed as RSI.
R8 through R15 These registers are only found in the Pentium 4 and Core2 if 64-bit
extensions are enabled. As mentioned, data in these registers are
addressed as 64-, 32-, 16-, or 8-bit sizes and are of general purpose.
Most applications will not use these registers until 64-bit processors
are common. Please note that the 8-bit portion is the rightmost 8-bit
only; bits 8 to 15 are not directly addressable as a byte.
FIGURE 2–2 The EFLAG 31 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 4 2 0

and FLAG register counts for I V V AV R N I I O DI T S Z A P C

T O O
DI I C M F
the entire 8086 and Pentium P F
P P

microprocessor family. 1 0 8
0
8
6
/
8
0
8
8
/
8
0
Special-Purpose Registers. The special-purpose registers include RIP, RSP, and RFLAGS;
1
and the segment registers include CS, DS, ES, SS, FS, and GS. 8
6
/
RIP RIP addresses the next instruction in a section of memory defined as
8
0
(instruction pointer) a code segment. This register is IP (16 bits) when the microprocessor
1
operates in the real mode and EIP (32 bits) when the 80386 and
8
8
above operate in the protected8 mode. Note that the 8086, 8088, and
80286 do not contain an EIP register
0
2
and only the 80286 and above
operate in the protected mode.8 The instruction pointer, which points
6
to the next instruction in a program, is used by the microprocessor to
8
find the next sequential instruction
0 in a program located within the
3
code segment. The instruction8 pointer can be modified with a jump
6
or a call instruction. In the 64-bit
/ mode, RIP contains a 40-bit
address at present to address a89 1T flat address space.
8
RSP RSP addresses an area of memory 6 called the stack. The stack memory
D
(stack pointer) stores data through this pointerXand is explained later in the text with
the instructions that address stack
8 data. This register is referred to as
0
SP if used as a 16-bit register and
4 ESP if referred to as a 32-bit register.
8
RFLAGS RFLAGS indicate the condition 6 of the microprocessor and control
S
its operation. Figure 2–2 showsX the flag registers of all versions of the
microprocessor. (Note the flagsP are upward-compatible from the
e
8086/8088 through the Core2 microprocessors.)
n The 8086–80286
t
contain a FLAG register (16 bits)i and the 80386 and above contain an
u
EFLAG register (32-bit extended m flag register). The 64-bit RFLAGS
/
contain the EFLAG register, whichP
is unchanged in the 64-bit version.
e
The rightmost five flag bits and the overflow flag change n after many arithmetic and logic
t
instructions execute. The flags never change for any datai transfer or program control operation.
u
Some of the flags are also used to control features found in them microprocessor. Following is a list of
each flag bit, with a brief description of their function. As instructions
4
are introduced in subsequent
chapters, additional detail on the flag bits is provided. The rightmost five flags and the overflow flag
are changed by most arithmetic and logic operations, although data transfers do not affect them.
C (carry) Carry holds the carry after addition or the borrow after subtraction. The
carry flag also indicates error conditions, as dictated by some programs
and procedures. This is especially true of the DOS function calls.
P (parity) Parity is a logic 0 for odd parity and a logic 1 for even parity. Parity is
the count of ones in a number expressed as even or odd. For example,
if a number contains three binary one bits, it has odd parity. If a
number contains no one bits, it has even parity. The parity flag finds
little application in modern programming and was implemented in
early Intel microprocessors for checking data in data communications
environments. Today parity checking is often accomplished by the
data communications equipment instead of the microprocessor.
A (auxiliary carry) The auxiliary carry holds the carry (half-carry) after addition or the
borrow after subtraction between bit positions 3 and 4 of the result.
This highly specialized flag bit is tested by the DAA and DAS
instructions to adjust the value of AL after a BCD addition or
subtraction. Otherwise, the A flag bit is not used by the
microprocessor or any other instructions.
Z (zero) The zero flag shows that the result of an arithmetic or logic operation is
zero. If Z = 1, the result is zero; if Z = 0, the result is not zero. This
may be confusing, but that is how Intel decided to name this flag.
S (sign) The sign flag holds the arithmetic sign of the result after an arithmetic
or logic instruction executes. If S = 1, the sign bit (leftmost bit of a
number) is set or negative; if S = 0, the sign bit is cleared or positive.
T (trap) The trap flag enables trapping through an on-chip debugging
feature. (A program is debugged to find an error or bug.) If the T
flag is enabled (1), the microprocessor interrupts the flow of the
program on conditions as indicated by the debug registers and
control registers. If the T flag is a logic 0, the trapping (debugging)
feature is disabled. The Visual C++ debugging tool uses the trap
feature and debug registers to debug faulty software.
I (interrupt) The interrupt flag controls the operation of the INTR (interrupt
request) input pin. If I = 1, the INTR pin is enabled; if I = 0, the
INTR pin is disabled. The state of the I flag bit is controlled by the
STI (set I flag) and CLI (clear I flag) instructions.
D (direction) The direction flag selects either the increment or decrement mode
for the DI and/or SI registers during string instructions. If D = 1,
the registers are automatically decremented; if D = 0, the registers
are automatically incremented. The D flag is set with the STD (set
direction) and cleared with the CLD (clear direction) instructions.
O (overflow) Overflows occur when signed numbers are added or subtracted. An
overflow indicates that the result has exceeded the capacity of the
machine. For example, if 7FH ( + 127) is added—using an 8-bit
addition—to 01H ( + 1), the result is 80H (–128). This result represents
an overflow condition indicated by the overflow flag for signed
addition. For unsigned operations, the overflow flag is ignored.
IOPL IOPL is used in protected mode operation to select the privilege
(I/O privilege level) level for I/O devices. If the current privilege level is higher or more
trusted than the IOPL, I/O executes without hindrance. If the IOPL
is lower than the current privilege level, an interrupt occurs, causing
execution to suspend. Note that an IOPL of 00 is the highest or most
trusted and an IOPL of 11 is the lowest or least trusted.
NT (nested task) The nested task flag indicates that the current task is nested within
another task in protected mode operation. This flag is set when the
task is nested by software.
RF (resume) The resume flag is used with debugging to control the resumption of
execution after the next instruction.
VM (virtual mode) The VM flag bit selects virtual mode operation in a protected mode
system. A virtual mode system allows multiple DOS memory
partitions that are 1M byte in length to coexist in the memory
 system. Essentially, this allows the system program to execute
multiple DOS programs. VM is used to simulate DOS in the
modern Windows environment.
AC The alignment check flag bit activates if a word or doubleword is
(alignment check) addressed on a non-word or non-doubleword boundary. Only the
80486SX microprocessor contains the alignment check bit that is
primarily used by its companion numeric coprocessor, the
80487SX, for synchronization.
VIF The VIF is a copy of the interrupt flag bit available to the Pentium–
(virtual interrupt) Pentium 4 microprocessors.
VIP (virtual VIP provides information about a virtual mode interrupt for the
interrupt pending) Pentium–Pentium 4 microprocessors. This is used in multitasking
environments to provide the operating system with virtual interrupt
flags and interrupt pending information.
ID (identification) The ID flag indicates that the Pentium–Pentium 4 microprocessors
support the CPUID instruction. The CPUID instruction provides the
system with information about the Pentium microprocessor, such as
its version number and manufacturer.

Segment Registers. Additional registers, called segment registers, generate memory

addresses when combined with other registers in the microprocessor. There are either
four or six segment registers in various versions of the microprocessor. A segment register func-
tions differently in the real mode when compared to the protected mode operation of the micro-
processor. Details on their function in real and protected mode are provided later in this chapter.
In the 64-bit flat model, segment registers have little use in a program except for the code seg-
ment register. Following is a list of each segment register, along with its function in the system:

CS (code) The code segment is a section of memory that holds the code
(programs and procedures) used by the microprocessor. The code
segment register defines the starting address of the section of memory
holding code. In real mode operation, it defines the start of a 64K-
byte section of memory; in protected mode, it selects a descriptor that
describes the starting address and length of a section of memory
holding code. The code segment is limited to 64K bytes in the
8088–80286, and 4G bytes in the 80386 and above when these
microprocessors operate in the protected mode. In the 64-bit mode,
the code segment register is still used in the flat model, but its use
differs from other programming modes as explained in Section 2-5.
DS (data) The data segment is a section of memory that contains most data used
by a program. Data are accessed in the data segment by an offset
address or the contents of other registers that hold the offset address.
As with the code segment and other segments, the length is limited to
64K bytes in the 8086–80286, and 4G bytes in the 80386 and above.
ES (extra) The extra segment is an additional data segment that is used by
some of the string instructions to hold destination data.
SS (stack) The stack segment defines the area of memory used for the stack.
The stack entry point is determined by the stack segment and stack
pointer registers. The BP register also addresses data within the
stack segment.
FS and GS The FS and GS segments are supplemental segment registers available
in the 80386–Core2 microprocessors to allow two additional memory
segments for access by programs. Windows uses these segments for
internal operations, but no definition of their usage is available.