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Verification

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Manisha Gupta
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4 views

Verification

verilog notes

Uploaded by

Manisha Gupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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NUM_VEX_ROWS:

One vex array with 40 vex cores (8 x 5);

What is CRUX?

What is ganging at input and ganging at output?

What is APB and AXI Protocols?

Binary to gray and gray to binary converter

APB Interface:

- printer, keyboard, IO devices, timer : low performance devices or peripherals / required less
memory
- a low-cost interface, low power consumption and reduced interface complexity
- The APB interface is not pipelined and is a simple, synchronous protocol.
- Every transfer takes at least two cycles to complete.
- designed for accessing the programmable control registers of peripheral devices.
- APB peripherals are typically connected to the main memory system using an APB bridge.

For example, a bridge from AHB to APB could be used to connect a number of APB peripherals to
an AXI memory system.
 APB transfers are initiated by an APB bridge. APB bridges can also be referred to as a Requester.
A peripheral interface responds to requests. APB peripherals can also be referred to as a
Completer. This specification will use Requester and Completer.
- In APB, signals are starting with letter “p”. (Total: 17 signals  clock, system bus reset, Requester
: 10, Completer: 5)

- During a transfer three phases are there: Idle phase, setup phase and access phase
Transfer:
WRITE:
No wait start

1) Idle phase

- PSEL=0
- PADDR=0
- PWRITE=0
- PWDATA=0

2) Setup phase

- PSEL=1(asserted)
- PADDR=1
- PWRITE=1

3)Access phase

- PSEL=1
- PENABLE=1
- PADDR=1
- PWDATA=1
- PWRITE=1

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