Faculty of Computers and Artificial Intelligence

CS222: Computer Architecture

Finite State Machines (FSMs)

Synchronous sequential circuits can be drawn in the forms shown in Figure 3.22. These forms
are called finite state machines (FSMs). A FSM has M inputs, N outputs, and k bits of state. It
also receives a clock and, optionally, a reset signal.
A FSM consists of two blocks of combinational logic, next state logic and output logic, and a
register that stores the state. On each clock edge, the FSM advances to the next state, which was
computed based on the current state and inputs.
There are two general classes of finite state machines, characterized by their functional
specifications. In Moore machines, the outputs depend only on the current state of the machine.
In Mealy machines, the outputs depend on both the current state and the current inputs.
Finite state machines provide a systematic way to design synchronous sequential circuits given
a functional specification.

Figure 3.22 Finite state machines: (a) Moore machine, (b) Mealy machine

One important decision in state encoding is the choice between binary encoding and one-hot
encoding. With binary encoding, each state is represented as a binary number.
In one-hot encoding, a separate bit of state is used for each state. It is called one-hot because
only one bit is “hot” or TRUE at any time. For example, a one-hot encoded FSM with three
states would have state encodings of 001, 010, and 100. Each bit of state is stored in a flip-flop,
so one-hot encoding requires more flip-flops than binary encoding. However, with one-hot
encoding, the next-state and output logic is often simpler, so fewer gates are required.

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Example 3.7 Layla owns a robotic snail with a FSM brain. The snail crawls from left to right
along a paper tape containing a sequence of 1’s and 0’s. On each clock cycle, the snail crawls to
the next bit. The snail smiles when the last two bits that it has crawled over are 01.
Design the FSM to compute when the snail should smile. Compare Moore and Mealy state
machine designs.
Solution
State Transition Diagram: Moore Machine

Binary State Encoding

State Encoding
S0 00
S1 01
S2 10
- 11

State Transition Table

Current State Inputs Next State
S1 S0 A S’1 S’0
0 0 0 0 1
0 0 1 0 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 X X X

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Next State Equations

The corresponding next state and output for the non-existent state are don’t cares. We use the
don’t cares to minimize our equations.
A A
S1S0
0 1 S1S0
0 1
00 00 1
01 1 01 1
11 X X 11 X X
10 10 1

S1' = S 0 A S 0' = A

Output Table and Equations

Current State Output
S1 S0 Y
0 0 0
0 1 0
1 0 1
1 1 X

S0
S1
0 1
0
1 1 X
Y = S1

FSM Schematic

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CS222: Computer Architecture

State Transition Diagram: Mealy Machine

Binary State Encoding

State Encoding
S0 0
S1 1

State Transition and Output Table

Current State Inputs Next State Output
S0 A S’0 Y
0 0 1 0
0 1 0 0
1 0 1 0
1 0 0 1

Next State and Output Equations

A A
S0
0 1 S0
0 1
0 1 0
1 1 1 1

S 0' = A Y = S0 A

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

FSM Schematic

In Example 3.7, the Moore machine requires three states. In comparison, the Mealy machine
requires only two states. An easy way to remember the difference between the two types of finite
state machines is that a Moore machine typically has more states than a Mealy machine for a
given problem.

FSM Review
Finite state machines are a powerful way to systematically design sequential circuits from a
written specification.
Use the following procedure to design an FSM:
1. Identify the inputs and outputs.
2. Sketch a state transition diagram.
3. For a Moore machine:
a. Write a state transition table.
b. Write an output table.
4. For a Mealy machine:
a. Write a combined state transition and output table.
5. Select state encodings—your selection affects the hardware design.
6. Write Boolean equations for the next state and output logic.
7. Sketch the circuit schematic.

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Exercise 3.22 Describe in words what the state machine in Figure 3.69 does. Using binary state
encodings, complete a state transition table and output table for the FSM. Write Boolean
equations for the next state and output and sketch a schematic of the FSM.

Solution
The finite state machine asserts the output Q for one clock cycle if A is TRUE followed by B
being TRUE.

Binary State Encoding

State Encoding
S0 00
S1 01
S2 10
- 11

State Transition Table

Current State Inputs Next State
S1 S0 A B S’1 S’0
0 0 1 X 0 1
0 0 0 X 0 0
0 1 X 1 1 0
0 1 X 0 0 0
1 0 X X 0 0
1 1 X X X X

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Next State Equations

AB AB
S1S0
00 01 11 10 S1S0
00 01 11 10
00 00 1 1
01 1 1 01
11 X X X X 11 X X X X
10 10

S1' = S 0 B S0' = S1 S0 A

Output Table and Output Equations

Current State Output
S1 S0 Y
0 0 0
0 1 0
1 0 1
1 1 X

S0
S1
0 1
0
1 1 X
Q = S1

FSM Schematic

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Exercise 3.23 Describe in words what the state machine in Figure 3.70 does. Using binary state
encodings, complete a state transition table and output table for the FSM. Write Boolean
equations for the next state and output and sketch a schematic of the FSM.

Solution
The finite state machine asserts the output Q if A is TRUE, followed by B being TRUE, followed
by AB being TRUE at least one time.
Binary State Encoding
State Encoding
S0 00
S1 01
S2 10
- 11

State Transition and Output Table

Current State Inputs Next State Output
S1 S0 A B S’1 S’0 Q
0 0 0 X 0 0 0
0 0 1 X 0 1 0
0 1 X 0 0 0 0
0 1 X 1 1 0 0
1 0 1 1 1 0 1
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 0 0
1 1 X X X X X

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Next State and Output Equations

AB AB
S1S0
00 01 11 10 S1S0
00 01 11 10
00 00 1 1
01 1 1 01
11 X X X X 11 X X X X
10 1 10

S1' = S0 B + S1 AB S0' = S1 S0 A
AB
S1S0
00 01 11 10
00
01
11 X X X X
10 1
Q = S1 AB

FSM Schematic
S1' = S0 B + S1 AB

S0' = S1 S0 A

Q = S1 AB

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Exercise 3.25 Layla’s snail from Section 3.4.3 has a daughter with a Mealy machine FSM brain.
The daughter snail smiles whenever she slides over the pattern 1101 or the pattern 1110.
Sketch the state transition diagram for this happy snail using as few states as possible. Choose
state encodings and write a combined state transition and output table using your encodings.
Write the next state and output equations and sketch your FSM schematic.
Solution

State Transition Diagram

State Encoding
State Encoding
S0 000
S1 001
S2 010
S3 011
S4 100
- 101
- 110
- 111

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CS222: Computer Architecture

State Transition and Output Table

Current State Inputs Next State Output
S2 S1 S0 A S’2 S’1 S’0 Q
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0
0 0 1 1 0 1 0 0
0 1 0 0 0 1 1 0
0 1 0 1 1 0 0 0
0 1 1 0 0 0 0 0
0 1 1 1 0 0 1 1
1 0 0 0 0 1 1 1
1 0 0 1 1 0 0 0
1 0 1 X X X X X
1 1 0 X X X X X
1 1 1 X X X X X

Next State and Output Equations

S0A S0A
S2S1
00 01 11 10 S2S1
00 01 11 10
00 00 1
01 1 01 1
11 X X X X 11 X X X X
10 1 X X 10 1 X X

S 2' = S 2 A + S1 S0 A S1' = S1 S0 A + S1S0 A + S 2 A

S0A S0A
S2S1
00 01 11 10 S2S1
00 01 11 10
00 1 00
01 1 1 01 1
11 X X X X 11 X X X X
10 1 X X 10 1 X X

S0' = S1 S0 A + S1S0 A + S 2 A + S 2 S1 S 0 A Q = S2 A + S1S0 A

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CS222: Computer Architecture

FSM Schematic

S 2' = S 2 A + S1 S0 A

S1' = S1 S0 A + S1S0 A + S 2 A

S0' = S1 S0 A + S1S0 A + S 2 A + S 2 S1 S 0 A

Q = S2 A + S1S0 A

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