UEI509: Digital Systems

Sequential Circuits, Systems, Logic.

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I Output of combinational circuits depends only and immediately on their inputs, they
have no memory.
I Sequential circuits, however, act as storage elements and have memory.
I The outputs in a sequential circuit are a function not only of the inputs, but also of the
present state of the storage elements.
I The next state of the storage elements is also a function of external inputs and the
present state.
I A sequential circuit is specified by a time sequence of inputs, outputs, and internal states.

Fig. 1: Block diagram of sequential circuit.

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I A synchronous sequential circuit is a system whose behaviour can be defined from the
knowledge of its signals at discrete instants of time.
I The behaviour of an asynchronous sequential circuit depends upon the input signals at
any instant of time and the order in which the inputs change.
I The storage elements commonly used in asynchronous sequential circuits are time-delay
devices.
I Synchronous sequential circuits are highly stable, whereas, asynchronous sequential
circuits may become unstable due to feedback and delay.
I Synchronization is achieved by a timing device called a clock generator.
I The clock pulses determine when computational activity will occur within the circuit, and
other signals determine what changes will take place.
I The storage elements (memory) used in clocked sequential circuits are called flip-flops.
I A flip-flop is a binary storage device capable of storing one bit of information.
I The value stored in the flip-flop is updated at the transition of clock pulses and depends
on the input.
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 Fig. 2: Block diagram of sequential circuit.

I Prior to the occurrence of the clock pulse, the combinational logic forming the next value
of the flip-flop must have reached a stable value.
I The speed at which the combinational logic circuits operate is critical.
I The combinational logic must respond to a change in the state of the flip-flop in time to
be updated before the next pulse arrives.
I Propagation delays play an important role in determining the minimum interval between
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clock pulses.
I A latch is a type of bistable logic device or multivibrator.
I An active-HIGH input S-R (SET-RESET) latch is formed with two cross-coupled NOR
gates.
I An active-LOW input S-R latch is formed with two cross-coupled NAND gates.
I An invalid condition in the operation of an active-HIGH input S-R latch occurs when
HIGHs are applied to both S and R at the same time.
I An invalid condition in the operation of an active-LOW input S-R latch occurs when
LOWs are applied to both S and R at the same time.
I In normal operation, the outputs of a latch are always complements of each other.
I In comparing the NAND with the NOR latch as shown in Figs. 3 and 4, note that the
input signals for the NAND require the complement of those values used for the NOR
latch.
I NAND gate latch is sometimes referred to as an S̄-R̄ latch.
I The action of resetting a latch or a flip-flop is also called clearing, and both terms are
used interchangeably in the digital field.
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 Fig. 3: NOR gate SET-RESET (S-R) latches.

Fig. 4: NAND gate of SET-RESET (S-R) latches.

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I The operation of the basic SR latch can be modified by providing an additional enable
input, giving rise to gated SR latch.
I The outputs of the NAND gates stay at the logic-1 level as long as the enable signal
remains at 0.

Fig. 5: S-R latch with control input.

I One way to eliminate the undesirable condition of the indeterminate state in the SR latch
is to ensure that inputs S and R are never equal to 1 at the same time.
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I This is done in the D latch, as shown in Fig. 5 which is gated.
I As long as the enable input is at 0, the cross-coupled SR latch has both inputs at the 1
level and the circuit cannot change state.
I When En = 1 and D = 1, the Q output goes to 1, placing the circuit in the set state.
I When En = 1 and D = 0, output Q goes to 0, placing the circuit in the reset state.
I It holds data in its internal storage and is suited for use as a temporary storage for binary
information.

Fig. 6: D latch.
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 Fig. 7: Symbols for latches.

I Various symbols used to represent latched are shown in Fig. 7.

I A good example of an application of an S̄-R̄ latch is in the elimination of mechanical
switch contact “bounce.”
I When the pole of a switch strikes the contact upon switch closure, it physically vibrates
or bounces several times before finally making a solid contact.
I Although these bounces are very short in duration, they produce voltage spikes that are
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often not acceptable in a digital system.
 Fig. 8: Contact debouncing circuit.

I A contact debouncing circuit shown in Fig. 8 has two inputs via VCC through pull-up
resistors and a ground connection from the mechanical switch.
I The input has two combinations 10 or 01 at the input terminals.
I From the truth table of Fig. 4, it can be easily understood that the circuit operates as
switch and eliminates the intermediate “bouncing.”
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I Flip-flops are synchronous bistable devices, also known as bistable multivibrators.
I Synchronous means that the output changes state only at a specified point (leading or
trailing edge) on the triggering input called the clock (CLK).
I Flip-flops are edge-triggered or edge-sensitive whereas gated latches are level-sensitive.
I An edge-triggered flip-flop changes state and is sensitive to its inputs only either at the
positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse.
I The graphical representation of both rising and falling edge trigger for two types of
flip-flops is shown in Fig. 9
I Clocked S-R flip-flop with its responses for both positive and negative edge triggers are
shown in Figs. 10 to 12.
I Implementation of edge detectors is shown in Fig. 13.

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Fig. 9: Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative
edge-triggered).
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 (a) S-R flip-flop and function table (b) Typical waveforms.

Fig. 10: Positive edge-triggered S-R flip-flop.

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 Fig. 11: Clocked S-R flip-flop that triggers only on negative-going transitions.

Fig. 12: Simplified version of the internal circuitry for an edge-triggered S-R flip-flop.
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Fig. 13: Implementation of edge-detector circuits used in edge-triggered flip-flops: (a) Positive; (b)
Negative. The duration of the CLK∗ pulses is typically 2-5 ns.

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I J-K flip-flop is similar to the S-R flip-flop, except that J = K = 1 condition does not
result in an ambiguous output.
I When J and K are both 1, the FF will always go to its opposite state upon the positive
transition of the clock signal, called as toggle mode of operation.

Fig. 14: Internal circuit of the edge-triggered J-K flip-flop.

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 (a) J-K flip-flop and function table (b) Typical waveforms.

Fig. 15: Positive edge-triggered J-K flip-flop.

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I A D flip-flop can be implemented using J-K flip-flop and an inverter gate as shown in
Fig. 16.

Fig. 16: Edge-triggered D flip-flop implementation from a J-K flip-flop.

I A similar implementation is shown in Fig. 6 using an S-R flip-flop.

I A J-K flip-flop can be implemented using D flip-flop and a combinational circuit as shown
in Fig. 17.

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I A J-K flip-flop has three operations: set, reset, compliment.
D = JQ0 + K 0 Q
I When J = 1 and K = 0, D = Q0 + Q = 1, so the next clock edge sets the output to 1.
I When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
I When both J = K = 1 and D = Q0 , the next clock edge complements the output.
I When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

Fig. 17: J-K flip-flop using a D flip-flop.

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I The T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK
flip-flop when inputs J and K are tied together.
I When T = 0 (J = K = 0), a clock edge does not change the output.
I When T = 1 (J = K = 1), a clock edge complements the output.
I The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gate.
I The expression for the D input is
D = T ⊕ Q = T Q0 + T 0 Q

Fig. 18: T flip-flop using JK and D flip-flop.

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I When T = 0, D = Q and there is no change in the output.
I When T = 1, D = Q0 and the output complements.
I The logical properties of a flip-flop, can be expressed algebraically with a characteristic
equation.

Fig. 19: Characteristic tables.

I For a D flip-flop

Q(t + 1) = D

I For a T flip-flop

Q(t + 1) = T ⊕ Q = T Q0 + T 0 Q
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 Fig. 20: Characteristic table.

I For a JK flip-flop

Q(t + 1) = JQ0 + K 0 Q

I Some flip-flops have asynchronous inputs that are used to force the flip-flop to a
particular state independently of the clock.
I The input that sets the flip-flop to 1 is called preset or direct set.
I The input that clears the flip-flop to 0 is called clear or direct reset.
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 Fig. 21: D flip-flop using 3 SR flip-flops with asynchronous reset.

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I A logic symbol for a D flip-flop with preset and clear inputs is shown in Fig. 22.
I These inputs are active-LOW, as indicated by the bubbles.
I These preset and clear inputs must both be kept HIGH for synchronous operation.
I In normal operation, preset and clear would not be LOW at the same time.

(a) Logic diagram. (b) Logic symbol.

Fig. 22: D flip-flop with active-LOW preset and clear inputs.

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 Fig. 23: D flip-flop with asynchronous preset and clear operation.
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I A common requirement in digital systems is to store several bits of data from parallel
lines simultaneously in a group of flip-flops, as shown in Fig. 24.
I Each of the four parallel data lines is connected to the D input of a flip-flop.
I The clock inputs of the flip-flops are connected together, so that each flip-flop is triggered
by the same clock pulse.
I The asynchronous reset(R) inputs are connected to a common CLR line, which initially
resets all the flip-flops.
I This group of four flip-flops is an example of a basic register used for data storage.
I In digital systems, data are normally stored in groups of bits.
I Another application of a flip-flop is dividing (reducing) the frequency of a periodic
waveform, with master-slave configuration.
I When a pulse waveform is applied to the clock input of a D or J-K flip-flop that is
connected to toggle (D = Q or J = K = 1), the Q output is a square wave with one-half
the frequency of the clock input, as shown in Fig. 25a.
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KarteekFig. 24: Basic register for parallel data storage using D flip-flops.
I Further division of a clock frequency can be achieved by using the output of one flip-flop
as the clock input to a second flip-flop, as shown in Fig. 25b.
I The frequency of the QA output is divided by 2 by flip-flop B.
I The QB output is, therefore, one-fourth the frequency of the original clock input.
I By connecting flip-flops in this way, a frequency division of 2n is achieved, where n is the
number of flip-flops.

(a) Single stage. (b) Multi-stage.

Fig. 25: Frequency division.

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I Another important application of flip-flops is in digital counters as shown in Fig. 26.
I Negative edge-triggered J-K flip-flops are used and are initially RESET.
I The flip-flops are counting in sequence from 0 to 3 (00, 01, 10, 11) and then recycling
back to 0 to begin the sequence again.

Karteek Fig. 26: J-K flip-flops used to generate a binary count sequence.
I A register is a digital circuit with two basic functions: data storage and data movement.
I A D flip-flop is generally used to store single bit information.
I Various classifications of registers:
1. Parallel in/parallel out (PIPO)
2. Serial in/serial out (SISO)
3. Parallel in/serial out (PISO)
4. Serial in/parallel out (SIPO)
I Serial data flow through a register is generally called shifting, and the data may be shifted
either to the left or to the right.
I If the serial output data is fed back into the serial input of the same register, the
operation is called a data rotate.
I Parallel inputting of data is often described as a register load.
I A PIPO can be implemented using 74ALS174/74HC174 IC as shown in Fig. 29.
I The same IC can also be used for SISO operation as shown in Fig. 30.

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Fig. 27: Data transfer circuits: (a) PIPO; (b) SISO; (c) PISO; (d) SIPO.
 Fig. 28: Basic data movement in shift registers.

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 Fig. 29: Parallel in parallel out using 74ALS174.
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I A serial in/serial out shift register will have data loaded into it one bit at a time.
I The data will move one bit at a time with each clock pulse through the set of flip-flops
toward the other end of the register.
I The logic diagram and schematic symbol for the 74HC166 is shown in Fig. 31 and an
example timing diagram is shown in Fig. 32

Karteek Fig. 30: Serial in serial out using 74ALS174.

Karteek Fig. 31: Serial in serial out using 74HC166.
 Fig. 32: Serial in serial out example using 74HC166.
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I A bidirectional shift register is one in which the data can be shifted either left or right as
shown in Fig. 33.

Fig. 33: Four-bit bidirectional shift register.

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I A shift register counter is basically a shift register with the serial output connected
back to the serial input to produce special sequences.
I Two of the most common types of shift register counters, the Johnson counter and the
ring counter.
I In a Johnson counter the complement of the output of the last flip-flop is connected back
to the D input of the first flip-flop.
I In general, a Johnson counter will produce a modulus of 2n, where n is the number of
stages in the counter.

Fig. 34: Four-bit Johnson sequence.

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 Fig. 35: Four-bit Johnson counter.

Karteek Fig. 36: Ten-bit Ring counter.

I A ring counter utilizes one flip-flop (FF) for each state in its sequence.
I A logic diagram for a 10-bit ring counter is shown in Fig. 35.
I Initially, a 1 is preset into the first FF, and the rest of the FFs are cleared.
I The interstage connections are the same as those for a Johnson counter, except that Q
rather than Q is fed back from the last stage.

Fig. 37: Ten-bit Ring sequence.

I A serial in/serial out shift register can be used to provide a time delay td from input to
output that is a function of both the number of stages (n) in the register and the clock
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frequency f , td = n/f .
I A cascade of JK FFs are used to implement asynchronous (ripple) counters.
I J = K = 1 is applied to all the FFs, output Q of one stage is applied as clock to the next
stage.
I For the circuit in Fig. 38, binary counting sequence from 0000 to 1111 is followed as clock
pulses are continuously applied.

Karteek Fig. 38: Four-bit asynchronous (ripple) counter.

I The nomenclature ‘asynchronous’ comes from the fact that FFs don’t change states in
exact synchronism with the applied clock pulses.
I This type of counter is also often referred to as a ripple counter because of the way the
FFs respond one after another in a kind of rippling effect.
I The counter in Fig. 38 has 16 distinctly different states (0000 through 1111). Thus, it is a
MOD-16 ripple counter.
I For n FFs in the circuit, Mod number = 2n .
I Because of the inherent propagation delay time (tpd) of each FF, the second FF will not
respond until a time tpd after the first FF receives an active clock transition; the third FF
will not respond until a time equal to 2 × tpd after that clock transition; and so on.
I The propagation delays of the FFs accumulate so that the Nth FF cannot change states
until a time equal to N × tpd after the clock transition occurs.
I Assume that the tpd = 50 ns for each FF, Fig. 39 shows the outcome for two clock periods
T = 1000 ns and T = 100 ns.
I High frequency can cause a missed state, as evident for the case of T = 100 ns.
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 Fig. 39: Propagation delay in ripple counter with tpd = 50 ns for each FF.

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I Problems such as this can be avoided if the period between input pulses is made longer
than the total propagation delay of the counter.
I For proper counter operation with N FFs,

Tclock ≥ N × tpd

I The maximum frequency that can be used is given by,

1
fmax =
N × tpd
I As the number of FFs in the counter increases, the total propagation delay increases and
fmax decreases.
I Asynchronous counters are not useful at very high frequencies, especially for counters
with large numbers of bits.
I Another issue is erroneous count patterns that can generate glitches.

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I For example, in Fig. 39, right after state 011, state 010 occurs before 100 for a small
duration of 50 ns.
I Digital circuits will be fast enough to detect it.
I Suppose that a four-bit ripple counter is constructed using the 74LS112 JK flip-flop that
has tP LH = 16 ns and tP HL = 24 ns as the propagation delays from CLK to Q.
I To calculate fmax , assume the “worst case”, tpd = tP HL = 24 ns, so that

1
fmax = = 10.4 MHz
4 × 24 × 10−9
I If there are 6 FFs,

1
fmax = = 6.9 MHz
6 × 24 × 10−9
I Asynchronous counters are not useful at very high frequencies, especially for counters
with large numbers of bits.
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I A synchronous counter is one in which all the flip-flops in the counter are clocked at the
same time by a common clock pulse.
I J-K flip-flops are used to illustrate most synchronous counters.
I D flip-flops can also be used but generally require more logic because of having no direct
toggle or no-change states.
I Fig. 40 shows a 2-bit synchronous binary counter.

Fig. 40: 2-bit synchronous binary counters.

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 Fig. 41: 2-bit synchronous binary sequence timing for JK FFs.

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 (a) (b)

Fig. 42: 3-bit synchronous binary counter and sequence timing.

Karteek Fig. 43: 3-bit synchronous binary sequence for JK FFs.

Karteek Fig. 44: 4-bit synchronous binary sequence timing for JK FFs.
I In certain applications, the sequence need to be truncated and recycled. For example, a
BCD decade counter.
I It exhibits a truncated binary sequence and goes from 0000 through the 1001 state.
I Rather than going from the 1001 state to the 1010 state, it recycles to the 0000 state.

Fig. 45: BCD decade counter sequence.

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I Observe that FF0 (Q0 ) toggles on each clock pulse.

J0 = K0 = 1

I FF1 (Q1 ) changes on the next clock pulse each time Q0 = 1 and Q3 = 0.

J1 = K1 = Q0 Q3

I FF2 (Q2 ) changes on the next clock pulse each time both Q0 = 1 and Q1 = 1.

J2 = K2 = Q0 Q1

I Finally, FF3 (Q3 ) changes to the opposite state on the next clock pulse each time Q0 = 1,
Q1 = 1, and Q2 = 1 (state 7), or when Q0 = 1 and Q3 = 1 (state 9).

J3 = K3 = Q0 Q1 Q2 + Q0 Q3

I Circuit and timing diagrams are shown in Figs. 46 and 47

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 Fig. 46: A synchronous BCD decade counter.

Fig. 47: Timing diagram for the BCD decade counter.

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I An alternative way of implementing the counters with M OD < 2N is by using CLEAR
input with appropriate combinational logic.

Fig. 48: MOD-6 counter using clear on MOD-8 counter.

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I If we assume a starting count of 000, the diagram shows that the states of the counter
change normally up until the count of 101.
I When the next clock pulse occurs, the counter temporarily goes to the 110 count before
going to the stable 000 count.
I Thus, we can essentially say that this counter counts from 000 (zero) to 101 (five) and
then recycles to 000, it is a MOD-6 counter.
I Temporary counter states, like the 110 state for this counter, are called transient states.
I Any desired MOD number can be obtained by changing the inputs to NAND gate.

Karteek Fig. 49: MOD-6 state transition.

I General procedure to construct a counter with MOD number X:
1. Find the smallest number of FFs such that 2N ≥ X, and connect them as a counter. If
2N = X, do not do steps 2 and 3.
2. Connect a NAND gate to the asynchronous CLEAR inputs of all the FFs.
3. Determine which FFs will be in the HIGH state at a count = X; then connect the normal
outputs of these FFs to the NAND gate inputs.
I Fig. 50 shows a MOD-14 counter, use similar logic to redesign BCD decade counter shown
in Fig. 26.

Karteek Fig. 50: MOD-14 counter.

I An up/down or a bidirectional counter is one that is capable of progressing in either
direction through a certain sequence.

Fig. 51: Up/Down sequence for a 3-bit binary counter.

I It can be observed for the sequence in Fig. 51 that,

J0 = K0 = 1
J1 = K1 = Q0 · UP + Q0 · DOWN
J2 = K2 = Q1 · Q0 · UP + Q1 · Q0 · DOWN
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 Fig. 52: Up/Down 3-bit binary counter.

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 Fig. 53: Up/Down 3-bit binary sequence.

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I A state machine is a sequential circuit having a limited number of states occurring in a
prescribed order.
I A counter is an example of a state machine; the number of states is called the modulus.
I Two basic types of state machines are the Moore and the Mealy.
I In Moore state machine, the outputs depend only on the internal present state.
I In Mealy state machine, the outputs depend on both the internal present state and inputs.
I Both types have a timing input (clock) that is not considered a controlling input.
I A simple counter of MOD X is an example of Moore state machine.
I If the value of X is selected based on the input, it becomes Mealy state machine.
I For example, assume that the tablet-bottling system uses three different sizes of bottles: a
25-tablet bottle, a 50-tablet bottle, and a 100-tablet bottle.
I This operation requires a state machine with three terminal counts: 25, 50, and 100.
I The combinational logic sets the modulus of the counter depending on the modulus-select
inputs as shown in Fig. 55.
I The output of the counter depends on both the present state and the modulus-select
inputs.
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 Fig. 54: Two types of sequential logic.

Karteek Fig. 55: Mealy state machine.

 Design of Synchronous Counters:
I It includes the following steps:
1. Develop a state diagram for a given sequence
2. Develop a next-state table for a specified counter sequence
3. Create a flip-flop transition table
4. Use the Karnaugh map method to derive the logic requirements for a synchronous counter
5. Implement a counter to produce a specified sequence of states
I The first step in the design of a state machine (counter) is to create a state diagram.
I A state diagram shows the progression of states through which the counter advances.
I Consider a 3-bit gray code counter, its state diagram is given in Fig. 56

Karteek Fig. 56: 3-bit gray code counter state diagram.

I The second step is to derive a next-state table, as shown in Fig. 57 for the gray counter.
I The third step is to develop transition table for the J-K flip-flops as shown in Table 1
(D flip-flops can also be used).
I All possible output transitions are listed by showing the Q output of the flip-flop going
from present states to next states.
I The next step is to develop the logic using Karnaugh maps as shown in Fig. 58,

Fig. 57: Next state table and transition table.

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 Table 1: State transition table.

Present state Next state J-K inputs

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 x 0 x 1 x
0 0 1 0 1 1 0 x 1 x x 0
0 1 1 0 1 0 0 x x 0 x 1
0 1 0 1 1 0 1 x x 0 0 x
1 1 0 1 1 1 x 0 x 0 1 x
1 1 1 1 0 1 x 0 x 1 x 0
1 0 1 1 0 0 x 0 0 x x 1
1 0 0 0 0 0 x 1 0 x 0 x

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 Fig. 58: Karnaugh maps for present-state J and K inputs.

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I The next step is to obtain the logic expressions from the Karnaugh maps:
J0 = Q2 Q1 + Q2 Q1 = Q2 ⊕ Q1
K0 = Q2 Q1 + Q2 Q1 = Q2 ⊕ Q1
J1 = Q2 Q0
K1 = Q2 Q0
J2 = Q1 Q0
K2 = Q1 Q0
I The final step is to implement:

Karteek Fig. 59: Three-bit Gray code counter.

I Historically, J-K flip-flops have been used to implement counters
I The logic circuits needed for the J and K inputs are usually simpler than the logic circuits
needed to control an equivalent synchronous counter using D flip-flops.
I When designing counters that will be imple mented in PLDs, where abundant gates are
generally available, it makes sense to use D flip-flops instead of J-Ks.
I Designing counter circuits using D flip-flops is even easier than using J-K flip-flops.
I Consider designing MOD-5 binary counter, corresponding excitation table is shown in
Fig. 60

Karteek Fig. 60: MOD-5 counter excitation table using D flip-flops.

 Fig. 61: MOD-5 counter K maps, simplified expressions, and implementation.

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