JOMO KENYATTA UNIVERSITY OF AGRICULTURE AND TECHNOLOGY University Examinations 2015/2016 EEE2406: MICROPROCESSOR I marking scheme QUESTION ONE (@) Define the following: () Bootstrap Loader (i) Instruction cycle (ili) Software [5 marks] Soln: 0) © It is a program used to load the loader program such that application programs can then be loaded to the program memory. It can be loaded manually from a disk by user keying IN its file name using the keyboard. fo. Iraan be in a ROM where it will only require initialization. Gi) ‘Am instruetion cycle is defined as the time duration required to fetch an instruction @O from program memory, decode it and execute it. Gis) Wis all activities associated with successive development and operation of computing system other than the hardware pieces themselves. Hardware does the ea) actual computing. Page 1 of 18w an Intel 8086 ing diagram, explain using all related signals hov i [8 marks] (b) With the aid of a timi executed. microprocessor ‘write instruction’ Is fetched and Soln: ALE Indicates the current data on 8086/8088 address/data bus are address DEN (Data enable) Disconnects data bus connection ahs DT/R (data transmit /Receive) Indicates the direction of data transfer Figure 3: Bus cycle signals MITO Indicates that the processor is assessing whether memory (1O/M=0) or VO devices (IO/M=1) ' RD __ Indicates that the processor is reading from memory or I/O devices | TR _ indicates that the processor is writing to memory or /O devices T1 The processor outputs control signals RD or WRto the bus controller, which in turn activates the address and data buffers. Afterwards the address of the required data is supplied by pins A19-A0 and fetched into the address buffer. The BHE signal indicates whether the whole word or only ne byte is read. Therefore the read process has been started and the READY signal drops to low. The memory controller starts an external read process of the main memory Page? of 182 The 8086 removes the address from the bus and either tri-states or activates the ADI5-ADO lines in preparation for reading data via ADI5-ADO lines during T3. In case of write bus cycle, 8086 GS ff} outputs data on ADIS-ADO. During this eycle, the upper four multiplexed bus lines switch from | A19-A116 to bus status $6-S3 . The RD or i/R signal is maintained active during T2-T4. 13 During 73, the 8086 continues to output status information. The processor will continue to read data or output write data. If the selected memory or I/O device is not fast enough the memory or VO device maintains the READY signal active. The signal forces the processor to insert additional clock cycles (wait state TW) after T3. If transfer is complete, the READY signal is raised to HIGH, Data on ADIS-ADO is latched during last wait state or during T3 if no wait states are requested. 14 The bus eycle is terminated after half clock cycle of T4. The buffers are disabled but the (7 processor continues to output the status signals S7-S3. After T4, the system bus is again at initial state (©) A sixteen bit microprocessor with a 16 bit address bus has the following added signals: READ (RD), WRITE (WR), memory request and Input Output request (M/ IO). (Design a hardware interface scheme of four (4) 4Kbyte of RAM, one (1) IKb of ROM and two (2) nel Programmable Peripheral Interface (PPI) devices. (ii) Tabulate the address-mapping scheme. (ii) Include any suggestions made. (7 marks] Page 3 of 18Soln: a f Microprocessor UAL we. 19 fot mg kB span Dis.p0_| y Y 1s & 4 i) Address Mapping. CHIP AIS-Al2 | AII-A8. AT-A4 A3-A0 Address ROM 0 0000 0 i} 0000H o oor F F 03FFH RAM 1 a 0000 0 0 1000H 1 Ait F F IEFFH RAM2 2 Oo 0 0 2000H F F F 2EFFH RAM3 3 0 0 0 3000H F _F F 3FFFH. RAM4 4 0 0 0 4000 F F F 4PFFH 8255 PPI 5 x x XX00 5000H 1 Xxo1 | 3001H XX10 5002H XX11 5003HL ‘8255 PPI 6 x x XX00 6000H 2 ‘XX01 6001 Xx10 6002H XX11 6003H. Page 4 of 18Suggestions: > + Don’t care states assumed to be zeros / * For linear addressing of the memories, the large memories are Mapped first (RAM) followed by smaller memories (ROM) Question, (@) Soln: An Intel 8255 programmable peripheral interface device is to be configured into mode 0 of its operation. Using a configuration table, obtain the control word and assembler module that would cause the device to operate with Port A as input and Port B as an output, Port C lower as input and Port C upper as an output (4 marks} Generating the Control word Groep A Group B ee controls a A CU % BCL rfofolzfeofojoja Control word = '91H Always 1 when sending control word 3038 Module: MOV DX, 03H; Address of control register MOV AL, 91H; CONTROL WORD ® ; OUT DX, AL, Send control word to programmable pi Ports are then configured. The programmer can then use them as programmed or reprogram them again if need arises. Page 5 of 18& Write a program that inpuls five (5) successive data from an Intel 8255 programmable Peripheral Interface (PPI) of an Intel 8086 based computer, stores the data into memory using Indexed-addressing mode. When character ‘O’ (CAPITAL) is pressed, the same stored data is output to same port and made to rotate left through carry at two (2) seconds interval, otherwise the process is repeated. w@ (i) Soln: (b) Draw a flowchart of the program Write an assembly language program which when compiled will run an Intel 8086 microprocessor system and achieve the objective [Program parameters ; EEE2406Microprocessor I Exam April 2015 ame Input_Output_model include 'emu8086.ine* model small ‘stack 100 data msg db "This is a program for conditional”, Odh, Osh db" outputting of saved data", Odh,Oah, Oah, S* butter_pos. DB? code “annoy ax,@data nov dsax tov esax mmov dxofiet msg mmovah9 © O 2 [16 marks} Page 6 of 18int 214 fast: mov al,90H mov dx,03, out dxaal mov ex, data: roy x,00H in aldx leasi,buffer_pos mov offset si. mov ah} inca Toop dal mov ah,1 int 21h or al,20h ‘emp al" Je fast cli gotoxy $0,50 mov cx,S ‘mov al,80H mov dx,03H out dxal prt lea si, buffer_pos mov dxsi mov ah,2 int 20h mov al,[si] mov dx,00 out dx,al call delay loop prit ip exit delay proc near + mov cx001EH mov dceatod (7) mov ahS6tt int 15H ret delay endp exit: mov ah,4ch | int 21h end main Page 7 of 18Question 3 (@ With the aid of diagram(s), explain how protected mode of microprocessor operations can be achieved stating any merits if any. [7 marks] Soln: Protected mode is designed in a versatile way such that any OS or program can be implemented on the microprocessor. The mode allows multitasking and computation of segmentation and paging. Other features are: Gate operations Protected mode interrupt response Flat system model Switch from real to protected mode. Privilege levels GDT Only one segment for each processor and not larger than 64K. ‘Must first be initialized with zeros due to debugging and access checks. LDT Can have one segment per process, hence each process on one computer can have its very own logical memory address space. 16 Index = 13 -GDT P: = ar rivilege =2 Metits Multitasking Access rights a 1 Privilege levels Complete system crash of the PC is impossible Page 8 of 18,13. Selector Logical Address 0 Seg. Descriptor-f” H 6 eoT/tpt__, ® a Descriptor Table Linear Ac DR Page Offset f= © Conrot Page I Register | Directory] (CR3) __JJ | J Physical Address Fig 6 Combined Segmentation paging system ® @ Explain the functions of the bus interface unit in an Intel 8086 microprocessor. @) Illustrate how data transfer to and from the microprocessor is controlled. [7 marks} Soln: The bus interface unit consists of three major functions; Control, address and data transfers. Controls: Figure I (2) shows the bus control unit. The controller handles all the control signals required between the microprocessor and the interfaced devices. This signals include data transfers ay between the memories, I/O devices and the microprocessor including the Interrupt acknowledge signal for communicating with Interrupt devices. Latches: For effective transfer of address information to targeted device, a buffer would be required to aid in reconciliation of speeds. A latch will thus serve this purpose. Latches can also be enabled by ® using signal ALE so that only during the instant an address is conveyed that they are active. Data transceiver This are very essential elements during data transfers. Intel 8086 uses multiplexing mode of transferring address and data at various destined instances of an instruction cycle. Tri-state Page 9 of 18,buffers/ latches are the controlling elements. During the time the latches are enabled transceivers are disabled, 8086 D[15:0] —— = |) Data <> mark bi AD[15:0] &) Figure Q1.0: (a) Components of Bus interface Unit (b) Transceiver Transceivers Figure I (b) shows transceivers with their control signals. DEN is data enable DT/R is a signal ‘sed to enable the tri-states during transmission or receiving of data to the microprocessor. DEN ]DTR | Tristate 0 fo Low impedance out=0 0 1 Low impedance out = 1 im 0 High impedance out= open ect | ae High impedance out = open ect Depending on the logic level of DT/R data is either transmitted from or received to the microprocessor. @ With the aid of diagrams, explain with reference to stack memory the Sequence of events that ‘ake place when a microprocessor executes a CALL type of instruction {6 marks} Page 10 of 18(LIFO) memory type. Hence whenever data is popped out of the stack, there is a probability of Popping the wrong address particularly where multiple pushing exists MAIN PUSH POP ci CALL Sas 4 LIFO RESUME MAIN RET @ CALL procedure (@) STACK Question 4 @ 0 With the aid of diagram (3) explain how asynchronous type of serial data communication i achieved in computer networks. (i) Mlustrate how phase encoded type of snchronous data communication | functions. [10 marks} i Soln: \ @ Idling bits Stop bits wt lal) 1 Character Parity bit Istart bit ie 8bits “| ‘Asynchronous transmission is used in systems that utilise serial peripherals at low data rates (30 characters per second). Such systems require interface that generate and check parity bits, recognise or add start and stop bits so that bits can be properly be identified. The systems are also required to accept the appropriate control and status signals. Universal Asynchronous Receiver transmitter (UART) modules perform this type of communication. Legitimate data word (including parity bit if any) is preceded by a start bit ‘O” and followed by | one to two stop bits as shown in fig. 4. jg rect 1 ating bits 4 | | F¥ Qvaky Asynchronous serial data transmission Page 11 of 18 {Each peripheral has its own clock. UART generally use a clock rate that is either 16 or 64 times the frequency of the bit rate or bit time. The high to low transition on the signal line starts the clock in the receiver portion of the UART or the peripheral. Refer to ‘double buffer UART transmitter / receiver logic diagram. No common system clock that provides synchronism of incoming and outgoing data stream 0 Bittime (ts): Time duration of any of the bits of a character which includes the start bit, parity and stop bits. Ty = K X tep where tepis the clock period of the receiver clock Elimination of false start / true start High to low transition starts a counter in the receiver. Referring to an eight bit character transfer, after nine (9) counts, the signal is sampled to determine if high or low. If the line goes high after a false start instead of a low due to parity, the receiver will interpret this as a false start UART operation with a true start has nine consecutive zeros (default). Having recognized there was a proper start bit, the counter resets itself and starts a count of a full bit time (ie. 16 full clock periods). If the serial data is 12 bits wide, the counter will recycle 12 times. The receiver will Took for legitimate start bit and synchronize oni ignoring any noise pulses. ‘1 Mii) Figure belew shows one of the many methods which may be used. In this case the data is phase- encoded (or Manchester encoded) by combining the clock signal with the data signal. A logical one is thus represented by a positive transition in the center of the bit and a logical zero demodulator circuits. The incoming data must be examined for recognizable bit groups which signify the beginning of by a negative transition. ‘At the receiver, the data signal may easily be split into the clock and pure data components using 0 a block of data, the end of it or some other control character. i) Data stream, before encoding Clock Loglcal2are —_Loglcalone present’ by rprasentod by Sfteneten” "Tension Page 12 of 18 eneNo common system clock that provides synchronism of incoming and outgoing data stream Each peripheral has its own clock. UART generally use a clock rate that is either 16 or 64 times the frequency of the bit rate or bit time. The high to low transition on the signal line starts the clock in the receiver portion of the UART or the peripheral. Refer to “double buffer UART transmitter / receiver logic diagram. Bit time (t,): Time duration of any of the bits of a character which includes the start bit, parity and stop bits. st clock Ty = K X tep where tepis the clock period of the rect Elimination of false start / true start High to low transition starts a counter in the receiver. Referring to an eight bit character transfer, after nine (9) counts, the signal is sampled to determine if high or low. If the line goes high after a false start instead of a low due to parity, the receiver will interpret this as a false start, UART operation with a true start has nine consecutive zeros (default). Having recognized there was a proper start bit, the counter resets itself and starts a count of a full bit time (i.e. 16 full clock periods). If the serial data is 12 bits wide, the counter will recycle 12 times. The receiver will look for legitimate sar bit and synchronize oni ignoring any noise pulses i in Figure belew shows one of the many methods which may be used. In this case the data is phase encoded (or Manchester encoded) by combining the clock signal with the data signal. ‘A logical one is thus represented by a positive transition in the center of the bit and a logical zero by a negative transition. At the receiver, the data signal may easily be spli demodulator circuits. ‘The incoming data must be examined for recognizable bit groups which signify the beginning of a block of data, the end of it or some other control character. into the clock and pure data components using = UL Phase encoded signal Page 12 of 18 D v 0 0 D ®& ‘Intel microprocessors are downwards compatible’. With illustrations, explain in support of the statement. [5 marks] Soln: Cache Level-2 Address Cache Data Cache Bus BEO#-BE7# 8 byte-enables | gy stem ‘ . 20, Data Bus ee (PentiumPro) Data Parity (8 byte-enables) Figure Q4 (b) Microprocessor compatibility Byte-enable signal selects one “byte-section” of a memory: For example, a “16-bit memory” is composed of two “byte-sections” that require 2 byte-enables; a “32-bit memory” of four “byte- sections” that require four byte-enables. Most processors now also provide extra pins to carry some additional information, such as one parity bit for each byte-lane of the data bus. These wider data buses permit the design and interconnecting of 128-bit (16-section) main memories; these 16 byte- sections would now require 16 byte-enables. The processor can issue the 16 byte-enables (by internally interpreting the 4 least significant bits of the address A3-A0 and the operand size to be transferred) along with only the remaining most significant address bits (28 bits if the address is a 32-bit address). @ () Explain the term ‘Flags' as used in microprocessor systems. (i) Mlustrate the importance flags have to computer programmers. [5 marks] Son: o ‘The term flags comes from the flag register microprocessors have which is referred as the status register. Intel 8086 has a 16-bit register even though not all the bits are used. The six bits used are conditional meaning that they indicate some condition that resulted after an instruction is executed. Page 13 of 18(ii ‘executed, various conditions arise which are indicated by respective flip-flops clocked high or low. tation is bei Flags are indicators to microprocessor computation status. Whenever any computati being f) Programmers use the status of the flip-flops to make vatious decisions in programme The programs then inherit the notion of human way of thoughts and controlling the behavior Patterns man undergoes. Question 5 (a) Use illustrations of the execution unit of a microprocessor to explain the functioning of its constituent elements. [6 marks} Sol Execution unit is used mainly to execute instructions, Arithmetic and logic unit (ALU). ‘An arithmetic logic unit (ALU) is a major component of the central processing unit of a computer system. It does all processes related to arithmetic and logic operations that need to be done on instruction words. In some microprocessor architectures, the ALU is divided into the arithmetic unit (AU) and the logic unit (LU). The output of any computation may result in raising some flags. These flags are in a register called the flags register. The raising of flags becomes the program status and can, be used by programmers to make various program decisions. EU [cama] ta ese Figure Q.5 (a) Page 14 of 18Registers ‘The EU has 8 general purpose registers, labeled AH, AL, BH, BL, CH, CL, DH, and DL. These registers can be used individually for temporary storage of 8 bit data. The AL register is also called the accumulator. All the above general purpose registers can be used to store 16-bit data @ (AX, BX, CX, DX). AX becomes the 16-bit accumulator. Other registers which can be used during data manipulation are BP (base pointer), DI (Destination index), SI (Source index) and SP (stack pointer) Controls and timing Any activity going on in a microprocessor is well coordinated so that precise inputs give corresponding outputs. Well defined timing is needed so as to synchronize the system () Explain how instruction pipelining architecture functions indicating its merits to the programmer if any. (4 marks] Soin: Pipelining is the ability of a processor to process several instructions simultaneously at various stages of execution, When one instruction is fetched, the other is decoded with the third being executed while the fourth is being executed back. All these activities take place within the same time duration, thus giving an overall execution rate of one instruction per clock cycle. Considering the conventional approach that requires 4 clock eycles to fetch and execute and( - write back for one instruction, the pipelining approach is much superior as shown in figure Q 5. Ifthe start and end times of the operation are considered, the overall (average) rate of processing comes out to be nearly one (slightly greater) instruction per clock. B[FETCH [Decode] Execuis | FETCH [Decode [Exeoute | FETCH] Decode | Brecare BL L 1 2 2 2 3 3 5 Bus [sosy_[ipce | pusy_[pusy_[ipce —[pusy—[eusy[ipce —[susy ‘Non-Pipelined Execution (8085) s | FETGH | FETGH | FETCH [FETCH STOREI | FETCH |FETCH6 | READ | FETCH 1 2 3 : 5 7 T “Instruction | Decode | Decode | Decode 3 |Decode4| IDLE | DecodeS | Decode | IDLE Unit 2 a 6 a) Execution Uni Execute | Execute [Execute 3| Execute | IDLE | Execute | Execute - 1 2 4 7 a < “Address Unit ———+ | Generate Generale Address ‘Address 1 2 Fig. Q5 Pipelining of instructions Page 15 of 18© (@ Explain using block diagrams how Based Indexed mode of addressing can Based Indentd Oe effectively be used in various forms of microprocessor systems data manipulations. (i) The instruction of a certain microprocessor is stored in an eight bit memory. If the instruction itself is 1543AEH and the accumulator contains FI the effect of execution of the instruction graphically. (Refer to Table 05) Sol ll @® = MOV AX, [BXI(SI" ‘DH, illustrate 0 marks} The instruction is a data memory referencing instruction where the data segment allocated to the program is accessed. The OS formulates the 20 bit address and adds the offset as shown in figure Q5@G-D. Daa Money LactDecoter O2ASemneHtD ng eal = x [sxe mazes FigneQ 56-1) 5 Foanistes te 20 laddvess DS: fet EA is computed by adding the base register (BX or BP), an Index register (SI or DI) Index registers are used as element pointers while base registers are used as row pointers. ‘The mode of addressing becomes very effective in array manipulations, string operations or data management systems. Refer to figure Q 5 (c) (i-2) Page 16 of 18 ()Gi) Bu penfamst 0 opcode _|p|w]mon|_REG_| RM Pfolefoltols fale [ol o]of+|ol 4 / pda reg a] | Reais} [Memory Be [Operation is word] (eae Table Q 5 (¢) Instruction 1543AEH Instruction is fetched from program memory as shown inthe decoded binary information. Displacenient se he two's complement of +52H which is AEH. This means that the program memory is accessed twice Retrieval of data uses LB followed by HB protocol. arama. es | E i Lasse es on = ofa = B te | iB = eRe e | Toarusion| lUait Instruction cycle pw Decoding: 0001 01 01 O1 00 0 O11 1010 1101 Op-code mod AX Disp BP +DI £8 bit disp Page 17 of 18Instruction Mov Alpha[BP]{DI), AX; Alpha~ — 52H Execution of the instruction is such that register AX (accumulator) content is copied to stack segment data pointed by Base pointer (BP) and indexing using DI. A relative negative i displacement is then added to a specified location as shown in figure Q 5 (6) (0). Note: Addressing the stack segment using this method is like addressing code and data segments; increment access procedure. Suck Memory toca Decoter {Sek Segment $5) ced T (3 fae 2 [Offest = Register contents LEY fees] | [| Ca faa Dante L| = Figure 25 (0) 6) (OS feasts the 20 fades $5: fet Page 18 of 18Instruction Mov Alpha[BP][DI], AX ; Alpha= — 524 execution of the instruction is such that register AX (accumulator) content is copied 19 stack segment data pointed by Base pointer (BP) and indexing. using DI. A relative negative (4 ssettacement is then added toa specified location as shown in figure Q 5 (©) ©). See aces cng the stack. segment using this method is like addressing code and data segments; increment access procedure. Stack Memory Local Decoder (Stack Seamest $5) 3 le sm pas Bas Figure Q 5 (C) 9) Page 18 of 18