Lab1 EECE2123 Spr23 ToolsIntroduction
Lab1 EECE2123 Spr23 ToolsIntroduction
A. Pre-Lab:
A.1. Pre-lab background ARM Emulator
In this lab, we will be introducing the CPUlator Computer System Simulator, which has the
ability to emulate a number of different CPU architectures in an online platform. We will be
using the capability for emulating the ARMv7 Architecture
(https://cpulator.01xz.net/?sys=arm). This architecture is newer than the ARMv4 that is
discussed in the book, but it is still 32-bit and contains the commands that are covered in the
book and the lecture portion of the course. The interface for the simulator is shown below. The
debug/compiled and memory views are shown on the next page. The different sections of the
interface, color coded, will be described below.
o Step-Over, Step-Out
§ Ignore this button for now
o Continue
§ This will run your entire program. It won’t stop until it reaches the
breakpoint.
o File
§ You can open previously saved code or save your current code.
• Messages
o The messages bar tells you any status messages, like whether the assembler
succeeded, how many breakpoints were detected, how many instructions were
run, etc.
• Register View
o This is a fantastic part of the tool, and the primary reason we are using it! It lets
us peek into the register values and how they are changing with each instruction.
This shows all 16 registers of the ARM architecture. Of special interest to us will
be:
§ any registers you change in your program, R0, R1, etc.
§ the Program Counter (PC)
§ the Link Register (LR)
§ the Stack Pointer (SP)
.global _start
_start:
We will be using the simulator to introduce and gain a basic understanding of ARM assembly,
and how commands affect the contents of our registers, and how that in turn affects what
instructions are executed next, etc. You should take a high-level look at sections 6.2 – 6.3.5,
6.4.1-6.4.3, and 6.4.5 of your textbooks for overviews of the basic ARM Assembly commands
for arithmetic, conditionals, and loop/branch. Skip the memory addressing topics for now.
• See if you can predict what will appear in our registers before and after an instruction
executes.
• Explore the difference between conditional execution and unconditional execution
• Explore the difference between conditional branching and unconditional branching.
• Observe how instructions are converted to their binary representation (Book Section
6.4) and compare similar commands like ADD and SUB.
Hint: This is a fantastic way to study for your second and final exams, where we will do more in-
depth ARM Assembly, but this tool may not be used as a tool for working your exam.
B. In-Lab:
B.1. Explore the Multiply by Summation Program
1. Study the “mulsum” program (eece2123_lab1_mulsum.s). This program performs
multiplication of two numbers, saved as words at “x” and “y” and loaded into registers
R0 and R1. The program repeatedly adds the value in R0 in a loop that iterates the by
the value stored in R1.
2. Assemble the program
3. Step through it
Pay careful attention to how your registers are changing with each instruction. Make sure the
final value is what you expect.
4. Watch as the program steps through the address and contents in the Disassembly view
and watch the Register View.
5. Change the initial value of “x” to a different value and rerun your analysis.
The final results should be the final value of R0 in hexadecimal. Additionally, check the
results by converting the hexadecimal value to decimal to make sure the multiplication is
correct. You will need to write down the final values in R0 and R1 for the above cases, and
you will turn those in on Brightspace following the lab.
Open the Quartus Software on the Lab Machine (login with VUNetID and Password)
Hints:
1. Do not start any file names with numbers or special characters
2. Do not use a path to your saved files that includes a space
3. I typically have one directory in which I save my work, e.g.,
C:\Users\<VUNETID>\EECE2123L
4. Under this directory, I either have one master project EECE2123L, or I do
projects for each lab, e.g., Lab01, Lab02…
5. There will be cases when you use work from prior labs, so you will want to
make sure you give designs logical names, e.g., adder4Bit,
sevenSegmentDisplay (Note: I start names with lower-case letters and then
for subsequent words, I use upper-case for the first letter. This is a common
practice in variable naming, and I find it works well in Quartus)
EECE 2123L Digital Systems Laboratory
Laboratory Assignment #1: Intro to ARM Emulator and Quartus
While we will not connect to the board this week, we will practice building a basic single-
gate schematic and simulating. Begin by creating a new project.
Note: There is strict rules to file naming. The first letter should not be numbers, special
symbols or space. The remaining letters should not be special symbols or spaces.
Remember that you will want to get a copy of these files for future reference (mainly for
later labs), as you may not always be at this lab bench.
Click Next, create a project directory and project file with the same name (e.g. Lab01).
Click Next twice to skip adding files to the project
Set the Cyclone II device settings:
Family: Cyclone V
Pin Count: Any
Speed Grade: 6_H6
Device: 5CSXFC6D6F31C6
(The screen should look like the window shown on the next page)
Tips: After the device is set the first time for your 1st project, you can clone the same settings
for later ones.
EECE 2123L Digital Systems Laboratory
Laboratory Assignment #1: Intro to ARM Emulator and Quartus
Click Finish.
EECE 2123L Digital Systems Laboratory
Laboratory Assignment #1: Intro to ARM Emulator and Quartus
Add gates by clicking the symbol shown below, or right clicking on the main window (with
gridlines below) and selecting Insert->Symbol.
Start with the first simple circuit below, which will be used to connect an AND gate. We will use
this again later to connect to switches and flash an LED. Don’t worry about the PIN assignments
shown here, that is for connecting to the board in Lab 2.
The AND/OR/NOT gates are under Primitives->Logic (You may need to expand the existing tree
by double clicking on “c:/intelfpga_lite/18.1/quartus/libraries”)
To make wires, drag lines from ports or click on the toolbar symbol shown below. (This is the
thin wire icon, not the thick wire icon)
EECE 2123L Digital Systems Laboratory
Laboratory Assignment #1: Intro to ARM Emulator and Quartus
Note: Make sure that all your wires are correctly connected to the ports on both gates and
input/output pins. Unconnected wires will result in compiling errors.
When you finish your schematic, save it: When you go to File->Save there is a checkbox at the
bottom of the screen saying, Add file to current project. Make sure that box is checked and click
save.
Compiling
After creating your schematic, make sure that it compiles.
(Web tutorial source: https://www.youtube.com/watch?v=a8JAkKhxlQI )
Before compiling, please set your target design file as top-level entity. This may not be
necessary if your design only has one schematic.
Future Use Note: All design BDF files should be added into a project folder (multiple files can
be included in a single project but only one file can be compiled each time)
Run a Simulation
The following steps are to be adopted to simulate the AND gate. For future labs, it will be very
helpful to have this complete before the lab, as it will help you complete the lab faster.
Simulation results will be a large part of post-lab reports and some pre-lab reports.
Before we run the simulation, please modify the setting shown below to ensure simulation
environment:
a. Tell Quartus to use ModelSim-Altera for the simulation tools (Assignments -> EDA Tool
Settings -> Simulation).
b. Tell Quartus to generate a netlist for functional simulation (Assignments -> EDA Tool
Settings - Simulation -> More EDA Netlist Writer Settings -> Generate Functional Simulation
Netlist -> ON).
c. Tell Quartus to use VHDL for the simulation netlist (Assignments -> EDA Tool Settings ->
Simulation -> Format for Output Netlist -> VHDL)
d. Tell Quartus where to put the simulation netlist (Assignments -> EDA Tool Settings ->
Simulation -> Output Directory). This is usually the "simulation" folder.
e. Tell the simulator (in the simulation waveform editor, see next screenshot) to use VHDL
for the netlist language (Simulation -> Simulation Settings -> Use VHDL)
Click File->New->University Program VWF. Right click the area shown and select Insert Node or
Bus.
Click Node Find. Set filter to Pins: All, and click List (If it says no nodes available, then you either
have not compiled your schematic, or you haven’t added any pins)
Move the desired pins over to the right half (use the arrow button ‘>>’ to move all pins at once)
and click OK. Click OK on the next screen. By using these settings, you can run simulations for
predefined input values. To set the values, use the various waveform editing tools on the
toolbar. Before setting any signal values to any pins, please set grid size and simulation
EECE 2123L Digital Systems Laboratory
Laboratory Assignment #1: Intro to ARM Emulator and Quartus
end time.
Click Edit->Grid Size by setting grid size time unit. Then click Edit -> Set End time… by setting
simulation end time.
a. The overwrite clock tool lets you set a periodic clock signal over the
waveform. (Recommended)
b. The count value tool: is like overwrite clock, lets you set a periodic signal over
the waveform (on a specific pin). Once you click the count value, click on the timing
pin to change the key settings.
c. The force high and low tools: arbitrarily set the value on an input pin to high
or low.
Note: If the count tool or the force high/low tools are not available, click on one of the
nodes to highlight it.
There are several other tools as well, but the ones shown above will be used the most often.
Try using these to give yourself a test waveform that tests all possible input patterns. An
example waveform is shown next.
Click File->Save as… to save the VWF file in the same project folder with the BDF file.
Tips: BDF and VWF files related to the same design should have same names.
Click Simulation-> Run Functional Simulation or click to run simulation. After the
simulation, a read-only waveform window will pop up. Verify the output signal with original
circuit behavior. Note: if an error occurs, there is likely a naming convention mismatch
between the contents of the VWF file and the name of the VWF file. There is a reset that may
need to be performed under Simulation Settings, if you run into this today, your TA can
assist.
C. Post-Lab:
C.1 Post-Lab Submission
We will not have a formal lab report for this lab. But you will need to turn in a single PDF file
with the results from your demonstrated in-lab examples using the mulsum program. Please
EECE 2123L Digital Systems Laboratory
Laboratory Assignment #1: Intro to ARM Emulator and Quartus
include the standard information for your cover page, but your content just needs to say
that the following are the results from the mulsum program for the cases of x=? and y=?.