DesignCon 2011

PDN Design Challenges for ATE

Test Fixtures

Jose Moreira, Verigy

[email protected]

Heinz Nuessle, Verigy

[email protected]

Heidi Barnes, Verigy

[email protected]
Abstract
This paper discusses the challenges of power distribution network design in ATE test
fixtures for high-speed digital applications. Test fixtures used with ATE can be very
different from the final application PCB of the DUT. These differences can raise
questions regarding measurement results correlation. This is due to several peculiarities
of ATE test fixtures related to the ATE system mechanics, requirements for high signal
performance to allow precise measurements, and finally to the design freedoms available
to the ATE test fixture designer that are not available to the final application PCB
designer. This paper discusses some of those differences and their consequences on the
measured performance of the DUT and provides methodologies to address these
challenges using examples from real designs.

Authors’ Biographies

Jose Moreira is a senior engineer in the high speed memory R&D group at Verigy in
Böblingen, Germany. He focuses on the challenges of testing high-speed digital devices
especially in the area of test fixture design, signal integrity, jitter testing and focus
calibration. He joined Agilent Technologies (now Verigy) in 2001 and holds a Master of
Science degree in Electrical and Computer Engineering from the Instituto Superior
Técnico of the Technical University of Lisbon, Portugal. He is a senior member of the
IEEE.

Heinz Nuessle is a senior engineer in the Verigy HW R&D group in Böblingen,

Germany. He focuses on power circuits, including power for Verigy’s V93000
semiconductor test system and device power. He joined Hewlett-Packard (later Agilent,
now Verigy) in 1981 and holds a Dipl. Ing. Degree in communication engineering from
the University of Stuttgart, Germany

Heidi Barnes is a Senior Application Engineer for high frequency device interface board
designs on Verigy’s V93000 semiconductor test system focusing on both digital and
analog controlled impedance transitions for full path signal integrity. Prior to this she was
with the Agilent’s Microwave Technology Center working with thin film, thick film, and
PCB laminate chip and wire circuit design for DC to 20 GHz analog and digital
applications. She joined Agilent Technologies (now Verigy) in 1997 and holds a
Bachelor of Science degree in electrical engineering from the California Institute of
Technology.

2
Introduction
The impact of the printed circuit board (PCB) power distribution network (PDN) design
on the performance of high-speed digital applications has gained significant relevance in
the last few years with a substantial body of work available on this topic [1,2,3]. The
automated test equipment (ATE) industry is also seeing this increase in the importance of
the PDN design for the PCB test fixture, however, there is a limited amount of prior
literature dealing with the specific requirements that are unique to ATE.
ATE test fixtures can vary significantly depending on their application. From very large
PCBs (e.g. 40 cm by 60 cm) with a single IC residing in a socket with current
requirements in the hundreds of Amperes to smaller PCBs containing multiple ICs in
sockets for parallel testing (multi-site) as shown in Figure 1.

Figure 1: Large size ATE test fixture with a single DUT (left) and a smaller test fixture for 16 DUTs
(right). Both test fixtures are intended for high-speed digital applications.
The fact that a single IC, or device under test (DUT), is present (ignoring multi-site
applications) does provide a significant amount of flexibility since an ATE test fixture
does not have the economic constraints of large volume PCBs for consumer applications.
On the other side, the objective is to measure the performance of the DUT as accurately
as possible which when combined with the mechanical requirements of an ATE system
does create some specific challenges for the PDN design. It is important to understand
that the power requirements of an IC, when being tested with an ATE system can be
different from the normal operation in its final application. Tests such as scan might
generate larger amounts of switching activity which would then lead to corresponding
increases in the DUT current.

To overcome some of the design challenges of ATE test fixtures for high-speed digital
applications, one usually ends up with a very thick stack-up of dielectric layers compared
to the final application PCB as shown in Figure 2 (left) [4,5]. This additional thickness
along with the need for a test socket can have a significant negative impact on the PDN
performance as also shown in the measured impedance in Figure 2 (right). A significant
difference can be seen in the impedance profile which shows the need for additional
improvements on the ATE test fixture PDN design. This is a critical point. The power
integrity topic is still sometimes not properly addressed in the design of ATE test fixtures
even though test engineers have become more sensitive to the signal integrity challenges
of ATE test fixtures.
3
Figure 2: Comparison of the PCB thickness of an ATE test fixture to the PCB board where the DUT
will be used in its final application and the measured impedance at the same DUT power pads.

Figure 3: PDN self-impedance comparison between two different test fixtures measured at the DUT
power pads and shmoo plot comparison of the DUT reference clock period (y-axis) vs data timing (x-
axis). Green means a functional test pass at that point and red a fail. The green region at each
reference clock period represents the measured data eye width for that specific data rate.

4
It is important for the test engineer to understand that the PDN performance can have an
impact on the measured performance of the DUT. Figure 3 compares the self impedance
of two test fixtures. In this example both test fixtures are exactly the same, other than the
PDN design. The measured results clearly show that one of the test fixtures has a worse
PDN design (higher impedance) especially in the 1 to 100 MHz region. The impact on
the time domain performance can be seen in the shmoo plots also presented in Figure 3,
where the data eye width is improved (larger) utilizing the test fixture with the better
PDN performance.

In the rest of this paper we will first concentrate on some basic theory regarding power
supply stability, especially in the context of ATE DUT power supplies. Second we will
discuss power planes, sockets, stack-up and decoupling capacitors in the context of PDN
design for ATE test fixtures.

ATE DUT Power Supplies

In ATE systems there are different types of power supplies depending on the DUT
requirements. The options range from low current, low noise power supplies to high-
current power supplies for applications like microprocessor testing. The ATE power
supplies usually reside in the ATE testhead and connect to the ATE test fixture interface
through a cable assembly as shown in Figure 4.

Figure 4: ATE system (left), ATE power supply card (center) and power supply cable assembly
(right).

Figure 5: High-level overview of the connecting a ATE DUT power supply to an ATE test fixture
with a DUT.

5
ATE DUT Power Supply Stability Basics
Figure 5 shows a high-level diagram of the different components of an ATE system PDN
including the ATE DUT power supply (DPS) and the test fixture with its power planes
and decoupling capacitors.
The ATE DUT power supply and the low impedance cable that connects the ATE system
to the test fixture are designed and specified by the ATE system manufacturer. However
it is the test engineer who is responsible for the test fixture since its design is driven by
the DUT application requirements.
Each ATE DUT power supply is a system primarily consisting of three blocks: controller,
output stage and feedback circuit. Each of the blocks is described by its own transfer
function and they are arranged in a closed loop as shown in Figure 6. The desired
programmed voltage value is set as Uprog in the block diagram of Figure 6.

Figure 6: Closed control loop.

To better understand stability basics, the open-loop view is more useful. Stability can
now be described by the phase and gain characteristics of the open loop in the frequency
domain. Total gain is simply a sum of the gain (in dB) of each block and total phase is a
sum of the phase angles of each block.

Figure 7: Open control loop.

The total gain and phase totals for the open loop response are:

G0 ( ) dB = GC ( ) dB + GS ( ) dB + GFB ( ) dB (1)

 0 ( ) =  C ( ) +  S ( ) +  FB ( ) (2)

Figure 8 shows a plot of the open loop frequency response where ωT is called ‘transit’
frequency or ‘crossover’ frequency. This frequency value is set by the DPS designer. The
higher this frequency the faster the DPS will respond to changes in the DUT load. The
trade-off is that higher crossover frequencies can create over and undershooting in the
DPS response, and make the DPS more prone to instability because of smaller phase

6
margins. This is the balance the ATE DPS designer must maintain when developing a
new product for a particular application or system.
To guarantee that the feedback loop (i.e. the DUT power supply operation) is stable there
are some stability requirements that are referred to as the Nyquist stability criteria [6].
Those requirements are:

- The absolute value of G0 has to be less than 0 dB when the phase is less than
-180º
- The phase margin φM and amplitude margin AM need to be positive.

Note that if the slope of the gain graph is at least 20 dB per decade, it is sufficient to
check the phase margin only. With that slope the amplitude margin is automatically
guaranteed.

Figure 8: Stability requirements described by simplified Nyquist criteria.

The ATE test fixture is a part of the PDN control loop and it is not unusual to have an
ATE DPS that requires a minimum capacitance in the test fixture to achieve stable
operation. This minimum capacitance has the effect of decreasing open loop gain which
in turn increases the phase margin

When designing an ATE test fixture it is important to verify if there is a minimum

capacitance requirements for the ATE DPS one intends to use. For example, the Verigy
UHC4 high-current DPS requires around 270 uF to guarantee sufficient stability. But as
will be shown later this minimum capacitance needs to be implemented in a proper way
by correctly choosing the type of decoupling capacitors used to reach this minimum
required capacitance.

A capacitor is not simply a device with pure capacitance. In series with the ideal
capacitance, there is also a series resistor called ESR and a series inductance called ESL
as shown in Figure 9. They are often called ‘parasitics’ by engineers to denote a
preference that they should not exist for an ideal capacitor. However, as already stated
7
by other authors and as will be shown in this paper, they are necessary for maintaining
the stability of the whole PDN circuit.

Figure 9: ESR and ESL and their impact on the impedance response of a real capacitor.
The impedance, resonance frequency and corner frequencies of a real capacitor are then
described by the following equations:
1
Z= + R + jL (3)
jC
1
f1 = (4)
2  RC
R
f2 = (5)
2  L
1
f0 = = f1  f 2 (6) Resonance frequency
2 LC
1 L
Q= (7 ) Quality factor
R C
R C 1
D= = (8) Damping factor
2 L 2Q

There are primarily two types of capacitors available. The type with a flat resistive
bottom impedance response vs. frequency in the case of f2 > f1 and the type with a sharp
transition from a capacitive to an inductive state at the resonance frequency f0. Ceramic
capacitors typically have a sharp transition between capacitive and inductive states
because their f1 is bigger than f2. Due to a much higher capacity, and very often a higher
ESR, most tantalum and electrolytic capacitors have a very low f1 which results in a flat
resistive bottom as shown in Table 1.

The difference between both cases can be described by using (4), (5) and (6).
For f1 = f0 the condition is:
1 1 1 C
f1 = = f0 =  =  Q = 1 or D = 0.5
2  RC 2 LC R L
8
For f2 = f0 it is:
R 1 L
f2 = = f0 = R=  Q = 1 or D = 0.5
2  L 2 LC C
In other words, for D = 0.5 or Q = 1, there is:
f 2 = f1 = f 0
All three graphs have one common intersection point at f = f0 with the impedance R =
ω0L = 1/ ω0C. For that reason, f0 and D are adequate attributes to describe the behavior of
a capacitor.
Table 1: Some typical capacitors and their attributes measured by the authors.

Type f1/kHz f2/kHz f0/kHz ESR (mΩ) ESL (nH) D Q

KEMET T510 (470μF) 11.3 884 100 30 5.4 4.42 0.11
OSCON SVPC (1500μF) 10.6 265 53 10 6.0 2.5 0.2
VISHAY 594D (1000μF) 11.3 3700 205 14 0.6 9.0 0.055
Ceramic (100μF) 884 136 350 1.8 2.1 0.2 2.5
Ceramic (1μF) 15900 1590 5000 10 1.0 0.16 3.16
OSCON SEPC (270μF) 58.9 206 110 10 7.7 0.93 0.53

When connecting the DPS to an external load (i.e. the DUT and the decoupling capacitors
on the test fixture), there is an impact on the open loop frequency response. Additional
phase lags can cause the feedback loop of the DPS to become unstable.
An additional phase-shift φAS just in the area around ωT can decrease phase margin to
zero causing oscillations. Phase shifts well below ωT as well as far above ωT are less
critical as shown in Figure 10.

Figure 10: Three important areas regarding stability [7].

9
Figure 11: Schematic of an example of the connection of an ATE DUT power supply with a typical
impedance of 5 mΩ and inductance of 25 nH to a capacitor on the ATE test fixture.
When connecting a DPS to a load in the test fixture (e.g. a decoupling capacitor), the
result is a voltage divider circuit like the one illustrated in Figure 11. The ATE DPS,
including the cable assembly, are modeled by an ideal voltage source with a series
resistance R1 and a series inductance L1. The decoupling capacitor C2 is modeled with an
equivalent series resistance (ESR) R2 and an equivalent series inductance (ESL) L2.

 
The transfer function for the circuit in Figure 11 is:

 
U ( ) 1 + j R C − 2
L  C
Load
= 2 2 2 2
(
9)
U DPS ( ) 1+ j 
(R 1 + R 2) C2 − 2
(L1 +
L
)
2
C2

The phase behavior of the circuit is critical for stability. For very low frequencies, the
phase of the circuit is zero. With increasing ω, a positive imaginary term in the
numerator transitions the phase of the complete equation to a positive value. On the other
hand, such a term in the denominator turns the phase of whole equation to a negative
value. We can now compare the terms: The imaginary term in the numerator is multiplied
with R2, the term in the denominator is larger because it is multiplied with (R1 + R2).
With increasing ω, the phase starts to go first to a negative value, possibly jeopardizing
stability. For very high frequencies, the phase returns back to zero.

To better understand Equation 9, let us look at an example using an ATE DPS with an fT
= 250 kHz and a phase of -100º. This is equivalent to a phase margin of 180º-100º = 80º.
C2, consists of 500 ceramic capacitors in parallel with each one of these capacitors
having a 1 uF capacitance, an ESR of 1 mΩ and an ESL of 1 nH. The open loop response
is shown in Figure 12. In addition to the existing phase of -100º of the ATE DPS, there is
a 130º phase lag due to this capacitive load with very low ESR and ESL. The resulting
phase is -100º-130º = -230º which is 50º below the stability minimum of -180º. Such a
condition is unstable and will cause oscillations on the ATE DPS output.

10
Figure 12: Phase shift is up to about -130º over a wide frequency range around 250 kHz which
corresponds also to the critical region causing the DPS to become unstable.
In the second example we use four 270 uF electrolytic type capacitors in parallel with an
ESR of 10 mΩ and an ESL of 7.7 nH instead of the 500 ceramic capacitors from the
previous example. The resulting open loop response is shown in Figure 13.

Figure 13: Connecting in parallel four 270 μF electrolytic type capacitors to an ATE DPS. Negative
phase shift is much smaller (compared with Figure 12) and limited to a relatively small frequency
range below fT. This setup is stable.
Let us now look in more detail as to why we got a quicker return of the phase to zero in
the second example. One possible way in solving this problem is to use Equation (3) and

11
(6). Above the resonance frequency of C2, its impedance becomes inductive. Let us now
calculate the resonance frequency of just these capacitors:

1 1
f0 = = = 110kHz
2 LC 2 7.7nH  270F

The resonance frequency of this type of capacitor is below fT which defines the middle of
the critical frequency range. In the second example a capacitor has been used with a
resonance frequency lower than transit frequency of the DPS. This means that in the
critical frequency range the impedance of the capacitor is inductive. It other words,
combining an inductive source with an inductive termination causes much less phase shift
than combining an inductive source with a capacitive termination.
There is another effect which limits the phase lag. Using equation (4), f1 of this capacitor
is 58.9 kHz. Above this frequency, its impedance is mainly resistive. fMAXφ (the
frequency with the maximum phase lag) is then only slightly above f1. One only has to
guarantee that f1 is smaller than f0 by making the capacitor ESR high enough. When using
Equations (4), (6) and (8), it can be shown that the solution is D > 0.5.
From the above discussion, one can state that it is important for C2 to use a decoupling
capacitor with a resonance frequency f0 below fT of the DPS. In other words, for stability
there is some ESL required. ESL is an inherent part of each capacitor that is often not
specified in the data sheets but nevertheless is very important when designing a stable
PDN system.

Let us now investigate whether decoupling capacitors with a larger f0 can also be used. A
capacitor with a resonance frequency of 200 kHz, which is close to the fT of the ATE
DPS was selected. This resonant frequency would be too high for the previous example
A 1000 μF capacitor was chosen for simulation. The capacitance ESL values were kept
constant while the ESR was changed from a very low value to the actual value of 14 mΩ.
Figure 14 shows the obtained simulation results.

Figure 14: Simulation of 1000μF capacitor with an ESL of 0.6 nH and different ESR values (black: 1
mΩ, blue: 2 mΩ, red: 5 mΩ, green: 14 mΩ). Solid lines are gain and dashed lines the phase.

12
From to the results in Figure 14 it is possible to observe that increasing the ESR has two
effects. First it shifts fMAXφ to values above fT or in other words into the non-critical
frequency range III of Figure 10. Second it limits the maximum phase deviation.

Table 2 summarizes the recommended values when deciding the type of decoupling
capacitor to use on the ATE test fixture for an ATE DPS with a fT of 250 kHz.
Table 2: Relationship between f0, D and Q for an ATE DPS with a fT of 250 kHz.

f0 D Q
<= 100 kHz >0.5 <1
About 150 kHz >1 < 0.5
200...250 kHz >2.5 < 0.2
> 300 kHz Don't use Don't use

Note that the recommended values contain some safety margin, so using capacitors with
marginal f0 / Q combinations do not jeopardize stability. Usage of capacitors with higher
f0 would require a lot of ESR to guarantee stability, so it is better not to use them at all.

To verify that the results of the previous theoretical discussion can be observed in a real
setup an ATE DPS with a fT of 250 kHz was connected to different types of decoupling
capacitors. For each test setup the gain and phase of the open loop response was
measured and compared as shown in Figure 15.
The measured results correlate well with the theoretical predictions:

- Without a capacitor, the gain is too high, and stability is marginal

- A minimum capacitor decreases gain to improve stability
- Pure ceramic capacitors generate a huge phase lag making the DPS unstable
- Electrolytic capacitors with sufficient ESR and ESL increase the phase margin
and improve stability.
- Increases in the phase begins with f > f1 , when the capacitor starts to become
resistive
- Above f0, the capacitor becomes inductive and results in the phase returning to a
value closer to zero.
- This effect can even be observed with a self made capacitor (f0 = 150 kHz, f1 =
122 kHz, f2 = 183 kHz and D = 0.6, yellow graph in Figure 15).

13
Figure 15: Measured gain and phase of the ATE DPS complete open loop response with different
decoupling capacitors.
Figure 16 shows the ATE DPS response in the time domain for unstable and stable
configurations.

14
Figure 16: Current waveform from the ATE DPS for an unstable PDN configuration that used only
ceramic capacitors (left) and a stabilized PDN configuration with electrolytic capacitors (right).
Note that the ATE DPS used in this example was designed to provide a very fast response
to load changes in very high-current. ATE power supplies with a slower response (lower
fT) might not show such sensitivity to the decoupling capacitors because with a lower fT
the phase lag of the capacitors is well above fT.
So far, we have only discussed the bulk capacitors that provide the decoupling
capacitance to the DPS. Ceramic capacitors positioned close to, or even under the DUT,
are necessary to provide the decoupling of the higher frequencies to the DUT that the
DPS cannot provide. Due to their low ESL and ESR values they stabilize the voltage
even in case of high dI/dt of load current demand from the DUT. The choice of these
ceramic capacitors must be made taking into account the DUT requirements, and there
are several design techniques available [2]. The question is how to guarantee the stability
of the ATE DPS since, as we have seen before, if ones uses only ceramic type decoupling
capacitors with an ATE DPS having a fast response time, it might become unstable. It is
not only the excessive high f0, it is also the low damping factor D, which does not allow
the use of them solely together with a DPS.
Let us then try to understand if adding ceramic decoupling capacitors to bulk capacitors
chosen according to Table 2 has an impact on the ATE DPS stability.

Figure 17: Circuit schematic looking from a test fixture point into the DPS connected to the bulk
capacitor C2.
15
In the circuit diagram shown in Figure 17 the bulk capacitor is formed by C2 with f0 =
150 kHz and Q = 1 which guarantees the ATE DPS stability as shown before. The
impedances of all elements are noted at f =250 kHz in the circuit.
According to Thevenin's theorem, the DPS plus C2 (including its ESR and ESL) can now
be considered as a black-box. The impedance of this black-box is R1 + jωL1 in parallel
with capacitor C2. Because of the small impedance of all elements of C2, the impedance
of the black-box is mainly defined by C2. In other words, it is more or less independent
from R1 and L1 and much smaller. In this example, the inductance of the black box is
smaller by a factor of about 45 and the resistance by a factor of 10 than the pure DPS
alone without the bulk capacitor.

This now allows the insertion of additional ceramic decoupling capacitors without an
impact on the ATE DPS stability. There is an additional positive effect which is that the
phase shift caused by the ceramic capacitors is more or less independent from the
behavior of the DPS.

Note that in the previous discussions we did not take into account the distribution of the
decoupling capacitors on the test fixture. For completeness it is important to check if this
could also create a stability problem. Figure 18 shows a circuit where the ATE DPS is
connected to the DUT with one electrolytic capacitor C2 (i.e. the result of 4 electrolytic
capacitors in parallel) and one ceramic decoupling capacitor C4 (i.e. the result of 500
capacitors ceramic in parallel) that are very close to the DUT. Since the electrolytic
decoupling capacitors are usually further away from the DUT than the ceramic
decoupling capacitors and assuming that a power plane is available on the test fixture we
model the inductance and resistance between the two capacitors by a 2 nH inductance and
a 200 μΩ resistance. Note that in this model the capacitance of the power plane is
ignored. Figure 19 shows the open loop response of this new circuit.

Figure 18: Schematic of a high-level model of an ATE DPS connected to two types of decoupling
capacitors (electrolytic and ceramic) with the ceramic capacitors located close to the DUT and the
electrolytic farther away. The power plane capacitance is ignored in this model.

16
Figure 19: Simulation with 2 nH and 200 uΩ in between node 'load' (where the ATE DPS is
connected to the test fixture) and node 'dut' which is close to device under test where the ceramic
decoupling capacitors are also located. Extra phase lag between nodes ‘load’ and ‘dut’ is around 50°.
Most of this phase shift is caused by the extra inductance L3. Dotted lines are phase and solid lines are
gain.
In some cases it might be not possible to totally overcome this problem even by proper
design of the test fixture PDN. The test fixture, sockets or probe needles that connect to
the DUT may inherently have too much inductance.
A high-level model of a DPS to DUT connection with a signal sense connection is shown
in Figure 20. In addition to the model in Figure 18, sense lines are added and also the
resistance and inductance for the power and return paths.

Figure 20: Connection of an ATE DPS to a DUT with sense lines. Black traces belong to
the power path, blocking caps are magenta and sensing elements are green.

The force and return power is provided through a resistive and inductive path R3, L3,
R31, L31,L33, R33, L32 and R32, which causes some extra phase shift.
17
On the left side of Figure 20, is the DPS connected to the test fixture where an
electrolytic or tantalum capacitor C2 resides. On the right hand side, close to the DUT,
there are the ceramic blocking caps C4. In the middle of the board there might be
additional decoupling capacitors C21.
Note that to keep the schematic as simple as possible, blocking capacitors C2, C21 and
C4 are shown without their (ESR/ESL) parasitic elements and the power plane in the test
fixture is also ignored.
Sense lines are connected to DUT via R51 and R52. This allows using the optional
capacitors C51, C52, C53 and C54. They provide feedback for the AC-path from a node
further away from DUT. Such a node has less phase shift then a sense point directly at the
DUT.
Two alternative AC-paths are shown in Figure 20, C52 and C54 are closer to the DUT, C51
and C53 are closer to the DPS. The last capacitors should be used only if usage of C52 and
C54 do not provide for a stable result. The reason is that the further away from DUT the
capacitors are located, the more the load step response is affected.
Typically, the optional capacitors C51 to C54 should be in the 50 nF range. Increasing the
size of these capacitors improves stability to some extend, but additionally slows down
load step response of the DPS. For that reason it is important to increase their capacitance
only as much as necessary for stability. Also, the values of R51 and R52 should not be too
high because they generate a voltage drop across the sense lines in conjunction with the
default resistors R61 and R62 which are part of the DPS. The combination of 100 Ω and
46.4 kΩ allows to compensate for the voltage drops on power lines to 100% ∙(1- 100 Ω
/46.4 kΩ) = 99.8%.

Power Planes and Stack-up

When designing an ATE test fixture, the first critical component for the PDN
performance is the choice of the power planes which has a direct impact on the test
fixture PCB stack-up. The location of the power planes on the PCB stack-up has in turn
an impact on the inductance of the connection between the DUT and the power planes,
and on the inductance of the connection of the decoupling capacitors to the power planes
as shown in Figure 21.

Figure 21: Power plane position and stack-up thickness effect on the added inductance to the
decoupling capacitors and power planes.
18
Figure 22 shows an example of the stack-up of an ATE test fixture for a high-speed
digital application. Note the large number of power planes in the center of the board
stack-up due to symmetry constraints to prevent the PCB from warping during
fabrication. The stack-up height on this example was around 260 mil (0.66 cm).

Figure 22: Example of a test fixture stack-up for a high-speed digital application.
When designing an ATE test fixture it is important that the test engineer defines the
stack-up in conjunction with the PCB manufacturer. For example, the critical power
planes for the application should be closer to the DUT on the stack-up to reduce the
added inductance while the less critical can be further away from the DUT. This type of
19
decision can only be made by the test engineer since he has the knowledge of the
application requirements for which the test fixture is being designed. Note that the stack-
up optimization needs to also take into account the signal layers since one would also like
to minimize the via length to the DUT pads on top of the test fixture. A compromise
between the different requirements needs to be found by the test engineer.
The stack-up shown in Figure 22 is very typical for high-speed digital applications but
the continuing increase in DUT pin counts is stressing the limits of layer counts and
thicknesses on the stack-up. Alternative methods where power planes are also used as
reference planes for the high-speed signal traces are being considered [8].

As mentioned before, ATE test fixtures can have very large power planes due to
mechanical requirements on the ATE system. This large power plane has the advantage
of higher capacitance, but at the same time a disadvantage in that the resonant frequency
of the power plane will be lower due to the large geometry.

Figure 23 shows the self-impedance of a power plane measured at its center for an ATE
test fixture with a 58 cm by 43 cm area for two different dielectric materials. One is a
standard FR4 dielectric with a 2.5 mil thickness and the other a 11 μm 3M ECM
dielectric material that has been shown to provide improved performance [9].

Figure 23: Cross-section of the ATE test fixture shown in Figure 30 (right) showing the 3M ECM
power plane and comparison of impedance of an ATE test fixture power plane with an area of 58 cm
by 43 cm with 2.5 mil FR4 dielectric and a 11 μm 3M ECM dielectric measured at the center. Note
that the measured data is from a test board with double the size of the one used for the cross section.
Cross-section pictures courtesy of R&D circuits.

20
The results show a significant increase on the power plane capacitance with the 3M ECM
dielectric material and also a dampening of the high-frequency oscillations in comparison
with FR4. The cross-section also provides a good comparison of the relative sizes of both
power planes.
It is also important to point out that there are ATE applications on the other extreme
where due to the massive number of sites, the power planes for each DUT are very small
as shown in Figure 24. Note that in this case, the resonance frequency is above 1 GHz.
For some power plane geometries the multiple resonances that occur after the main
resonance frequency of the power plane might degrade the PDN performance of the test
fixture. In this case techniques like dissipative edge decoupling [10,11] can be used.
The self-impedance measurements presented in Figure 3, Figure 23 and Figure 24 were
performed using the two side probing approach described in [1] and shown in Figure 25
which avoids the added inductance of the vias to the DUT.

Figure 24: Self-impedance of a power plane with approximately 2 cm by 3 cm measured at one of the
DUT power pads with all decoupling capacitors removed (left) and the power plane layer layout
showing all the added holes for vias that additionally reduce the power plane performance.

Figure 25: Measuring the self-impedance of a power plane at the DUT power pads using a two-side
probing approach and micro-coaxial probes.

21
The DUT Socket
The socket of an ATE test fixture can also have a significant influence on its PDN
performance. The challenge is that the socket will add additional length to the vias
connecting the DUT package and the power planes on the test fixture and in this way
increase the inductance as shown in Figure 26. The clear guideline for optimizing the
PDN performance would then be to use the socket with the smallest height, i.e., in a pogo
pin type socket to use the smallest compressed pogo pin lengths. The issue is that there
are other considerations on choosing an ATE socket that go in the opposite directions.
For example, large BGA packages require sockets with large pogo pin lengths for
compliance reasons. Also, sockets with larger pogo pin lengths are usually able to handle
a larger number of insertions.
Sockets based on elastomer type connections present an advantage for PDN performance
due to their small height when compared to pogo pin type sockets. Note that elastomer
type sockets can have some limitations especially for high-current applications. Choosing
the proper socket for an application is a complex problem for which the influence on the
PDN performance is only one of several measures that need to be optimized.

Figure 26: The challenge of the added inductance form the ATE test fixture socket when compared
to the final application PCB where the DUT might be directly soldered without any socket.

Decoupling Capacitors
Decoupling capacitors are a critical part of a PDN design. Although there are several
excellent references on this topic [1,2,3], we would like to point out some options that are
available to an ATE test fixture designer that are usually not available to standard PCB
designs due to the associated cost.
As already discussed, the large thickness of some ATE test fixture stack-ups, add a
significant amount of inductance to the decoupling capacitors at the bottom of the PCB
and in this way reduce their high-frequency performance. Since an ATE test fixture
typically has a large amount of available space, one standard option is to increase the
number of capacitors of the same type so that the inductance is decreased by the parallel
sum of the capacitors. This approach has the limitation that capacitors that are mounted
far away from the DUT will also have an added inductance on top of the via inductance
connecting to the power and ground planes. Mounting some of the decoupling capacitors
on the top of the test fixture can be of some help for very thick test fixtures but for large
22
BGAs they will still be located far away from the power and ground pins that are usually
in the center of the BGA.

Another option is to increase the capacitance of the power plane using more advanced
dielectric materials and in this way allow the power plane to compensate for the reduced
performance of the decoupling capacitors as already shown in the previous section.
An even more advanced option is to embed the capacitors to avoid the mechanical
restrictions of the stack-up. Two approaches have been followed for ATE test fixtures.
The first is to embed the higher-frequency decoupling capacitors into the DUT socket as
described in [12,13,14] and shown in Figure 27.

Figure 27: Integrating decoupling capacitors on the DUT socket (reprinted with permission from
[13,14]).
A second option is to embed the higher-frequency decoupling capacitors into the ATE
test fixture. This can be done by special manufacturing technologies and the decoupling
capacitors can be embedded in the top layer below the DUT power and ground pins.
Another option is to embed the decoupling capacitors on a PCB interposer between the
test fixture PCB and the DUT socket as shown in Figure 28. Figure 29 shows a picture of
the components of a real implementation of this technique. An interposer with
elastomeric type connections is used to connect the PCB interposer with the embedded
capacitors to the test fixture. The socket is then mounted on top of the embedded
capacitor interposer where a pad connects to the socket pogo pins.

Figure 28: Embedding capacitors into a PCB to use as an interposer between the ATE test fixture
and the DUT socket (pictures courtesy of R&D circuits).
23
Figure 29: Embedded capacitor interposer (left), elastomer interposer to connect the embedded
capacitors interposer to the test fixture PCB pads (center) and the DUT socket (right).
Figure 30 shows a diagram of how the decoupling capacitors are now distributed on the
ATE test fixture and also a picture of the ATE test fixture with the interposer and socket
assembled.
Figure 31 (left) shows the results obtained with the ATE test fixture in Figure 30 intended
for the characterization of a high-speed digital multi-core IC. The ATE test fixture is
shown in (right) with a measurement interposer on top of the socket to allow the socket to
be included in the measurement [15]. The power planes on the test fixture were
implemented using a 14 μm thick 3M ECM dielectric material. A long 165.7 mil via
connected the power plane being measured to the power pads on the top of the test
fixture. Note that in the self-impedance measurement of Figure 31 both probes are on the
same side of the PCB test fixture. Although this measurement setup will include the
inductance of the via to the DUT on the measured result which will dominate the higher
frequencies [1], it does allow a better comparison since the interposer with embedded
capacitors is intended to also compensate for this via inductance since it is closer to the
DUT.

Figure 30: Decoupling capacitors distributed on an ATE test fixture with an embedded capacitors
interposer (left) and picture of an ATE test fixture with 310 mil thick stack-up and with the two
critical power planes implemented using a 14 μm 3M ECM dielectric material and with an embedded
capacitor interposer between the test fixture PCB and socket (right). The high-frequency decoupling
capacitors should be placed on the interposer.

24
Figure 31: Comparison of the self-impedance of the ATE test fixture PDN with and without the
embedded decoupling capacitors interposer. Note that in this measurement the impedance was
measured with an insertion loss measurement where both probes are in the top side of the board at a
4 mm distance.
Although these options might not be economically practical for high-volume PCBs where
cost constraints can be significant, in the context of an ATE test fixture they are
reasonable solutions to improve the PDN performance.

Conclusions
Although ATE test fixtures present some special challenges in regards to PDN design,
they also allow the application of less conventional approaches to solve these challenges.
We have pointed out that on the PDN design it is important to make sure that the ATE
DPS is operating in a stable mode especially when using an ATE DPS with a very fast
response time. In this context the ESR and ESL values of the decoupling capacitors
should not be treated simply as “parasitic” but as important characteristics of the
capacitors that enable the stability of the test fixture PDN. It is then important to choose
capacitors such as bulk tantalum capacitors that have their ESL and ESR values specified
in the manufacturer's data sheet. The location of the capacitors can have a significant
effect on what frequency range will benefit from the added capacitance. The reduction in
impedance at the higher frequencies is best accomplished by placing low ESL and ESR
ceramic capacitor on the DUT power and ground pins and taking advantage of the large
power and ground planes available on an ATE test fixture.
Advanced technologies such as embedded capacitance materials between the power and
ground planes, or ceramic SMT capacitors embedded in the PCB layers adjacent to the
DUT have been demonstrated to provide improvements when needed for high
performance applications.
The question of the ATE test fixture PDN behavior in comparison to the end-user
application PCB PDN remains a major challenge for test engineers. This is especially true
for the cases where the final application PCB PDN is not clearly defined. There is also a
clear need for the ATE test engineer to understand the PDN design in the package and die

25
so that he can simulate the PDN performance of the ATE test fixture in conjunction with
the DUT.

Acknowledgments
We would like to thank R&D Circuits for the collaboration in the investigation of
embedded capacitors and the use of new dielectric materials into ATE PCB test fixture
designs.

References
[1] Istvan Novak, “Frequency Domain Characterization of Power Distribution
Networks”, Artech House 2007.
[2] Istvan Novak, “Power Distribution Network Design Methodologies”, IEC 2008.
[3] Eric Bogatin, “Signal and Power Integrity – Simplified”, Prentice Hall 2009
[4] J. Moreira, Ming Tsai, Jonathan Kenton, Heidi Barnes and Don Faller “PCB
Loadboard Design Challenges for Multi-Gigabit Devices in Automated Test
Applications”, IEC DesignCon 2006.
[5] Jose Moreira, Hubert Werkmann, “An Engineer’s Guide to Automated Testing of
High-Speed Interfaces”, Artech House 2010.
[6] Manfred Reuter and Serge Zacher, “Regelungstechnik fuer Ingenieure“, Vieweg
Verlag, 2002.
[7] Heinz Nuessle, “Lecture in Control engineering”, Baden-Wuerttemberg Cooperative
State University Horb/Germany
[8] Erkan Acar and Tim Swettlen, “Using Ground-Signal-Power Stack-Up for Striplines
in ATE loadboard”, 2010 BiTS Workshop.
[9] J. Peiffer, B. Greenlee and I. Novak, “Electrical Performance Advantages of Ultra-
Thin Dielectric Materials Used for Power-Ground Cores in High Speed, Multilayer
Printed Circuit Board”, IPC Expo 2003.
[10] Istvan Novak, “Reducing Simultaneous Switching Noise and EMI on Ground/Power
Planes by Dissipative Edge Termination”, IEEE Transactions on Advanced Packaging
August 1999.
[11] Xin Wu, “Matched Lossy Decoupling Termination for Power Plane Noise
Mitigation”, International Symposium on Electromagnetic Compatibility, 2005.
[12] O. Vikinski, S. Lupo, G. Sizikov and C. Y. Chung, “Embedded Power Delivery
Decoupling in Small Form Factor Test Sockets”, IEEE International Test Conference
[13] A. Detofsy, O. Vikinski, S. Lupo and T. Swettlen, “Power Integrity Ingeniuty at
Test,” Burn-In and Test Socket Workshop, 2009.
[14] Shaul Lupo, Omer Vikinski, David Bogardus, Khaled Elmadbouly and Cody Jacob,
“Next Generation CiS (Capacitor in Socket) Featuring Discrete Capacitors and Elastomer
Hybrid Schemes”, Burn-In and Test Socket Workshop, 2010.
[15] Heidi Barnes, Jose Moreira, Michael Comai, Abraham Islas, Francisco Tamayo-
Broes, Mike Resso, Antonio Ciccomancini, Orlando Bell and Ming Tsai “Performance at
the DUT: Techniques for Evaluating the Performance of an ATE System at the Device
Under Test Socket”, DesignCon 2008.

26