ECE 4102

VLSI Design & Nanotechnology Laboratory

1st Edition: March 2023

List of Experiments

Exp. No. Title of the Experiment Page

1 Mask Layout Design & Simulation Using Microwind 3
Design and Analysis of Transfer Characteristics of Different Gates
2 15
Using Multisim.
3 Introduction to Verilog HDL and Xilinx ISE Design Suite. 24
4 Verilog HDL Switch Level and Behavioral Modelling 44

2|Page
Experiment-1: Mask Layout Design & Simulation Using Microwind.

1.01 Objectives

1. To introduce with stick diagram and mask layout of CMOS based Boolean functions.

2. To sketch the circuit diagram and stick diagram for Boolean functions.

3. To design the mask layout for the stick diagram in the mask layout design tool “Microwind”.

1.02 Theory

The goal of VLSI design is to transfer circuit ideas to silicon. Stick diagrams are a way to
visually represent topography and layer information. Stick diagrams use color codes to express
layer information (or monochrome encoding). Serves as a bridge between the symbolic circuit and
the actual layout.

Fig. 1.01: The colors of the different layers used in stick

diagram.

3|Page
Some rules are followed when designing stick diagrams:

I. The crossing or touching of two or more "sticks" of the same type indicates electrical
contact.
II. There is no electrical contact when two or more "sticks" of different types cross or touch.
(If electrical contact is required, we must explicitly demonstrate the connection.)
III. A transistor is formed when a polysilicon crosses diffusion layer. (If a contact is shown at
the crossing point, then it is not a transistor).

IV. Use as few contacts as feasible. One of the layers in the contact must be metal.

Stick diagrams do not display precise positioning, transistor sizes, wire lengths and widths,
boundaries, or any other type of adherence to layout or design principles. These information are
depicted in the “mask layout” of the circuit. Mask layout is designed based on the design rule.
Design rules outline geometric restrictions for the layout design and establish a line of
communication between the engineer working on the fabrication process and the IC designer. Two
approaches for design rules are used: (a) micron rules and (b) lambda based design rules. Lambda
based design rules are followed widely for designing CMOS logic functions. All width and spacing
rules are specified in terms of the parameter 𝜆. Due to this, scaling is possible in this design
approach. If the value of lambda is changed, then automatically the width and spacing of layers
will be changed.

4|Page
 Fig. 1.02: Lambda based design rules.

1.03 Experimental Procedure

Follow some common steps for designing any mask layout in Microwind:

1. Design the circuit in CMOS switch level.

2. Draw the stick diagram of the circuit.
3. Open a new file in Microwind.
4. From the palette, select the corresponding layer and draw the layout.
5. Include the proper contacts at the proper points e.g., for metal and p diffusion, include the
contact P+diff/Metal1 and similarly, for metal and n diffusion select the N+diff/metal1
contact from the palette.
6. It is highly recommended to check the design rule after adding each layer by clicking
“Design Rule Checker” of the “Analysis” tab of the toolbar.
7. Then power the layout using “Vdd Supply” and “Ground” from the palette.
8. Click “Add a clock” from the palette and then click the point where the input has to be
provided.
9. Then add a “Visible node” at the point from where the output has to be observed.
10. Then click the “Simulation” tab on the toolbar and then click “Run simulation” and then
click “Voltage vs. Time (Default)”.
11. Finally you can see the timing diagram for the circuit layout.

5|Page
  Inverter using CMOS:

Fig 1.03: CMOS inverter switch level Fig 1.04: CMOS inverter Stick diagram
circuit diagram

Fig 1.05: Mask layout of the CMOS inverter.

6|Page
 Fig. 1.06: Timing Diagram of the designed inverter.

 NOR using CMOS:

Fig 1.07: Switch level circuit diagram Fig 1.08 Stick diagram of CMOS
CMOS based NOR gate. based NOR gate.

7|Page
Fig 1.09: Mask layout of the CMOS based NOR gate.

8|Page
 Fig. 1.10: Timing Diagram of the designed CMOS based NOR gate.

 NAND using CMOS:

Fig 1.11: Switch level circuit diagram

CMOS based NAND gate.

9|Page
 Fig 1.12: Stick diagram of CMOS based NAND gate.

Fig 1.13: Mask layout of the CMOS based NAND gate.

10 | P a g e
Fig. 1.14: Timing Diagram of the designed CMOS based NAND gate.

11 | P a g e
 XOR gate Using CMOS

Fig 1.15: Switch level circuit diagram CMOS based

XOR gate.

Fig 1.16: Stick diagram of CMOS based XOR gate.

12 | P a g e
Fig 1.17: Mask layout of the CMOS based XOR gate.

13 | P a g e
Fig. 1.18: Timing Diagram of the designed CMOS based XOR gate.

14 | P a g e
Experiment-2: Design and Analysis of Transfer Characteristics of
Different Gates Using Multisim.

2.01 Objectives

1. To understand the transfer characteristics of different MOS inverters.

2. To design the circuit of MOS inverters using the tool “Multisim”.

3. To obtain the transfer characteristics of the designed circuit by using tool “Multisim”.

2.02 Theory

The inverter is the true heart of all digital designs. Once its function and features are known,
creating more complex structures like NAND gates, adders, multipliers, and microprocessors
becomes much easier. By extending the conclusions found for inverters, the electrical behavior of
these complicated circuits may be nearly entirely deduced. An inverter, often known as a NOT
gate, is a logic gate used in digital logic to implement logical negation. When a bit is input, it
produces the exact opposite bit. Usually, the bits are implemented as two contrasting voltage
levels.

Fig. 2.01: Symbol of NOT gate.

The output of a NOT gate is either a zero or a one depending on the input. As a result, it inverts
the inputs. As with all binary logic gates, one and zero may be replaced by other symbol pairs,
such as true and false or high and low.

15 | P a g e
Different types of MOS based inverters are used. For simplicity, the voltage transfer characteristics
of a resistive load nMOS inverter is described.

Fig. 2.02: The circuit diagram of a typical resistive load inverter.

When a high input voltage is applied to the input of the circuit of Fig. 2.02, the MOS is turned on
and it acts as a short circuit. The voltage across a shorted line is 0, so the voltage is LOW for the
HIGH input. Again if a voltage of zero (or less than the threshold voltage) is given to the circuit,
then the MOS remains OFF and acts like an open circuit. So, the voltage at the output is the same
as the supply voltage. In this way the output is HIGH for a LOW input voltage. In an actual inverter
circuit, the transition between VH and VL does not occur in the abrupt manner but is more gradual,
as indicated by the more realistic transfer characteristic shown in Fig. 2.03.

16 | P a g e
 Fig. 2.03: Voltage transfer characteristics (VTC) of a resistive load NMOS inverter.

VL = The nominal voltage corresponding to a low-logic state at the output of a logic gate for
𝑣𝐼 = VH. Generally, V− ≤ VL.
VH = The nominal voltage corresponding to a high-logic state at the output of a logic gate for
𝑣𝐼 = VL. Generally, VH ≤ V+.
VIL = The maximum input voltage that will be recognized as a low input logic level.
VIH = The minimum input voltage that will be recognized as a high input logic level.
VOH = The output voltage corresponding to an input voltage of VIL.
VOL = The output voltage corresponding to an input voltage of VIH.

17 | P a g e
2.03 Experimental Procedure

Follow some common steps for designing any circuit of this experiment and for simulating the
transfer characteristics:

1. Open a new file in Multisim.

2. Click on “Place” of the toolbar. Then click “Component” from the dropdown list.
3. Then select the necessary component and place it on the circuit. For MOS, don’t forget to
select the MOS which is configurable.
4. Double click on the MOS and go to the “values” tab. Click “Edit Model” at the lower right
corner.

5. Enter the specified values of the MOS. And then click “Change component”. And then
click “OK”
6. Then connect all the components to complete the circuit.
7. Put voltage and current probe to the point of interest in the circuit.
8. Click on “Simulate” of the toolbar and from the dropdown select the “Analyses and
simulation”.

18 | P a g e
9. Then set all the parameters in the DC Sweep and click “Run”.

19 | P a g e
 nMOS Resistive Load Inverter

nMOS parameters: Vth = 0.6 V, Kn = 0.0001 A/V2, W/L = 2.2/1

Fig. 2.04: Circuit diagram of nMOS resistive load inverter.

Fig. 2.05: Voltage transfer characteristics of nMOS resistive load inverter.

20 | P a g e
 nMOS Saturated Load Inverter

nMOS parameters: Vth = 0.6 V, Kn = 0.0001 A/V2, W/L = 2.2/1

Fig. 2.06: Circuit diagram of nMOS saturated load inverter.

Fig. 2.07: Voltage transfer characteristics of nMOS saturated load inverter.

21 | P a g e
 nMOS Depletion Load Inverter

nMOS parameters: Vth = 0.6 V, Kn = 0.0001 A/V2, W/L = 2.2/1

Depletion type nMOS parameters: Vth = 0.6 V, Kn = 0.0001 A/V2, W/L = 2.2/1

Fig. 2.08: Circuit diagram of nMOS depletion load inverter.

Fig. 2.09: Voltage transfer characteristics of nMOS depletion load inverter.

22 | P a g e
 CMOS Inverter
nMOS parameters: Vth = 0.6 V, Kn = 0.0002 A/V2
pMOS parameters: Vth = -0.7 V, Kp = 0.00008 A/V2

Fig. 2.10: Circuit diagram of CMOS inverter.

Fig. 2.11: Voltage transfer characteristics of CMOS inverter.

23 | P a g e
Experiment-3: Introduction to Verilog HDL and Xilinx ISE Design
Suite.

3.01 Objectives

1. To introduce with the syntax and functionalities of Verilog HDL.

2. To design different digital circuits using Verilog.

3. To understand the testbench writing rules.

3. To simulate timing diagram of different circuits using Verilog in Xilinx ISE Design Suite.

3.02 Theory

HDL stands for “Hardware Description Language”. HDLs allow the design to be simulated
earlier in the design cycle in order to remedy problems or experiment with different architectures.
Designs expressed in HDL are independent of technology, simple to create and debug, and
typically easier to read than schematics, especially for big circuits. One of the two most popular
Hardware Description Languages (HDL) used by designers of integrated circuits is Verilog HDL.
Another one is VHDL. But in this lab Verilog HDL will be covered.

Designs can be described in Verilog at four different levels of abstraction:

1. Behavioral Level Modelling: A module can be implemented in terms of the desired design
algorithm without concern for the hardware implementation details.
2. Data Flow Level Modelling: Module is designed by taken into consideration the data flow.
The program is comprised of expressions made up of input signals and assigned to outputs.
3. Gate Level Modelling: Module is implemented in terms of logic gates and interconnections
between these gates. This modelling approach is closer to the physical implementation.
4. Switch Level Modelling: Switch level modelling is the fundamental level of modelling
digital circuits.

The gate level modelling and data flow modelling will be covered in this lab.

24 | P a g e
3.02.01 Fundamentals of Verilog

A. Lexical Tokens

Verilog source text files consists of the following lexical tokens:

1. White Space: White space can contain tabs, blanks, newlines, and form feeds. Except when
used to separate other tokens, these characters are ignored.
2. Comments: Comments can be specified in two ways. a) begin the comment with double
slashes //, b) enclose comments between the characters /* and */.
3. Numbers: Number storage is defined as a number of bits, but values can be specified in
binary, octal, decimal or hexadecimal.
Examples are 3’b001, a 3-bit number, 5’d30, (=5’b11110), and 16‘h5ED4, (=16’d24276).
4. Identifiers: Identifiers are user-defined words for variables, function names, module
names, block names and instance names. Identifiers begin with a letter or underscore (Not
with a number or $) and can include any number of letters, digits and underscores.
Identifiers in Verilog are case-sensitive.
allowed symbols: ABCDE . . . abcdef. . . 1234567890_$
not allowed: anything else especially - & #@
5. Operators: Operators are one, two and sometimes three characters used to perform
operations on variables. Examples include >, +, ~, &, !=.
6. Verilog Keywords: These are words that have special meaning in Verilog. Some examples
are assign, case, while, wire, reg, and, or, nand, and module. They should not be used as
identifiers.

B. Data Types

The Verilog HDL value set consists of four basic values:

 0 (logic zero, or false condition)

 1 (logic one, or true condition)
 x (unknown logic value) x and z have limited use for synthesis.
 z (high impedance state)

25 | P a g e
 A wire represents a physical wire in a circuit and is used to connect gates or modules. The
value of a wire can be read, but not assigned to, in a function or block. A wire does not store its
value but must be driven by a continuous assignment statement or by connecting it to the output
of a gate or module.
Syntax:

reg is a Verilog variable type and does not necessarily imply a physical register. Declare
type reg for all data objects on the left hand side of expressions in inital and always procedures. A
reg is the data type that must be used for latches, flip-flops and memory. However it often
synthesizes into leads rather than storage. In multi-bit registers, data is stored as unsigned numbers
and no sign extension is done for what the user might have thought were two’s complement
numbers. Syntax: reg [msb:lsb] reg_variable_list;

The input, output ports have to be declared in Verilog modules. Input and inout ports are
of type wire. An output port can be configured to be of type wire, reg, wand, wor or tri. The
default is wire.
Syntax:

Supply0 and supply1 define wires tied to logic 0 (ground) and logic 1 (power),
respectively.
Syntax:

26 | P a g e
C. Operators

Operators in an expression perform an operation on one or more operands. Different types

of operators are used in Verilog for performing different operation. For example, arithmetic
operators are used to perform arithmetic operations which are addition, subtraction, multiplication,
division, and modulus.

The precedence of operators from highest to lowest is shown in Table 3.01. Operators on
the same level evaluate from left to right. It is strongly recommended to use parentheses to define
order of precedence and improve the readability of your code.

Table 3.01: Precedence table of Verilog operators.

Bit-wise operators always perform bit-by-bit operation between operands. They are different from
the other operators. For example, the logical AND and the bitwise AND operator are not the same.

27 | P a g e
D. Operands

 Literals are constant-valued operands that can be used in Verilog expressions. The two
common Verilog literals are:
a) String: A string literal is a one-dimensional array of characters enclosed in double
quotes (“ “).
b) Numeric: constant numbers specified in binary, octal, decimal or hexadecimal.
Syntax of numeric literals:

 Wires, regs and parameters can also be used as operands in Verilog expressions.
 Bit-selects and part-selects are a selection of a single bit and a group of bits, respectively,
from a wire, reg or parameter vector using square brackets “[ ]”. Bit-selects and part-selects
can be used as operands in expressions in much the same way that their parent data objects
are used.
Syntax:

E. Modules

A module is the principal design entity in Verilog. The first line of a module declaration
specifies the name and port list (arguments). The next few lines specifies the i/o type and width of
each port. The default port width is 1 bit. Then the port variables must be declared wire, wand,. .
., reg. The default is wire. Typically inputs are wire since their data is latched outside the module.
Outputs are type reg if their signals were stored inside an always or initial block

28 | P a g e
3.02.02 Gate Level Modelling

Most digital designs in Verilog are created at a higher level of abstraction, such as RTL.
However employing combinational components like AND and OR makes it easy to create more
compact deterministic circuits at a lower level. Since it contains gates and has a one-to-one link
between a hardware schematic and the Verilog code, modeling at this level is known as gate-level
modeling. A few fundamental logic gates, referred to as primitives, are supported by Verilog since
they may be instantiated like modules and are predefined.

Verilog supports built-in primitive gates modeling. The gates that are supported include
pull, tri-state, multiple-input, and multiple-output gates. The multiple-input gates with two or
more inputs and just one output include and, nand, or, nor, xor, and xnor. The multiple-output
gates that have just one input and one or more outputs are buf and not. Moreover, the language
allows for the modeling of tri-state gates such as bufif0, bufif1, and notif0 and notif1. These
gates feature one input, one control signal, and one output.

Fig. 3.01: Circuit diagram of a 4×1 multiplexer.

The Verilog code for the 4×1 multiplexer circuit of Fig. 3.01 in gate level modelling is given below
(https://www.javatpoint.com/verilog-gate-level-modeling):

29 | P a g e
 Verilog Code:
module 4x1_mux (out, in0, in1, in2, in3, s0, s1);

// port declarations
output out; // Output port.
input in0, in1, in2. in3; // Input ports.
input s0, s1; // Input ports: select lines.

// intermediate wires
wire inv0, inv1; // Inverter outputs.
wire a0, a1, a2, a3; // AND gates outputs.

// Inverters.
not not_0 (inv0, s0);
not not_1 (inv1, s1);

// 3-input AND gates.

and and_0 (a0, in0, inv0, inv1);
and and_1 (a1, in1, inv0, s1);
and and_2 (a2, in2, s0, inv1);
and and_3 (a3, in3, s0, s1);

// 4-input OR gate.
or or_0 (out, a0, a1, a2, a3);

endmodule

3.02.03 Data Flow Modelling

Dataflow modeling use functions that define the operation of the circuit rather than its gate
configuration. Due to the development of advanced logic synthesis tools, dataflow modeling has
grown in popularity as a design strategy. This strategy enables the circuit designer to concentrate
on improving the circuit's data flow. To achieve the desired outcomes, dataflow modeling makes
use of a number of operators that act on operands. Verilog has around 30 different types of
operators. Hardware is described in terms of the data flow from input to output in dataflow
modeling. Combinational circuits are best described using dataflow modeling. The fundamental
technique employed is a continuous assignment.

In a continuous assignment, a value is assigned to a data type called net that is used to
represent a physical link between circuit pieces. An expression that makes use of operands and
operators specifies the value that is given to the net. Gates are replaced with continuous

30 | P a g e
assignments, which represent the circuit at a higher level of abstraction. The term assign is used to
begin a continuous assignment statement.
The syntax of a continuous assignment is:

assign [delay] LHS_net = RHS_expression;

LHS_net is a destination net of one or more bit, and RHS_expression is an expression of various
operators. The statement is evaluated at any time any of the source operand value changes, and the
result is assigned to the destination net after the delay unit.

 The LHS of the assign statement must always be a scalar or vector net or a concatenation.
It cannot be a register.
 Continuous statements are always active statements, which means that if any value on the
RHS changes, LHS changes automatically.
 Registers or nets or function calls can come in the RHS of the assignment.
 The RHS expression is evaluated whenever one of its operands changes. Then the result is
assigned to the LHS.
 Delays can be specified in the assign statement.

In real-world hardware, there is a time gap between change in inputs and the corresponding
output. For example, a delay of 2 ns in an AND gate implies that the output will change after 2 ns
from the time input has changed. Delay values control the time between the change in an RHS
operand and when the new value is assigned to LHS. It is similar to specifying delays for gates.
Adding delays helps in modeling the timing behavior in simple circuits. It is getting us closer to
simulating the practical reality of a functioning circuit. The Verilog code for the 4×1 multiplexer
circuit of Fig. 3.01 in dataflow modelling is given below:
Verilog Code:
module 4x1_mux (out, in0, in1, in2, in3, s0, s1);

// port declarations
output out; // Output port.
input in0, in1, in2. in3; // Input ports.
input s0, s1; // Input ports: select lines.

assign out = (~s1 & ~s0 & in0) | (~s1 & s0 & in1) |
(s1 & ~s0 & in2) | (s1 & s0 & in3);
endmodule

31 | P a g e
3.02.04 Verilog Test Bench

A test bench supplies the signals and dumps the outputs to simulate a Verilog design
(module(s)). It invokes the design under test, generates the simulation input vectors, and
implements the system tasks to view/format the results of the simulation. It is never synthesized
so it can use all Verilog commands. For example consider a half adder designed in Verilog as
given below,
module half_adder (input wire a, b, output wire sum, carry);

assign sum = a ^ b;
assign carry = a & b;

endmodule

Now the test bench for this half adder to observe/verify the output is given below,

`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps

module half_adder_tb;

reg a, b;
wire sum, carry;

// duration for each bit = 20 * timescale = 20 * 1 ns= 20ns

localparam period = 20;

half_adder UUT (.a(a), .b(b), .sum(sum), .carry(carry));

initial // initial block executes only once

begin
// values for a and b
a = 0;
b = 0;
#period; // wait for period

a = 0;
b = 1;
#period;

a = 1;
b = 0;
#period;

a = 1;
b = 1;
#period;
end
endmodule

32 | P a g e
The simulation results for the above half adder code and the test bench will be as below,

3.03 Experimental Procedure

Dataflow Modelling of Half Adder

The following steps are to be followed to code and simulate a half adder in Xilinx ISE:

1. Click on “File” and then click on the “New Project…” to create a new project.
2. Then type the project Name as VerilogIntro and then click on the “Next” button.

3. Select “Preferred Language” as “Verilog” and then click the “Next” button.

33 | P a g e
4. Then click the “Finish” button to complete creation of the new project.

5. Right click on the “VerilogIntro” project in the Hierarchy and then click on the “New
Source”.

34 | P a g e
6. Select source type as “Verilog Module” and type “HalfAdder” as the “File Name” and then
click “Next”.

7. Now click “Next” without the specification of the ports. This will be defined by writing in
the Verilog file.

8. Then click “Finish”.

35 | P a g e
9. Now the Verilog file is added in the project which you can see in the Hierarchy.

10. Now write the Verilog code for an Half Adder.

`timescale 1ns / 1ps

module HalfAdder(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum = a^b;
assign carry = a&b;
endmodule

11. Double click on the process “Synthesize – XST”.

12. Now double click on the “View RTL Schematic”.

36 | P a g e
13. Now you can see the RTL schematic of the half adder.

14. Right click on the “VerilogIntro” project in the Hierarchy and then click on the “New
Source”.
15. Select source type as “Verilog Module” and type “HA_TB” as the “File Name” and then
click “Next”

16. Click “Next” button again.

17. Then click “Finish”. The testbench file is created.

37 | P a g e
18. Write the testbench as given below:

`timescale 1ns / 1ps

module HA_TB;
// Inputs
reg a;
reg b;
// Outputs
wire sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
HalfAdder uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
initial begin
// Initialize Inputs
a = 0; b = 0;
#100 a = 0; b = 1;
#100 a = 1; b = 0;
#100 a = 1; b = 1;
#100;
end
endmodule

19. Go to the “Simulation” view from the “Implementation” view.

20. Now double click on the “Behavioral Check Syntax” to check that the code is free of any
syntax error.

38 | P a g e
 21. Now double click on the “Simulate Behavioral Model”.

22. A window of ISim will be open with the timing diagram of the half adder.

At the bottom of the ISim window, you can see the “Console” in which you can see if any
text/number/character is need to be displayed/printed according to the code.

** For coding and simulating other circuits, the same steps from Step-1 to Step-22 are also
followed.

39 | P a g e
Gate Level Modelling of Full Adder

Verilog code:
`timescale 1ns / 1ps

module FullAdder(sum, c_out, in0, in1, c_in);

output sum, c_out;

input in0, in1, c_in;
wire s0, c0, c1;

xor x1(s0,in0,in1);
and a1(c0,in0,in1);
xor x2(sum,s0,c_in);
and a2(c1,s0,c_in);
or o1(c_out,c0,c1);

endmodule

RTL Diagram:

Fig. 3.02: RTL diagram of the designed full adder.

40 | P a g e
 Test bench:
`timescale 1ns / 1ps

module FA_TB;

// Inputs
reg in0;
reg in1;
reg c_in;

// Outputs
wire sum;
wire c_out;

// Instantiate the Unit Under Test (UUT)

FullAdder uut (
.sum(sum),
.c_out(c_out),
.in0(in0),
.in1(in1),
.c_in(c_in)
);
initial begin
// Initialize Inputs
in0 = 0; in1 = 0; c_in = 0;
#100 in0 = 0; in1 = 0; c_in = 1;
#100 in0 = 0; in1 = 1; c_in = 0;
#100 in0 = 0; in1 = 1; c_in = 1;
#100 in0 = 1; in1 = 0; c_in = 0;
#100 in0 = 1; in1 = 0; c_in = 1;
#100 in0 = 1; in1 = 1; c_in = 0;
#100 in0 = 1; in1 = 1; c_in = 1;
#100 $finish;
end

endmodule

Timing Diagram:

Fig 3.03: Timing diagram of the gate level modelled full adder.

41 | P a g e
Data Flow Modelling of Full Adder

Verilog code:
`timescale 1ns / 1ps
module FA(sum, c_out, in0, in1, c_in);

output sum, c_out;

input in0, in1, c_in;

assign sum = in0^in1;

assign c_out = (in0&in1)|(c_in&(in0^in1));
endmodule

Test bench:
`timescale 1ns / 1ps
module FA2_TB;

// Inputs
reg in0;
reg in1;
reg c_in;
// Outputs
wire sum;
wire c_out;

// Instantiate the Unit Under Test (UUT)

FA uut (
.sum(sum),
.c_out(c_out),
.in0(in0),
.in1(in1),
.c_in(c_in)
);

initial begin
// Initialize Inputs
in0 = 0; in1 = 0; c_in = 0;
#100 in0 = 0; in1 = 0; c_in = 1;
#100 in0 = 0; in1 = 1; c_in = 0;
#100 in0 = 0; in1 = 1; c_in = 1;
#100 in0 = 1; in1 = 0; c_in = 0;
#100 in0 = 1; in1 = 0; c_in = 1;
#100 in0 = 1; in1 = 1; c_in = 0;
#100 in0 = 1; in1 = 1; c_in = 1;
#100 $finish;
end
endmodule

42 | P a g e
Timing Diagram:

Fig 3.04: Timing diagram of the gate level modelled full adder.

43 | P a g e
Experiment-4: Verilog HDL Switch Level and Behavioral Modelling.

4.01 Objectives

1. To know how to design digital circuits in Verilog switch level modelling.

2. To know how to design digital circuits in Verilog behavioral modelling.

4.02 Theory

4.02-A. Verilog Switch Level Modelling

A degree of abstraction in between the logic and analog-transistor levels of abstraction is

provided by the switch level of modeling. It illustrates how transmission gates, which are
abstractions of specific MOS and CMOS transistors, are connected. For each category of
primitives—those that turn on with positive gates, like NMOS transistors, and those that turn on
with negative gates, like PMOS transistors—switches are unidirectional, bidirectional, and
resistive or non-resistive. Logic values travel from the input transistor to its output when a switch
is turned on. When a transistor is switched off, its output is always at the Z level, regardless of the
value of its input. When turned on, a unidirectional transistor transmits the value of its input to
its output. Transistors that are bidirectional conduct in both directions.

The keywords nmos and pmos can be used to denote the two different types of MOS switches.
NMOS transistors are modeled using the keyword nmos. And PMOS transistors are modeled
using the pmos keyword.

Fig. 4.01: Schematic diagram of NMOS and PMOS switches.

44 | P a g e
 Verilog Syntax:
nmos n1(out, data, control); // instantiate a nmos switch
pmos p1(out, data, control); // instantiate a pmos switch

In case of switch level modelling, two keywords “supply1” and “supply0” are used to declare the
power source and ground respectively.

For example, let’s consider the following CMOS inverter:

Fig. 4.02: Schematic diagram of CMOS inverter.

The Verilog switch level code for this circuit will be:

Verilog Code:

module CMOS_INVERTER(out, in);

output out;
input in;

supply1 pwr;
supply0 gnd;

pmos (out, pwr, in);

nmos (out, gnd, in);

endmodule

45 | P a g e
 4.02-B. Verilog Behavioral Modelling

In behavioral modelling, the behavior of the circuit is modelled employing Verilog

programming. The behavioral modelling represents the circuit at a higher level of abstraction. It
doesn’t focus on the hardware implementation. It doesn’t give any information about how the gates
and the registers are connected to perform the specific tasks. The “initial” and “always” blocks
are used in Verilog behavioral modelling. Both these blocks start executing at the simulation time
0. The initial block is executed exactly once during the simulation. If multiple initial blocks are
present, then each block is executed concurrently at the simulation time 0. The initial blocks are
used to initialize variables and drive design ports with specific values. They are commonly used
in testbenches. The syntax of initial block is given below:

initial initial begin

[single statement] [multiple statements]
end
An always block always executes (free running process). The statements inside an always block
are executed sequentially.

always @ (event) always @ (event) begin

[statement] [multiple statements]
end
The symbol @ means that the block will only be executed under the conditions stated in the
parenthesis. The statements inside the always block will be executed whenever the variables in the
parenthesis after the @ symbol changes.

Conditional statements are also used in Verilog. Two common conditional statements are the if-
else-if and the case statement. The if-else-if statement is used to impose conditions on whether
certain statements will be executed or not.

// if statement without else part if (expression) begin

if (expression) [multiple statements]
[statement] end
else begin
[multiple statements]
end

46 | P a g e
 // if statement with an else part // if-else-if statement
if (expression)
if (expression)
[statement]
[statement] else if (expression)
[statement]
else
else
[statement] [statement]

The use of if-else may is inconvenient if number of conditions to be checked is quite high. In such
occasions, the case statement is used. The case statement checks if the given expression matches
one among the other expressions inside the list and branches. A case statement begins with the
case keyword and closes with the endcase keyword.

case (<expression>)
case_item1 :
case_item2 :
case_item3 :
case_item4 :
begin
//multiple statement for case 4
end
default:
endcase

Verilog also has looping functionalities like the C language. For loop is one of them.

Fig.4.03: Flowchart of for loop.

47 | P a g e
The statements are controlled by the for loop in three steps:
1) Initialization of counter variable
2) Condition check
3) Update counter variable

Syntax:
for (initialize; condition; update) begin
[statements]
end

The truth table of a half adder is given below:

Inputs Outputs
A B C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

The Verilog code for this half adder in behavioral modelling can be written as,

module halfadder(C,S,A,B);

input A, B;
output C, S;
wire A,B;
reg C,S;
always@(A,B)
begin
if(A!=B)
S=1;
else
S=0;
if((A==1)&(B==1))
C=1;
else
C=0;
end
endmodule

48 | P a g e
4.03 Experimental Procedure

Xilinx ISE is also used for this experiment. The procedural steps to run any simulation in this
experiment are the same as the previous experiment (Experiment-3).

 Switch Level Modelling of NAND Gate

Fig. 4.04: Circuit diagram of NAND gate using MOS.

Truth table of NAND gate

x y f

0 0 1

0 1 1

1 0 1

1 1 0

49 | P a g e
 Verilog Code

`timescale 1ns / 1ps

module NAND_gate(f, x, y);
input x, y;
output f;
supply1 vdd;
supply0 gnd;
wire a;
// NAND gate body
pmos p1 (f, vdd, x);
pmos p2 (f, vdd, y);
nmos n1 (f, a, x);
nmos n2 (a, gnd, y);
endmodule

Test bench

`timescale 1ns / 1ps

module NAND_TB;
// Inputs
reg x;
reg y;

// Outputs
wire f;

// Instantiate the Unit Under Test (UUT)

NAND_gate uut (.f(f), .x(x), .y(y));

initial begin
// Initialize Inputs
x = 0; y = 0; #100;
$display("x = %b, y = %b, f= %b",x, y, f);
x = 0; y = 1; #100;
$display("x = %b, y = %b, f= %b",x, y, f);
x = 1; y = 0; #100;
$display("x = %b, y = %b, f= %b",x, y, f);
x = 1; y = 1; #100;
$display("x = %b, y = %b, f= %b",x, y, f);
end

endmodule

50 | P a g e
 Console View:

Timing Diagram:

Fig. 4.05: Timing diagram of the designed NAND gate.

 Behavioral Modelling of JK Flip Flop

51 | P a g e
 Verilog Code:

`timescale 1ns / 1ps

module JK_FF ( input J, input K, input CLK, output Q);
wire CLK, J, K;
reg Q;

always @ (posedge CLK) begin

case ({J,K})
2'b00 : Q <= Q;
2'b01 : Q <= 0;
2'b10 : Q <= 1;
2'b11 : Q <= ~Q;
endcase
end
endmodule

Test bench:

`timescale 1ns / 1ps

module JKff_TB;
reg j, k, clk;
wire q;
integer i;
JK_FF ff1 (.J(j), .K(k), .CLK(clk), .Q(q));
//Clock generation
initial begin
clk = 0;
for(i=1; i<=20; i=i+1) begin
#3 clk = ~clk;
end
end

initial begin
// Initialize inputs
j = 1; k = 0;
#10 j = 0; k = 0;
#10 j = 0; k = 1;
#10 j = 0; k = 0;
#10 j = 1; k = 1;
#10 j = 1; k = 1;
#10;
end
endmodule

52 | P a g e
Timing Diagram:

Fig. 4.06: Timing diagram of the designed JK Flip-Flop.

53 | P a g e