VL2005-VLSI Design Automation

Academic Course Description

SRM University
Faculty of Engineering and Technology
Department of Electronics and Communication Engineering

VL2005 VLSI Design Automation

Second Semester, 2014-15 (Even semester)

Course (catalog) description: There is a great need for methods to automate VLSI design methods. This
course introduces the automation techniques in physical design process.

Compulsory/Elective course: Compulsory course for M. Tech (VLSI) I year students

Credit hours: 4 credits

Course coordinator: Mr. B Srinath, Assistant Professor (O.G), Department of ECE

Instructor(s)

Name of the Class Office Office

Email Consultation
instructor handling location phone
Day 4
M.TECH
Mr. B SRINATH TP1106 [email protected] 11.00am to 4.00
VLSI
pm
Relationship to other courses
Pre-requisites : Basic knowledge in VLSI Systems
Assumed knowledge : Basic Knowledge in VLSI design technologies and theoretical computer science
Following courses : ASIC Design (VL2106)
Reference Books

1. N.A. Sherwani, “Algorithms for VLSI Physical Design Automation”, Kluwar Academic Publishers,
2002.
2. S.H. Gerez, “Algorithms for VLSI Design Automation”, John Wiley & Sons, 2008.
3. Sung Kyu Lim, “Practice Problems in VLSI physical design Automation”, Springer, 2008.
4. Charles J . Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, “Hand book of algorithms of Physical
design Automation “, CRC press, 2009.
5. Jeffrey D Ullman, “Computational aspects of VLSI”, Computer Science Press, 1984.
6. Sadiq M .Sait, Habib Youssef, “VLSI Physical design automation theory and Practice”, World
Scientific Publishing, 1999.

Page 1 of 7
 VL2005-VLSI Design Automation
.
,

Class schedule: Four 50 minutes Lecture sessions per week

Schedule
Section

Day-1 : 5 th hour
Day-4 : 1st and 2nd hour
VLSI -A
Day -5 : 4 th hour

Professional component
General - 0%
Basic Sciences - 0%
Engineering sciences & Technical arts - 0%
Professional subject - 100%

Broad area: Communication | Signal Processing | Electronics | VLSI | Embedded

Test Schedule - Theory

S. No. Test Portions Duration

1 Cycle Test Sessions 1 to 12 1 hr 40 min
2 Model Exam sessions 13 to 60 3 hrs

Course objectives

 To impart knowledge on implementation of graph theory in VLSI.

 To impart knowledge on automation methods for VLSI physical design.
 To impart knowledge on automation methods on VLSI interconnects.

Page 2 of 7
 VL2005-VLSI Design Automation

Session plan

Session Topics Text / Chapter

Unit-I DATA STRUCTURES AND BASIC ALGORITHMS

Basic terminology – Complexity Issues and NP-Hardness: algorithms for NP-hard problems-Basic
algorithms: Graph algorithms, computational Geometry algorithms- Basic data structures-Graph algorithms
for physical design: classes of graphs in physical design, relationship between graph classes, graph problems
in physical design, algorithms for Interval graphs, permutation graphs and circle graphs.
1 VLSI Design cycle and its recent trends
a) Basic Graph terminologies
2
b) Complexity issues and NP hardness
3 Computational Geometry algorithms
Basic Data structures
a) Atomic operations for layout editors
4
b) Linked list of blocks
c) Bin- Based methods Reference [1]
d) Neighbor pointers
5
e) Corner stitching

6 Classes of Graphs in physical design

Relationship between graph classes and graph problems in

7
Physical design

8 Algorithms for Interval graphs

9 Algorithms for permutation graphs

10 Algorithms for circle graphs

Unit- II PARTITIONING AND CLUSTERING

Partitioning and Clustering Metrics -Move-Based Partitioning Methods -Mathematical Partitioning
Formulations -Clustering :Hierarchical Clustering ,Agglomerative Clustering -Multilevel Partitioning.

11 Partitioning: Problem formulation and its classification

References [3 and 4]
12 Net models and Metrics: Partitioning and clustering

Page 3 of 7
 VL2005-VLSI Design Automation
Session Topics Text / Chapter

Moved based Partitioning methods

13
a) KL algorithm with example problems

b) FM algorithm and its extensions with example

14
problems
Mathematical partitioning formulation
15
a) Quadratic programming formulation

16 Linear and integer programming

Clustering : Hierarchical and agglomerative clustering

17
a) Vertex ordering

18 Connectivity and cell area

Reference [4]
Multi-level partitioning : Move based methods and new
19
methods
Unit-III FLOORPLANNING AND PLACEMENT
Floorplanning: Early research-Slicing floorplan-Floorplan representation-Packaging floorplan
representation-Recent advances in floorplanning. Placement-Introduction- Problem formulation- Simulation
based placement algorithms- Partitioning based placement algorithms-cluster growth-Quadratic assignment-
resistive network optimization.

20 Floorplanning :Problem formulation and classification

21 Floorplan topologies

22 Floorplan slicing methods and its algorithms

23 Floorplan considering placement constraints

References
24 Floorplan representation: Corner block list and Q sequence
[1,3 ,4 and 6]

25 Non-slicing methods: O-tree and B tree

26 Non-slicing methods: Sequence pair

27 Placement :Problem formulation and classification

28 Top –down partition based placement frame work

Page 4 of 7
 VL2005-VLSI Design Automation
Session Topics Text / Chapter

29 Enhancement of Min- cut placement

30 Advantages of Min-cut placement

31 Placement algorithm using Simulated annealing

32 Placement algorithm using Genetic algorithm

References [1,3 and 4]
33 Partition based placement

Unit- IV ROUTING and COMPACTION

Global Routing- Detailed routing- Over the cell routing and via minimization- clock and power routing.
Problem Formulation- Classification of Compaction algorithms- 3/2 dimensional compaction-2D
compaction- Hierarchical compaction- Recent trends in Compaction.

34 Global Routing: Problem formulation and classification

35 Maze Routing algorithm

36 Line Probe algorithms

37 Shortest Path algorithms

38 Steiner tree based algorithms

39 Detailed Routing: Problem formulation and classification

References [1,3 and 4]
40 Single layer routing and Single row routing

41 Two layer channel routing algorithms

42 LEA based algorithms

Switch Box routing:

43
classification , greedy router , Rip and re-route based router
Over the Cell Routing:
44
Cell model

45 2 layer OTC

Page 5 of 7
 VL2005-VLSI Design Automation
Session Topics Text / Chapter

46 Constrained via minimization problem

47 Clock routing schemes : H tree based algorithm

Compaction :
48
Classification and constraint based compaction

49 Virtual grid based compaction and recent trend in Compaction

Assignment 3/2 and 2D Compaction

Unit-V ISSUES ON INTERCONNECTS

Timing driven Interconnect synthesis-Buffer insertion basics-Generalized buffer insertion-Buffering in
layout environment-Global interconnect planning. Introduction to physical design for 3D circuits.

50 Wire length Radius trade-off

51 Elmore Delay based routing constructions

52 Non- Hunan Interconnect synthesis

53 Wire-sizing and non-tree routing Reference [4]

54 Van Ginneken’s algorithm

55 Two phase approach and buffer aware tree construction

56 Buffered path with blockage avoidance

57 Buffered tree with blockage avoidance

58 Routablity driven buffer planning

59 Noise aware buffer planning

60 Flip flop and buffer planning

Assignment Physical design in 3D circuits

Evaluation methods
Attendance - 5%
Cycle Test - 25%
Page 6 of 7
 VL2005-VLSI Design Automation
Model Test - 25%
Assignment - 5%
Term Paper - 10%
Final exam - 30%

Prepared by: Mr. B Srinath, Professor, Department of ECE

Dated: 05th January 2015 Revision No.: 00 Date of revision: NA

Page 7 of 7