A Project Report On

FIFO BUFFER USING HDL

SENSE SEMICONDUCTOR AND IT SOLUTIONS

PVT.LTD.
Submitted By
Ms.Y.V.N Hitha Sri
Ms.M.L Abhigna

S.NO MODIFIED DATE MODIFIED BY REVIEWED BY

1 03-06-2023 P.Tejesh
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3
4

Under the guidance of

Mr.Sudheer Reddy Mr.P.Tejeswara Rao
Chairman and Founder of SSIT FPGA Consultant

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1 ABSTRACT
This project presents the design and implementation of a First-In-First-Out (FIFO) memory
buffer using Hardware Description Language (HDL). FIFO is a fundamental data structure
extensively used in digital systems to manage data flow between different clock domains or
to buffer data for processing. The primary objective of this project is to develop a robust and
efficient FIFO design suitable for high-speed and low-latency applications in digital signal
processing, communication systems, and computer architecture.The design is implemented
in Verilog/VHDL and synthesized for FPGA deployment. Key features of the FIFO design
include parameterizable depth and width, support for synchronous and asynchronous read/write
operations, and efficient handling of underflow and overflow conditions.

The FIFO design is verified using a testbench that simulates various operating condi-
tions, ensuring reliable data storage and retrieval. The synthesized design is optimized for
minimal resource utilization and high operational speed, making it suitable for integration into
larger digital systems. Performance evaluation is conducted on an FPGA platform, where the
FIFO demonstrates effective throughput and low latency. The results show that the proposed
FIFO design meets the required specifications for a wide range of applications, showcasing
its versatility and reliability. This project contributes to the field of digital system design
by providing a flexible and efficient FIFO implementation that can be adapted to various
real-world applications.

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Contents
1 ABSTRACT 2

2 INTRODUCTION 5
2.1 Overview of FIFO buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Importance in Digital Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Data Flow Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Synchronization Between Clock Domains . . . . . . . . . . . . . . . . . . . . 5
2.5 Enhancing System Performance and Reliability . . . . . . . . . . . . . . . . . 6
2.6 Flexibility and Scalability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7 Objectives of the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 OVERVIEW OF FIFO 7
3.1 Synchronous FIFO Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Asynchronous FIFO Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Depth and Width Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Specialized FIFO Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Comparison of FIFO Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 METHODOLOGY 10
4.1 Design Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.1 FIFO Depth and Width . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.2 Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.3 Read and Write Operations . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1.4 Overflow and Underflow Management . . . . . . . . . . . . . . . . . . 11
4.1.5 Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Memory Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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 4.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 Scalability and Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 DESIGN AND IMPLEMENTATION 13

5.1 Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Program Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Constraint File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6 SIMULATION 26

7 RESULTS 26

8 CONCLUSION 29

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2 INTRODUCTION
2.1 Overview of FIFO buffers
First-In-First-Out (FIFO) buffers are a fundamental data structure widely used in digital sys-
tems to manage the flow of data between different processing units, typically in situations where
data arrives at a different rate than it is processed. The FIFO principle ensures that the first data
element written into the buffer is the first one to be read out, maintaining the order of data
entries. This characteristic makes FIFOs particularly suitable for applications that require or-
derly data transfer, such as in communication protocols, data streaming, and buffering between
asynchronous systems.

2.2 Importance in Digital Systems

FIFO (First-In-First-Out) buffers are crucial components in digital systems, playing a signifi-
cant role in managing data flow, ensuring data integrity, and facilitating communication between
different subsystems. Their importance stems from their ability to efficiently handle varying
data rates, synchronize data between different clock domains, and provide reliable data storage
and retrieval mechanisms. This section highlights the key reasons why FIFOs are indispensable
in modern digital systems.

2.3 Data Flow Management

FIFO buffers manage data flow between system components with different data rates, ensur-
ing smooth and orderly data transfer without loss or corruption. They temporarily store data
when a producer and consumer operate at mismatched speeds, maintaining data integrity.

2.4 Synchronization Between Clock Domains

FIFOs are crucial for synchronizing data transfer between different clock domains in digital
systems. They prevent data corruption by using specialized techniques to handle asynchronous
read and write operations, ensuring reliable communication across subsystems operating at dif-
ferent frequencies.

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2.5 Enhancing System Performance and Reliability
FIFOs improve system performance by enabling parallel data processing and reducing la-
tency. They handle overflow and underflow conditions effectively, enhancing the reliability and
stability of digital systems, especially in high-speed and real-time applications.

2.6 Flexibility and Scalability

FIFOs are flexible and scalable, easily configurable for various depths and widths to meet
specific application requirements. This adaptability makes them suitable for a wide range of
digital systems, from simple communication tasks to complex high-speed data processing ap-
plications.

2.7 Objectives of the Project

The primary objective of this project is to design and implement a First-In-First-Out (FIFO)
memory buffer using a Hardware Description Language (HDL) such as Verilog or VHDL. The
FIFO buffer is intended to efficiently manage data flow between different components in a
digital system, ensuring reliable data storage and retrieval while minimizing latency and maxi-
mizing throughput. The specific objectives of the project include:

• Designing a Robust FIFO Architecture

• Parameterizing FIFO Depth and Width

• Efficient Handling of Overflow and Underflow Conditions

• Optimizing for FPGA Implementation

• Verifying Functionality through Simulation

• Analyzing Performance Metrics

• Documenting Design and Implementation Details

• Ensuring Scalability and Adaptability

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3 OVERVIEW OF FIFO
3.1 Synchronous FIFO Designs
Synchronous FIFOs are designed to operate within a single clock domain, meaning that both
read and write operations are synchronized to the same clock signal. These designs are simpler
and more straightforward compared to their asynchronous counterparts, as they do not require
complex clock domain crossing techniques. The primary features of synchronous FIFOs in-
clude:

• Single Clock Domain: All operations, including reading and writing, are controlled by a
single clock signal, ensuring predictable timing and synchronization.

• Simple Control Logic:Synchronous FIFOs use straightforward control logic with read
and write pointers to manage the buffer. This simplicity reduces the risk of design errors
and makes the FIFO easier to implement and debug.

• Efficient for High-Speed Applications:Due to their simplicity and single-clock operation,

synchronous FIFOs are well-suited for high-speed applications where data throughput is
critical.

3.2 Asynchronous FIFO Designs

Asynchronous FIFOs are designed to handle data transfer between different clock domains,
making them ideal for systems where components operate at different clock frequencies. These
FIFOs employ specialized techniques to ensure data integrity across clock boundaries. Key
features of asynchronous FIFOs include:

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 • Multi-Clock Domain Support:Asynchronous FIFOs can manage read and write opera-
tions that are clocked by different clock signals, making them suitable for systems with
multiple clock domains.

• Clock Domain Crossing Techniques:These FIFOs use methods such as Gray code coun-
ters, dual-port memory, and multi-stage synchronizers to safely transfer data between dif-
ferent clock domains, preventing metastability and ensuring reliable operation.

• Greater Complexity:The design of asynchronous FIFOs is more complex due to the need
for additional synchronization logic and metastability prevention mechanisms. This com-
plexity can lead to increased design time and resource utilization.

• Versatility:Despite their complexity, asynchronous FIFOs are highly versatile and are
widely used in applications such as inter-chip communication, data buffering in SoCs,
and crossing clock domains in high-performance computing systems.

3.3 Depth and Width Variability

Existing FIFO designs also vary in terms of depth (number of storage locations) and width
(size of each data element):

• Depth:The depth of a FIFO determines the maximum number of data elements it can store
at any given time. Deeper FIFOs are used in applications where large amounts of data need
to be buffered, such as video processing or data packet buffering in network devices.

• Width:The width of a FIFO specifies the size of each data element. Wider FIFOs are
employed in applications where larger data elements, such as 32-bit or 64-bit words, need
to be stored and transferred.

• Configurable Designs:Some FIFO designs offer configurable depth and width, allowing
users to tailor the FIFO to their specific application requirements. This flexibility makes
them suitable for a broad range of digital systems.

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3.4 Specialized FIFO Designs
Several specialized FIFO designs have been developed to address specific needs in digital
systems:

• Circular FIFOs:These FIFOs use a circular buffer structure, where the read and write
pointers wrap around to the beginning of the buffer when they reach the end. Circular
FIFOs are efficient in terms of memory usage and are commonly used in situations where
continuous data streaming is required.

• Dynamic FIFOs:Dynamic FIFOs can adjust their depth dynamically based on the data
flow requirements. This adaptability makes them suitable for applications with varying
data rates, such as adaptive signal processing.

• Error-Correcting FIFOs:These FIFOs incorporate error-detection and correction mech-

anisms to ensure data integrity in systems where data corruption could occur due to noise
or other interferences. They are used in high-reliability applications such as aerospace and
telecommunications.

3.5 Comparison of FIFO Designs

Each type of FIFO design has its own advantages and trade-offs, making them suitable for
different applications:

• Synchronous FIFOsare ideal for high-speed, single-clock domain applications due to their
simplicity and low latency.

• Asynchronous FIFOsare essential for multi-clock domain systems, despite their increased
complexity and design overhead.

• Specialized FIFOscater to unique requirements such as dynamic data rates or error cor-
rection, providing tailored solutions for specific use cases.

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4 METHODOLOGY
4.1 Design Specifications
The design specifications for the FIFO (First-In-First-Out) buffer are crucial to ensure it meets
the performance, functionality, and resource requirements for its intended application in digital
systems. The following specifications outline the key design parameters, operational require-
ments, and performance criteria that guide the development of the FIFO buffer using HDL
(Hardware Description Language).
4.1.1 FIFO Depth and Width
• Depth (D):The FIFO buffer must be designed with a configurable depth, defined by the
number of storage locations it contains. The depth will be parameterized to accommodate
different application needs, ranging from small buffers (e.g., 8 or 16 entries) for simple
tasks to larger buffers (e.g., 256 or 1024 entries) for more complex or high-throughput
applications.

• Width (W):The width specifies the size of each data word stored in the FIFO, typically
in bits. The FIFO should support different data widths (e.g., 8-bit, 16-bit, 32-bit, 64-bit)
to cater to various digital systems and processing requirements. The design will allow for
parameterization of the width to optimize for different data sizes.

4.1.2 Operating Frequency

• Clock Frequency (Fclk):The FIFO must operate at a clock frequency that matches or ex-
ceeds the requirements of the digital system in which it is deployed. The design should sup-
port a wide range of operating frequencies, from low frequencies (e.g., 10 MHz) for simple
embedded systems to high frequencies (e.g., 100 MHz or higher) for high-performance
computing and real-time applications.

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4.1.3 Read and Write Operations
• Synchronous and Asynchronous Support:The FIFO design must support both syn-
chronous (single clock domain) and asynchronous (multi-clock domain) read and write
operations. This flexibility ensures the FIFO can be used in systems where the producer
and consumer operate on either the same or different clock signals.

• Read/Write Latency:The design should minimize read and write latency to ensure high-
speed data throughput. The target is to achieve a single-cycle read and write latency for
synchronous operations and minimal latency for asynchronous operations, taking into ac-
count the necessary synchronization stages.

4.1.4 Overflow and Underflow Management

• Overflow Handling:The FIFO must include mechanisms to detect and handle overflow
conditions, where the buffer is full and cannot accept new data. The design should provide
an overflow flag to indicate this condition, and the control logic should prevent additional
write operations until space becomes available.

• Underflow Handling:Similarly, the FIFO must handle underflow conditions, where the
buffer is empty and there is no data to read. An underflow flag should indicate this condi-
tion, and the design should prevent further read operations until new data is written to the
buffer.

4.1.5 Control and Status Signals

• Status Flags:The FIFO design should include status flags such as full, empty, almost full,
and almost empty to provide real-time information about the buffer’s state. These flags
help in managing the data flow and implementing effective control strategies.

• Write and Read Pointers:The FIFO should utilize separate read and write pointers to
track the positions for reading from and writing to the buffer. These pointers must be
updated efficiently to reflect the current state of the buffer.

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4.2 Memory Utilization
The FIFO should be designed to utilize memory efficiently, minimizing the use of memory
blocks or registers on the FPGA or ASIC. The design should aim for optimal memory usage to
ensure that the FIFO does not consume excessive resources, which is crucial for integrating the
FIFO into larger, more complex systems.

4.3 Power Consumption

Power consumption is a critical factor, especially in battery-powered or portable applications.
The FIFO design should aim for low power consumption, leveraging techniques such as clock
gating or power-down modes when the FIFO is not in use.

4.4 Scalability and Flexibility

• Scalable Design:The FIFO should be scalable, allowing easy adjustment of depth and
width to suit different application requirements without significant redesign effort. This
scalability ensures the FIFO can be used across a range of applications, from simple data
buffering to complex data handling in high-speed digital systems.

• Configurable Parameters:The design should be highly configurable, with parameters for

depth, width, clock frequency, and other operational characteristics. This configurabil-
ity enables easy adaptation to various system requirements and simplifies the integration
process.

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5 DESIGN AND IMPLEMENTATION
The architecture of a FIFO (First-In-First-Out) buffer is designed to efficiently manage data
storage and retrieval in digital systems. A typical FIFO consists of a memory array to store data,
along with read and write pointers that track the positions for reading and writing operations.
The control logic coordinates these operations, ensuring data is processed in the correct order
and manages conditions like overflow and underflow. Status flags such as ”full” and ”empty”
are used to indicate the FIFO’s state, allowing for effective data flow management. There
are two main types of FIFO architectures: synchronous, which operates with a single clock
domain, and asynchronous, which supports multiple clock domains. Asynchronous FIFOs
use additional synchronization logic to safely transfer data between different clock domains,
making them suitable for complex digital systems.

Figure 1: block diagram

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5.1 Flow Chart

Figure 2:

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 5.2 Program Code
1 module fifo_test(
2 input clk_100MHz, // 100MHz
3 input reset, // btnC
4 input wr, // btnU - upload
5 input rd, // btnD - download
6 input [2:0] sw, // data value 3 bits
7 output full, // LED15
8 output empty, // LED0
9 output [2:0] data_out // read data - LEDs 7,6,5
10 );
11 // signal declaration
12 wire write, read;
13 debounce_explicit debounce_unit1(
14 .clk_100MHz(clk_100MHz),
15 .reset(reset),
16 .btn(wr),
17 .db_level(), // unconnected
18 .db_tick(write)
19 );
20 debounce_explicit debounce_unit2(
21 .clk_100MHz(clk_100MHz),
22 .reset(reset),
23 .btn(rd),
24 .db_level(), // unconnected
25 .db_tick(read)
26

27 );

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 1 fifo #(.DATA_SIZE(3), .ADDR_SPACE_EXP(2)) fifo_unit(
2 .clk(clk_100MHz),
3 .reset(reset),
4 .write_to_fifo(write),
5 .read_from_fifo(read),
6 .write_data_in(sw),
7 .read_data_out(data_out),
8 .full(full),
9 .empty(empty)
10 );
11 endmodule
12 module sev_seg(input clk,input rst,output reg[3:0] an,output reg
[7:0]ca,input wr,
13 input rd,
14 input [2:0] sw,
15 output full,
16 output empty);
17 wire [2:0]read_data_out;
18 reg [31:0]count=0;
19 reg clk_seg;
20 always@(posedge clk)
21 begin
22 if (count==100000)
23 begin
24 clk_seg= ˜clk_seg;
25 count<=0;
26 end

16
 1 else count<= count+1;
2 end
3 reg [1:0]sel;
4 wire [7:0]ca1,ca2,ca0;
5 always@(posedge clk_seg)
6 begin
7 case(sel)
8 2’b00: begin an=4’b1110; ca=ca0; end
9 2’b01: begin an=4’b1101; ca=ca1; end
10 2’b10: begin an=4’b1011; ca=ca2; end
11 2’b11: begin an=4’b1111; ca=0; end
12 endcase
13 sel<=sel+1;
14 end
15 fifo_test t1(clk,rst,wr,rd,sw,full,empty,read_data_out);
16 display d1(clk,read_data_out[0],ca0);
17 display d2(clk,read_data_out[1],ca1);
18 display d3(clk,read_data_out[2],ca2);
19 endmodule
20 module fifo // Parameterized FIFO Unit
21 #(
22 parameter DATA_SIZE = 8, // number of bits in a data word
23 ADDR_SPACE_EXP = 4 // number of address bits (2ˆ4 = 16
addresses)
24 )
25 (
26 input clk,
27 input reset,

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 1 input write_to_fifo,
2 input read_from_fifo,
3 input [DATA_SIZE-1:0] write_data_in,
4

5 output [DATA_SIZE-1:0] read_data_out,

6 output empty,
7 output full
8 );
9 // signal declaration
10 reg [DATA_SIZE-1:0] memory [2**ADDR_SPACE_EXP-1:0]; // memory
array register
11 reg [ADDR_SPACE_EXP-1:0] current_write_addr,
current_write_addr_buff, next_write_addr;
12 reg [ADDR_SPACE_EXP-1:0] current_read_addr,
current_read_addr_buff, next_read_addr;
13 reg fifo_full, fifo_empty, full_buff, empty_buff;
14 wire write_enabled;
15 // body
16 // register file (memory) write operation
17 always @(posedge clk)
18 if(write_enabled)
19 memory[current_write_addr] <= write_data_in;
20 // register file (memory) read operation
21 assign read_data_out = memory[current_read_addr];
22 // only allow write operation when FIFO is NOT full
23 assign write_enabled = write_to_fifo & ˜fifo_full;
24 // FIFO control logic
25 // register logic

18
 1 always @(posedge clk or posedge reset)
2 if(reset) begin
3 current_write_addr <= 0;
4 current_read_addr <= 0;
5 fifo_full <= 1’b0;
6 fifo_empty <= 1’b1; // FIFO is empty after reset
7 end
8 else begin
9 current_write_addr <= current_write_addr_buff;
10 current_read_addr <= current_read_addr_buff;
11 fifo_full <= full_buff;
12 fifo_empty <= empty_buff;
13 end
14 // next state logic for read and write address pointers
15 always @* begin
16 // successive pointer values
17 next_write_addr = current_write_addr + 1;
18 next_read_addr = current_read_addr + 1;
19 // default: keep old values
20 current_write_addr_buff = current_write_addr;
21 current_read_addr_buff = current_read_addr;
22 full_buff = fifo_full;
23 empty_buff = fifo_empty;
24 // Button press logic
25 case({write_to_fifo, read_from_fifo}) // check both buttons
26 // 2’b00: neither buttons pressed, do nothing
27 2’b01: // read button pressed?

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 1 if(˜fifo_empty) begin // FIFO not empty
2 current_read_addr_buff = next_read_addr;
3 full_buff = 1’b0; // after read, FIFO not full anymore
4 if(next_read_addr == current_write_addr)
5 empty_buff = 1’b1;
6 end
7 2’b10: // write button pressed?
8 if(˜fifo_full) begin // FIFO not full
9 current_write_addr_buff = next_write_addr;
10 empty_buff = 1’b0; // after write, FIFO not empty anymore
11 if(next_write_addr == current_read_addr)
12 full_buff = 1’b1;
13 end
14 2’b11: begin // write and read
15 current_write_addr_buff = next_write_addr;
16 current_read_addr_buff = next_read_addr;
17 end
18 endcase
19 end
20 // output
21 assign full = fifo_full;
22 assign empty = fifo_empty;
23 endmodule
24 module display(clk,value,cath);
25 input clk;
26 input value;
27 output reg [7:0]cath;
28 always@(posedge clk)

20
 1 begin
2 case(value)
3 1’b0: cath=8’b0000_0011;
4 1’b1: cath=8’b1001_1111;
5 endcase
6 end
7 endmodule
8 module debounce_explicit(
9 input clk_100MHz,
10 input reset,
11 input btn, // button input
12 output reg db_level, // for switches
13 output reg db_tick // for buttons
14 );
15

16 // state declarations
17 parameter [1:0] zero = 2’b00,
18 wait0 = 2’b01,
19 one = 2’b10,
20 wait1 = 2’b11;
21 // Artix-7 has a 100MHz clk with a period of 10ns
22 // number of counter bits (2ˆN * 10ns = ˜40ms)
23 parameter N = 22;
24 // signal declaration
25 reg [1:0] state_reg, next_state;
26 reg [N-1:0] q_reg;
27 wire [N-1:0] q_next;
28 wire q_zero;

21
 1 reg q_load, q_dec;
2 // FSMD state and data registers
3 always @(posedge clk_100MHz or posedge reset)
4 if(reset) begin
5 state_reg <= zero;
6 q_reg <= 0;
7 end
8 else begin
9 state_reg <= next_state;
10 q_reg <= q_next;
11 end
12 // FSMD data path (counter) next state logic
13 assign q_next = (q_load) ? {N{1’b1}} : // load all 1s
14 (q_dec) ? q_reg - 1 : // decrement
15 q_reg; // no change in q
16 assign q_zero = (q_next == 0);
17 // FSMD control path next state logic
18 always @* begin
19 next_state = state_reg;
20 q_load = 1’b0;
21 q_dec = 1’b0;
22 db_tick = 1’b0;
23 case(state_reg)
24 zero : begin
25 db_level = 1’b0;
26 if(btn) begin
27 next_state = wait1;
28 q_load = 1’b1;

22
 1 end
2 end
3 wait1 : begin
4 db_level = 1’b0;
5 if(btn) begin
6 q_dec = 1’b1;
7 if(q_zero) begin
8 next_state = one;
9 db_tick = 1’b1;
10 end
11 end
12 else
13 next_state = zero;
14 end
15 one : begin
16 db_level = 1’b1;
17 if(˜btn) begin
18 q_dec = 1’b1;
19 if(q_zero)
20 next_state = zero;
21 end
22 else
23 next_state = one;
24 end
25 default : next_state = zero;
26 endcase
27 end
28 endmodule

23
 5.3 Constraint File
1 set_property IOSTANDARD LVCMOS33 [get_ports clk_100MHz]
2 set_property IOSTANDARD LVCMOS33 [get_ports empty]
3 set_property IOSTANDARD LVCMOS33 [get_ports full]
4 set_property IOSTANDARD LVCMOS33 [get_ports rd]
5 set_property IOSTANDARD LVCMOS33 [get_ports reset]
6 set_property IOSTANDARD LVCMOS33 [get_ports wr]
7 set_property IOSTANDARD LVCMOS33 [get_ports {data_out[2]}]
8 set_property IOSTANDARD LVCMOS33 [get_ports {data_out[1]}]
9 set_property IOSTANDARD LVCMOS33 [get_ports {data_out[0]}]
10 set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
11 set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
12 set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
13 set_property PACKAGE_PIN W5 [get_ports clk_100MHz]
14 set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
15 set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
16 set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
17 set_property PACKAGE_PIN V19 [get_ports {data_out[2]}]
18 set_property PACKAGE_PIN U19 [get_ports {data_out[1]}]
19 set_property PACKAGE_PIN E19 [get_ports {data_out[0]}]
20 set_property PACKAGE_PIN U17 [get_ports rd]
21 set_property PACKAGE_PIN U18 [get_ports reset]
22 set_property PACKAGE_PIN T18 [get_ports wr]
23 set_property PACKAGE_PIN U16 [get_ports empty]
24 set_property PACKAGE_PIN L1 [get_ports full]
25 set_property PACKAGE_PIN W5 [get_ports clk]
26 set_property PACKAGE_PIN U18 [get_ports rst]
27 set_property PACKAGE_PIN V4 [get_ports {an[2]}]

24
 1 set_property PACKAGE_PIN U4 [get_ports {an[1]}]
2 set_property PACKAGE_PIN U2 [get_ports {an[0]}]
3 set_property PACKAGE_PIN W7 [get_ports {ca[7]}]
4 set_property PACKAGE_PIN W6 [get_ports {ca[6]}]
5 set_property PACKAGE_PIN U8 [get_ports {ca[5]}]
6 set_property PACKAGE_PIN V8 [get_ports {ca[4]}]
7 set_property PACKAGE_PIN U5 [get_ports {ca[3]}]
8 set_property PACKAGE_PIN V5 [get_ports {ca[2]}]
9 set_property PACKAGE_PIN U7 [get_ports {ca[1]}]
10 set_property PACKAGE_PIN V7 [get_ports {ca[0]}]
11 set_property IOSTANDARD LVCMOS33 [get_ports clk]
12 set_property IOSTANDARD LVCMOS33 [get_ports rst]
13 set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
14 set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
15 set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
16 set_property IOSTANDARD LVCMOS33 [get_ports {ca[7]}]
17 set_property IOSTANDARD LVCMOS33 [get_ports {ca[6]}]
18 set_property IOSTANDARD LVCMOS33 [get_ports {ca[5]}]
19 set_property IOSTANDARD LVCMOS33 [get_ports {ca[4]}]
20 set_property IOSTANDARD LVCMOS33 [get_ports {ca[3]}]
21 set_property IOSTANDARD LVCMOS33 [get_ports {ca[2]}]
22 set_property IOSTANDARD LVCMOS33 [get_ports {ca[1]}]
23 set_property IOSTANDARD LVCMOS33 [get_ports {ca[0]}]
24 set_property PACKAGE_PIN W4 [get_ports {an[3]}]
25 set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]

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6 SIMULATION

Figure 3: Waveform

7 RESULTS
• FIFO empty: In figure(3), the FIFO empty LED glowing because the memory is empty
when no data is entered.

• FIFO full: In figure(4), the FIFO full LED is turned on up once data has been input into
the memory for the program’s designated number of locations four in this case.

• Data insertion into the memory:The input must first be enabled by pressing the Write
enable push button. After that, data must be entered using the switches. In a same manner,
we may keep filling the data until FIFO full is enabled.

• Reading data from memory:Press the push button read enable to view the data placed
sequentially that is, the data that is inserted first is read out first. It is evident from the
image above that the data is shown on the seven segment. This allows the data to be read
out and shown until the FIFO empty is activated.

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Figure 4: FIFO empty

Figure 5: FIFO full

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Figure 6: FIFO write

Figure 7: FIFO Read

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8 CONCLUSION
The design and implementation of a FIFO (First-In-First-Out) buffer using Hardware De-
scription Language (HDL) have been successfully achieved, addressing key requirements for
efficient data management in digital systems. This project demonstrated the importance of a ro-
bust FIFO architecture in ensuring smooth data flow between components operating at different
rates or in different clock domains. By incorporating both synchronous and asynchronous de-
signs, the FIFO provides flexibility and reliability, accommodating a wide range of applications
from simple buffering tasks to complex, high-speed data processing. The configurable depth
and width of the FIFO allow for easy adaptation to various system needs, while the effective
handling of overflow and underflow conditions ensures data integrity. The project’s successful
FPGA implementation and thorough testing under different scenarios validate its performance
and efficiency. Overall, the developed FIFO buffer enhances system performance, scalability,
and robustness, proving to be a valuable component for modern digital systems and paving the
way for future improvements and applications in advanced digital design.

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