Semiconductor Devices

EE203

Field Effect Transistors

(MOSFETs)
Module 4
Outline

• The ideal MOS Structure

• Capacitance of the MOS System
• CV of MOS System; Ideal, effect of oxide and
interface charge
• Structure and operation of MOSFET devices
• Short-Channel MOSFETs
• Devices based on MOSFET

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FETs
Field Effect Transistors

Billions of MOSFETs are in the silicon chips of every smartphone, tablet, laptop, desktop and power hungry data
centre. Without the MOSFET, the chips and the corresponding electronic devices there will be no internet, world wide web,
Google, Facebook, Instagram, Tweeter, WhatsApp, digital economy, on line shopping… In the last few decades the
MOSFET has completely transform the economy, the society and us as humans. We still do not understand in full the
magnitude and the consequences of this transformation.

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Source: Sze
FETs
Junction FET Metal-Oxide FET

CMOS
MODFET

The 1-T DRAM cell is now the most man-made object on this planet earth.

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Source: Pierret, Google
FETs

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Source: Sze
MOS system

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Source: Nanohub
MOS system

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Source: Sze
MOS
MOS Interface Physics: Flat band conditions

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Source: Baliga
MOS
MOS Interface Physics: Accumulations

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Source: Baliga
MOS
MOS Interface Physics: Depletion

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Source: Baliga
Forward Conduction
MOS Interface Physics: Inversion

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Source: Baliga
Forward Conduction
MOS Surface Charge Analysis

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Source: Baliga
Forward Conduction
MOS Surface Charge Analysis

Potential Distribution within the MOS structure operating under inversion conditions
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Source: Baliga
Forward Conduction
MOS Surface Charge Analysis

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Source: Mishra and Singh
Forward Conduction
MOS Surface Charge Analysis

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Source: Mishra and Singh
Forward Conduction
MOS Charge Analysis

Since charge neutrality exists in the bulk of the

semiconductor far removed from the oxide interface

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Source: Baliga
Forward Conduction

Debye length – distance at which charge fluctuations are screened out

to look like neutral entities

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Source: Baliga
Forward Conduction
MOS Interface Physics
Total space charge per unit area within the semiconductor

Electric field at the semiconductor surface

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Source: Baliga
Forward Conduction

Strong Inversion
Accumulation

Depletion
Weak Inversion

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Source: Baliga
Forward Conduction
MOS Interface Physics

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Source: Baliga
Forward Conduction
MOS Interface Physics

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Source: Baliga
Forward Conduction
Spatial Carrier Distribution
Under Inversion

Shared!!

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Source: Baliga
Forward Conduction
Maximum Depletion Width
defined by the on-set of strong inversion conditions.

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Source: Baliga
Forward Conduction
Threshold Voltage

The voltage applied to the metal electrode of the MOS structure is shared between the oxide
and the semiconductor

The threshold voltage (V TH ) is defined as the voltage applied to the metal electrode to enter
the strong inversion domain of operation.

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Source: Baliga
Forward Conduction

High tox leads to high Vth

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Source: Baliga
Forward Conduction
Non-idealities
1. Negative work function difference
Use of polysilicon

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Source: Baliga
Forward Conduction

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Source: Baliga
Forward Conduction
2. Oxide Charges

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Source: Baliga
Forward Conduction

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Source: Baliga
Forward Conduction

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Source: Baliga
Forward Conduction

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Source: Baliga
Forward Conduction

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Forward Conduction

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Source: nanohub.org
CV

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Source: Neaman
CV

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Source: Neaman
CV

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Source: Streetman, P-309
Forward Conduction
Channel Resistance

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Source: Baliga
Forward Conduction

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Source: Baliga
Forward Conduction
Output Characteristics

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Source: Baliga
Forward Conduction
Transfer Characteristics Output Characteristics

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Source:
 MOSFET Device Metrics

Adopted from: Lundstrom, Fundamental of Nanotransistors: Physics and Technology, 2nd Ed. 41
Forward Conduction

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Source: Baliga
Forward Conduction

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Source: Sze
 MOSFET Device Metrics:
Output characteristics at a specific VGS

Adopted from: Lundstrom, Fundamental of Nanotransistors: Physics and Technology, 2nd Ed. 44
 MOSFET Device Metrics: Output characteristics

Adopted from: Lundstrom, Fundamental of Nanotransistors: Physics and Technology, 2nd Ed. 45
MOSFET: Energy Barrier Controlled Device

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Source:
MOSFET: Energy Barrier Controlled Device

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Source:
Forward Conduction
An analytical treatment of the channel resistance can be performed
under the following assumptions:
(a) an ideal gate MOS structure with no charge transport through the gate dielectric,

(b) a free carrier mobility in the inversion layer that is independent of the transverse and
longitudinal electric fields,

(c) a uniformly doped base region,

(d) current transport through the channel exclusively by the drift phenomenon,

(e) negligible leakage current in the substrate, and

(f) a longitudinal electric field along the surface much smaller when compared with the
transverse electric field created by the gate bias. This assumption is referred to as the
gradual channel approximation.

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Source: Baliga
Forward Conduction

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Source: Baliga
Forward Conduction

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Source: Baliga
Forward Conduction

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Source: Baliga
Forward Conduction
Linear region of operation, VD << VG

RCH can be decreased by VG, but limited due to mobility degradation.

Independent of VG

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Source: Baliga
Forward Conduction
Sublinear region of operation, VD ~ VG
Reduction of inversion layer charge, pinch-off

Independent of VD, o/p impedance infinite in magnitude

• Proportional to the gate bias voltage and independent of the drain bias voltage.
• The dependence of the transconductance on the gate bias voltage is a
fundamental nonlinearity inherent in MOSFET structures that operated with
current saturation due to channel pinch-off.

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Source: Baliga
 MOSFET Small Signal Model
(Saturation Region)
• Conductance parameters:
A small change in VG or VDS will result
in a small change in ID

low-frequency:
id = g d vd + g m v g

I D
high-frequency: gd  = I Dsat0
VD VG = const

I D W eff Coxe
gm  = (VGS − VT )
VG VD = const
mL

R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.12

MOSFET Capacitances

➢ CGS and CGD are intrinsic capacitances

➢ COS and COD are parasitic capacitances
➢ CjS and CjD are reverse-biased p-n junction capacitance

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Source:Streetman
Short Channel Effects

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Source: Baliga
Short Channel Effects

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Source: Sze
Short Channel Effects

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Source: Synopsis
Short Channel Effects
Threshold Voltage Roll-off in Linear Region

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Source: Sze
Short Channel Effects
Drain-Induced Barrier Lowering (DIBL)

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Source: Sze
 Channel Length Modulation
• As VDS is increased above VDsat, the width L of the depletion
region between the pinch-off point and the drain increases,
i.e. the inversion layer length decreases.
If L is significant compared to L,
then IDS will increase slightly with
increasing VDS>VDsat, due to
“channel-length modulation”
1 1  L 
I Dsat   1 + 
IDS L − L L  L 

L  VDS − VDsat
L
  (VDS − VDsat )
L

VDS I Dsat = I Dsat0 1 +  (VDS − VDsat )

R. F. Pierret, Semiconductor Device Fundamentals, Figs. 17.2, 17-3
Short Channel Effects
Scaling Rules

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Source: Sze
 Sub-Threshold Swing, S
−1
 d (log 10 I DS )  log ID
S   
 dVGS 
kT Cdep,min
= ln (10)(1 + ) Inverse slope is
q Coxe subthreshold swing, S
[mV/dec]
NMOSFET Energy Band Profile VGS
0 VT
n(E)  exp(-E/kT)
increasing E

Source increasing
VGS Drain

distance
 CMOS Devices and Circuits
CIRCUIT SYMBOLS CMOS INVERTER CIRCUIT
N-channel P-channel VDD VOUT INVERTER
MOSFET MOSFET S LOGIC SYMBOL
VDD
D
VIN VOUT
D

S VIN
GND
0 VDD

• When VG = VDD , the NMOSFET is on and the PMOSFET is off.

• When VG = 0, the PMOSFET is on and the NMOSFET is off.

EE130/230A Fall 2013 Lecture 19, Slide 64

Thank you!!

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