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Review of Electronics Based on Single-Walled Carbon Nanotubes

Article in Topics in Current Chemistry · August 2017

DOI: 10.1007/s41061-017-0160-5

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Top Curr Chem (Z) (2017)375:75
DOI 10.1007/s41061-017-0160-5

REVIEW

Review of Electronics Based on Single-Walled Carbon

Nanotubes

Yu Cao1 • Sen Cong1 • Xuan Cao2 • Fanqi

Wu2 • Qingzhou Liu2 • Moh. R. Amer3,4 • Chongwu
Zhou1

Received: 6 March 2017 / Accepted: 11 July 2017

Ó Springer International Publishing AG 2017

Abstract Single-walled carbon nanotubes (SWNTs) are extremely promising

materials for building next-generation electronics due to their unique physical and
electronic properties. In this article, we will review the research efforts and
achievements of SWNTs in three electronic fields, namely analog radio-frequency
electronics, digital electronics, and macroelectronics. In each SWNT-based elec-
tronic field, we will present the major challenges, the evolutions of the methods to
overcome these challenges, and the state-of-the-art of the achievements. At last, we
will discuss future directions which could lead to the broad applications of SWNTs.
We hope this review could inspire more research on SWNT-based electronics, and
accelerate the applications of SWNTs.

Keywords Single-walled carbon nanotubes
Radio-frequency electronics
Digital

electronics
Macroelectronics

This article is part of the Topical Collection ‘‘Single-Walled Carbon Nanotubes: Preparation, Property
and Application’’; edited by Yan Li, Shigeo Maruyama.

& Chongwu Zhou

[email protected]
1
Department of Electrical Engineering, University of Southern California, Los Angeles,
CA 90089, USA
2
Department of Chemical Engineering and Materials Science, University of Southern California,
Los Angeles, CA 90089, USA
3
Center of Excellence for Green Nanotechnologies, Joint Centers of Excellence Program, King
Abdulaziz City for Science and Technology, P. O. Box 6086, Riyadh 11442, Saudi Arabia
4
Department of Electrical Engineering, University of California, Los Angeles, 420 Westwood
Plaza, 5412 Boelter Hall, Los Angeles, CA 90095, USA

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75 Page 2 of 36 Top Curr Chem (Z) (2017)375:75

1 Introduction

In the past one and a half decades, continued downscaling of complementary metal–
oxide–semiconductor (CMOS) technology toward nanoscale dimensions (e.g. sub-
14-nm technology nodes) has been enabled by tremendous research breakthroughs
and engineering innovations, such as the introduction of strained silicon channels,
implementing high-j/metal-gate dielectric stacks, and the use of non-planar
transistor structures such as double-gate and fin field-effect transistors (FinFETs).
Scaling beyond the silicon roadmap has generated much interest in the research of
low-dimensional [i.e. one-dimensional (1D) and two-dimensional (2D)] electronic
systems, the synthesis of nanomaterials, and the fabrication of nanoscale electronic
devices. Low-dimensional nanomaterials have the desired scaling potential and also
provide access to novel physical phenomena that results in unique electronic
properties with exceptional transport characteristics that can enable future high-
speed and low-power applications. In addition, low-dimensional materials bring
new opportunities for flexible and portable electronics due to their ultrathin
thickness. Single-walled carbon nanotubes (SWNTs) are the most prominent
representatives of 1D nanomaterials. SWNTs, with diameters ranging between 1
and 3 nm, have chirality-dependent properties. Of particular interest, semiconduct-
ing SWNTs have shown to exhibit high mobility, high current-carrying capability,
small intrinsic capacitance, and extraordinary thermal and mechanical properties
[1–5]. Owing to their unique properties, SWNTs have been widely investigated as
the channel materials for radio-frequency (RF) electronics, digital electronics, and
macroelectronics.
In the application of RF electronics, researchers have devoted a majority of their
efforts to improving the RF performance of SWNT transistors [6–18]. Different
device structures, channel length scaling, and key SWNT parameters, such as
diameter, semiconducting purity, and alignment, have all been investigated. The
milestone came in 2016 when SWNT RF transistors with cut-off frequencies greater
than 70 GHz were reported [11]. In addition, the linearity performance of these
SWNT RF transistors has also been characterized [8, 11, 13, 14, 17–20]. Moreover,
circuits (e.g. mixers and frequency doublers) [14, 16, 21] and systems (e.g. radio
receivers) [4, 22, 23] based on SWNT RF transistors have also been demonstrated
by several research groups.
In the application of digital electronics, significant progress has been achieved
experimentally. SWNT-based digital systems are theoretically proven to have more
than one order of magnitude higher energy-delay product in comparison with Si-
based complementary metal–oxide–semiconductor (CMOS) technologies [24].
Field-effect transistors (FETs) based on a single nanotube [2, 5, 25–31] and aligned
nanotube arrays [32–35] have all been fabricated and characterized, showing the
tremendous potential for building future energy-efficient digital systems. SWNT
FETs have also been further optimized in regard to nanotube alignment, dielectrics,
and metal contact, and the channel length scaling of these transistors has been
investigated systematically. Moreover, various methods to achieve n-type SWNT
FETs have been developed, and complementary operations of SWNT FETs have

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been demonstrated [36–43]. With the advancement in the transistor performance,

both SWNT digital circuits and systems, e.g. central processing units (CPUs), have
been demonstrated [35], and three-dimensional (3D) integration of SWNT digital
electronics to achieve higher transistor density and more logic functions per area
have been under active investigation [44–47].
In the application of macroelectronics, SWNT networks are considered as
excellent materials for thin-film transistors (TFTs) due to their superior electrical
performance, reliability, flexibility, and transparency [48–61]. A variety of methods
to achieve pure, high-density, high-semiconducting, and highly uniform SWNT
networks have been developed [48–50, 52, 54, 56, 62–73]. TFTs have been
fabricated based on these SWNT networks on both rigid and flexible substrates and
have been demonstrated to drive various displays and sensors [55–57, 74–76], and
even to work as building blocks for digital circuits and systems
[33, 48, 53, 68, 71, 77–82]. In addition, the application of SWNTs has extended
into printed electronics due to their printability, and has generated great impacts in
achieving large-scale and low-cost macroelectronics [49, 83–89].
In this review, we will discuss all the significant progress in the development of
SWNT-based electronics, including SWNT-based RF electronics, SWNT-based
digital electronics, and SWNT-based macroelectronics, including printed electron-
ics. In the last part, further development of SWNT-based electronics will be
discussed.

2 SWNT RF Electronics

The extraordinary properties of SWNTs, such as nanoscale size, high mobility,

small intrinsic capacitance, and high current-carrying capability, make SWNTs one
of the excellent materials for RF electronics [1–5]. In this research field, the
majority of the efforts are devoted to improving the current gain cut-off frequency
(ft) and the maximum oscillation frequency (fmax) of SWNT RF transistors which
are important for future circuit-level applications [6–18]. Recently, the RF
performance of SWNT transistors has been advanced to 70 GHz which is ready
for practical applications [11].

2.1 SWNT RF Transistors Based on CVD-Aligned Nanotubes

Arrays of aligned SWNTs are one existing form of the nanotubes used as the
channel materials for RF transistors [10, 14–16]. Chemical vapor deposition (CVD)
is a widely used method to produce aligned SWNT arrays [10, 90–92]. The density
of such aligned nanotube arrays can be as high as 130 nanotubes/lm by carefully
engineering the catalyst and controlling the synthesis conditions [10]. The CVD-
synthesized SWNT arrays are a mixture of semiconducting and metallic nanotubes,
and the semiconducting purity of such CVD-aligned SWNT with high density is
usually *60%. However, these nanotube arrays can be directly used for RF
transistors. Unlike digital electronics which require an extremely high current on/off
ratio, a high current on/off ratio is not a necessity for RF electronics.

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Kocabas et al. are one group of pioneers who reported SWNT RF transistors
based on CVD-aligned SWNTs [15]. Figure 1a presents their schematic cross-
sectional illustration of the SWNT RF transistor layout. The density of the CVD-
aligned SWNTs is 2–5 nanotubes/lm, and the channel length (L) is 700 nm. Their
device layout, which utilizes a double-channel configuration (two gate electrodes
and two drain electrodes surrounding a drain electrode), is one of the two commonly
used device structures for SWNT RF electronics. However, the drawback of this
device structure is that there exist either un-gated channel regions or overlapped
gate-to-source/drain regions which adversely affect the RF performance. Figure 1b

Fig. 1 a, b Schematic cross-sectional illustration of the SWNT RF transistors, and the corresponding
frequency response, respectively. Adapted with permission from Ref. [15]. Copyright (2009) American
Chemical Society. c, d SEM and AFM images of the high-density SWNT arrays on a sapphire surface,
and the corresponding frequency response of the transistors based on these high-density aligned SWNTs,
respectively. Adapted with permission from Ref. [10]. Copyright (2015) Nature Publishing Group. e,
f Schematic of the CVD-aligned SWNT RF transistor with the self-aligned, self-oxidized, aluminum,
T-shaped gate structure, and the corresponding frequency response, respectively. Adapted with
permission from Ref. [14]. Copyright (2013) American Chemical Society

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Top Curr Chem (Z) (2017)375:75 Page 5 of 36 75

shows the RF performance of their SWNT RF transistor. According to the current

gain (H21), unilateral power gain (U), and maximum available gain (MAG)
frequency response between 0.5 and 50 GHz, the ft, which is the unity current gain
frequency, and the fmax, which is the unity power gain frequency, are *5 and
*9 GHz, respectively.
One method to improve the RF transistors based on CVD-aligned SWNTs is to
increase the SWNT density. Hu et al. successfully achieved SWNT arrays with a
density of 130 nanotubes/lm by using a Trojan catalyst [10]. Figure 1c shows SEM
and AFM images of the as-grown high-density SWNT arrays on a sapphire surface.
The RF performance of a typical SWNT transistor based on the high-density
nanotube arrays with L = 1200 nm is shown in Fig. 1d. The extrinsic ft and fmax are
5 and 11 GHz, respectively. The intrinsic ft and fmax after device de-embedding,
which would remove only the parasitics from the bonding pads without removing
the capacitances associated with the gate, and reveal the performance of RF
transistors achievable for practical applications, is 7 and 14 GHz, respectively.
These RF transistors have similar device structure and RF performance as those
reported by Kocabas et al. [15] but with a much larger channel length, indicating
that one can achieve better RF performance by increasing the aligned nanotube
density.
Another method to improve the RF transistors based on CVD-aligned SWNTs is
to use a self-aligned gate structure. A self-aligned, self-oxidized, aluminum,
T-shaped gate structure has been developed, as is shown in Fig. 1e [14]. This self-
aligned, self-oxidized, aluminum, T-shaped gate structure has the advantages of
reducing the gate parasitic capacitance, decreasing the gate resistance, scaling down
the channel length, and offering optimized gate control. With this gate structure, the
channel length of SWNT RF transistors has been scaled down to *140 nm, and the
thickness of the gate dielectric (self-oxidized Al2O3) has been reduced to 2–4 nm.
The RF performance of these CVD-aligned SWNT transistors with a nanotube
density of *5 nanotubes/lm is shown in Fig. 1f. The extrinsic ft is as high as
25 GHz, and the intrinsic ft after intrinsic de-embedding, which would remove the
parasitics from both the bonding pads and the fringe capacitances associated with
the gate, and reveal the upper-limit performance of the material’s properties, is
*100 GHz. The fmax is *9 GHz. One can find that the ft of these transistors with a
self-aligned gate structure has been greatly improved compared with those without a
self-aligned gate structure. The fmax does not show significant improvement due to
the low semiconducting purity of CVD-aligned SWNTs. Ding et al. also developed
a similar self-aligned gate structure for single-nanotube transistors, and also
demonstrated improved RF characteristics [93].

2.2 SWNT RF Transistors Based on Nanotube Networks

SWNT networks can also be used to make RF transistors. In comparison with CVD-
aligned SWNT arrays, SWNT networks are usually formed by dispersing pre-
separated SWNT solutions onto target substrate. The advantages of SWNT
networks are that the SWNTs could be of much higher semiconducting purity than
the CVD-aligned SWNTs, which helps the fmax of the RF transistors. In addition, the

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diameter distribution of SWNTs could also be engineered to achieve the optimal

diameter range for RF transistors. However, unlike aligned SWNT arrays where the
charge transport is electrically continuous and has an independent pathway, the
charge transport in SWNT networks is based on percolation transportation. The
tube-to-tube junctions will limit the maximum carrier mobility achievable, which
limits both the ft and fmax of RF transistors. However, SWNT networks still provide
an important platform to investigate the RF performance of SWNTs, and researchers
have demonstrated RF transistors based on SWNT networks [7, 8, 13, 17, 18].
The effects of SWNT semiconducting purity and diameter distribution on the
performance of RF transistors based on SWNT networks have been investigated
systematically [17, 18]. Cao et al. applied the excellent self-aligned, self-oxidized,
aluminum, T-shaped gate structure to a variety of SWNT networks for the
investigations, as schematically shown in Fig. 2a. Figure 2b, c shows the extrinsic
and intrinsic current gain frequency response and power gain frequency response of
RF transistors based on SWNTs with 99.99% semiconducting purity, respectively
[17]. The extrinsic ft and fmax are 22 and 19 GHz, respectively, and after device de-
embedding, the intrinsic ft and fmax are 28 and 25 GHz, respectively. The RF
performance is better than that based on SWNT networks with lower semicon-
ducting purity, indicating the importance of achieving ultrahigh semiconducting
purity separation of SWNTs for RF applications. In addition, Cao et al. also
investigated the effects of diameter distribution [18]. Figure 2d shows the diameter-
separated SWNT solution which has a tight diameter distribution and an average
diameter of *1.6 nm. The RF performance of these transistors based on the
diameter-separated SWNTs are shown in Fig. 2e, f. The ft and fmax are 23 and

Fig. 2 a Schematic of the RF transistors based on SWNT networks. Adapted with permission from Ref.
[18]. Copyright (2016) American Institute of Physics. b, c Current gain frequency response and power
gain frequency response of RF transistors based on ultrahigh-purity semiconducting SWNTs,
respectively. Adapted with permission from Ref. [17]. Copyright (2016) Springer. d–f Optical
absorbance spectrum of the diameter-separated SWNTs, the current gain frequency response, and the
power gain frequency response, respectively. Adapted with permission from Ref. [18]. Copyright (2016)
American Institute of Physics

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Top Curr Chem (Z) (2017)375:75 Page 7 of 36 75

20 GHz before de-embedding, and are 65 and 35 GHz after intrinsic de-embedding,
respectively. The RF performance is similar to that based on 99.99% ultrahigh-
purity semiconducting SWNTs, indicating the necessity to achieve diameter
separation for SWNT RF electronics.
We note that the superior RF performance achieved with SWNT networks even
outperforms the best RF transistors based on CVD-aligned SWNTs, suggesting that
SWNT networks are a valuable platform for nanotube RF electronics.

2.3 SWNT RF Transistors Based on Aligned Pre-separated SWNTs

Based on the discussions above, CVD-aligned SWNTs have the advantages of free
tube-to-tube junctions and high-density while suffering from low semiconducting
purity and degraded output resistance. In comparison, SWNT networks have the
advantages of high semiconducting purity and engineered diameter distribution,
while having the disadvantages of tube-to-tube junctions and low density. The best
platform for SWNT RF transistors is to use SWNTs which go through the process of
post-synthesis sorting and assembly, combining the advantages of CVD-aligned
SWNTs and SWNT networks together.
Le Louarn et al. reported using a dielectrophoresis (DEP) assembly method to
achieve aligned SWNTs for the RF transistors [12]. The transconductance increased
by a factor of 2.5 compared with their previous work using SWNT networks, and
the de-embedded ft was 30 GHz. However, their SWNTs still suffered from a low
semiconducting purity. Steiner et al. used SWNTs with a much higher semicon-
ducting purity (*99.6%), and also achieved aligned SWNTs using the DEP
assembly method [9]. Their RF transistors showed a big improvement for SWNT
RF electronics. With a channel length of 100 nm, the extrinsic ft and fmax were 7 and
15 GHz, respectively. The intrinsic ft and fmax were 153 and 30 GHz, respectively,
using an intrinsic de-embedding structure. However, the fmax of the RF transistors is
still far below the ft, which limits the highest frequency of their SWNT RF
transistors in practical applications since a power gain is needed for real
applications.
Recently, significantly improvement of the SWNT RF transistors has been
achieved by the combined use of well-aligned, ultrahigh-purity semiconducting
([99.99%), high-density SWNTs and our self-aligned, self-oxidized, aluminum,
T-shaped gate structure [11]. The well-aligned, ultrahigh-purity semiconducting,
high-density SWNTs are achieved by dose-controlled, floating evaporative self-
assembly (DFES) of poly[(9,9-dioctylfluorenyl-2,7-diyl)-alt-co-(6,60-(2,20-bipyr-
idine))] (PFO-BPy) separated SWNTs. Figure 3a shows the SEM image of one
channel region of a typical SWNT RF transistor. The T-shaped gate, self-aligned
source and drain electrodes, and aligned PFO-BPy-sorted SWNTs underneath are
clearly demonstrated. The RF performance of these SWNT RF transistors are shown
in Fig. 3b, c. The extrinsic ft and fmax of these transistors are both *40 GHz. The
intrinsic ft and fmax are 80 GHz and 70 GHz with device de-embedding, and
100 GHz and 70 GHz with intrinsic de-embedding, respectively. The RF perfor-
mance exceeds all previously reported SWNT RF transistors, especially for the fmax,
which is at least twice that of the best previously reported results. The SWNT RF

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Fig. 3 a SEM image of a channel region of the RF transistor based on PFO-BPy-separated aligned
SWNTs. The T-shape gate, self-aligned source and drain, and aligned polyfluorene-sorted SWNTs
underneath are clearly demonstrated. b, c Current gain frequency response, and power gain frequency
response, respectively. Adapted with permission from Ref. [11]. Copyright (2016) American Chemical
Society

transistor advances the state-of-the-art of SWNT RF electronics, and may find broad
applications for signal amplifications, wireless communications, and future flexible/
wearable electronics.

2.4 Linearity Performance of SWNT RF Transistors

One great advantage of SWNT RF transistors is their linearity. Baumgardner et al.

theoretically predicted that a carbon nanotube (CNT)-based field-effect transistor
with ohmic contacts, quantum capacitance, and ballistic single-subband transport is
inherently linear [19]. However, achieving the above conditions are difficult in
realistic devices. Mothes et al. later used simulations to show that the requirements
for high-linearity SWNT transistors could be relaxed with a moderate Schottky
barrier at the source contact [20].
In addition to the simulation efforts, the linearity performance of SWNT RF
transistors can be measured using single-tone and two-tone tests. Cao et al. have
measured the linearity performance of the best SWNT RF transistors based on
aligned PFO-BPy-separated SWNTs [11]. Figure 4a shows the schematic of the
measurement setup commonly used for single-tone and two-tone tests [17]. In the
single-tone test, they apply an RF single of a fixed frequency to one input of the
measurement setup with various powers, and measure the power of the fixed
frequency component at the output. A 1-dB gain compression point (P1 dB), which
defines the power level that causes the gain to drop by 1 dB from its small signal
value, can be used to characterize the linearity. Figure 4b shows the results of the
single-tone test. The P1 dB is 13–14 dBm. In the two-tone test, they apply two RF
singles with a small frequency difference to the two inputs of the measurement
setup, and measure the powers of the fundamental frequency term and the third-
order frequency term at the output. Input third-order intercept point (IIP3) is defined
as the input power level which causes the fundamental frequency term and the third-
order frequency term to have the same output power level. Figure 4c shows the
results of the two-tone test. IIP3 is *22 dBm at a frequency of 8 GHz. Further
improvement of the linearity performance of SWNT RF transistors can be achieved
by carefully engineering the gate dielectric and source/drain contacts.

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Fig. 4 a Schematic of the measurement setup for single-tone and two-tone tests. Adapted with
permission from Ref. [17]. Copyright (2016) Springer. b, c Single-tone and two-tone test results for the
RF transistors based on PFO-BPy-separated aligned SWNTs. Adapted with permission from Ref. [11].
Copyright (2016) American Chemical Society

2.5 Circuit Applications Based on SWNT RF Transistors

In addition to transistor-level investigation of SWNT RF transistors, research groups

have integrated SWNT RF transistors into circuits for realistic applications
[4, 14, 16, 21–23].
Kocabas et al. demonstrated a radio which utilized four SWNT RF transistors
[22]. The circuit schematic, images, and frequency response are shown in Fig. 5a–c.

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Fig. 5 a Block and circuit diagrams of a radio that uses SWNT transistors for the resonant antenna, two
fixed RF amplifiers, an RF mixer, and an audio amplifier. b Image of the radio, with magnified views of
SWNT transistor wire bonded into DIP packages. c Power spectrum of the radio output, recorded during a
commercial broadcast of a traffic report. Adapted with permission from Ref. [22]. Copyright (2008)
National Academy of Sciences of the United States of America

The radio could record a commercial broadcast of a traffic report. Rutherglen et al.
and Jensen et al. also demonstrated components in a receiver built with SWNT RF
transistors [4, 23]. These receivers represent the most complex circuits so far built
with SWNT RF transistors. With the advancement of SWNT RF transistors, circuits
and systems with more complex functions and higher operation frequencies are
expected to be built. Considering that SWNTs have the inherent high linearity and
could be made to be flexible, these circuits and systems may find broad applications
for signal amplification, wireless communication, and wearable electronics.

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3 SWNT Nanoelectronics

SWNTs, due to their exceptional intrinsic carrier mobility [5], high saturation
velocity [94], and quasi-1D structure, may offer various advantages for future
digital electronics. Furthermore, the quasi-ballistic transport property of SWNTs
enables a lower energy delay product predicted to outperform silicon-based
complementary metal–oxide–semiconductor (CMOS) technologies [24]. During the
past few years, SWNT-based devices and circuits have been making progress in
various aspects under intense research.

3.1 Single SWNT Transistor

With the progress in nanotube synthesis, researchers have the material platform and
are making further steps to gain better comprehension of the electrical transport
properties of the SWNT FETs. Due to the fact that the properties of individual
nanotubes may vary strongly from one another, it is indispensable to fabricate a
transistor with a single nanotube present in the channel to fully understand the
transport properties of each nanotube. Since the report of the first individual SWNT
FETs [25], the high current-carrying capacity in the quantum ballistic regime [2],
the high carrier mobility in the diffusive regime [5], and the low leakage current
[26] have all been investigated. Furthermore, researchers have also worked
extensively to improve the device performance by carefully studying the ohmic
contacts between SWNTs and the contact metal, optimizing the device structures,
and scaling down the device dimensions.
Up to now, the superior intrinsic properties of SWNTs have been confirmed by
single nanotube FETs. Javey and coworkers did pioneering work by demonstrating
high-performance ballistic SWNT FETs using palladium (Pd) contacts, with the
room-temperature conductance near the ballistic transport limit of G0 = 4e2/h and
the high current-carrying capability of 25 lA per tube [2]. Kim and co-workers
developed a method to deduce the mean free path by studying the channel length
dependence of the channel resistance, where they confirmed that the long mean free
path of SWNTs is on the order of a millimeter [27]. To study the diffusive transport,
Durkop et al. fabricated semiconducting SWNT FETs with ultralong channel
lengths larger than 300 microns, and estimated the intrinsic SWNT mobility to be
10,000 cm2 V-1 s-1 at room temperature, which was the highest value for all
known semiconductors at the time of study [5]. Weitz and coworkers demonstrated
that transistors based on individual CNTs can achieve large transconductance
(5 lS), small subthreshold swing (68 mV/dec), large on/off ratio (107), and good
reliability of performance under ambient conditions simultaneously [28].
For future high-performance SWNT circuits, the scaling of SWNT FETs is
inevitable to pack more transistors on the chip. Of all the scaling parameters, two
dimensions are critical, i.e., the channel length (Lch) and the contact length (Lc).
Understanding the scaling behavior of both Lch and Lc are crucial for the integration
of SWNT FETs. The IBM group fabricated a series of transistors with channel
length scaled from 3 mm to 15 nm on the same SWNT, and demonstrated that these

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nanotube transistors maintained their performance without the presence of short-

channel effects [29]. When Lch is aggressively scaled, the on state performance
improves significantly, potentially leading to a high-speed circuit. The SEM image,
transfer (ID–VLBG), and output (ID–VDS) characteristics of these devices are shown
in Fig. 6a–c. The 15-nm device has the shortest channel length and highest room-
temperature conductance (0.7 G0) and transconductance (40 lS). In a separate
work, the same group further pushed the Lch scaling, and demonstrated a sub-10-nm
SWNT transistor [30]. The transistor outperforms the best competing silicon devices
with more than four times the diameter-normalized current density (2.41 mA/lm) at
a low operating voltage of 0.5 V. In terms of contact length scaling, for large
contact lengths ([100 nm), some studies have suggested that sharp needle-like
contacts are ideal, since transport between a metal and a nanotube occurs only at the
contact edge [95, 96]. On the contrary, for contact length less than 100 nm, the IBM
group applied the same strategy as in the Lch scaling study, i.e., with multiple
devices located on the same nanotube, to study the contact length scaling from 20 to
100 nm, and showed that Lc scaling affects the on state far more dramatically than
the off state of a device [29]. Figure 6d–f shows the contact length dependence of
the SWNT FET performance. To tackle the short contact length scaling effects, Cao
et al. developed an end-bonded contact scheme that allows scaling the contacts to
10 nm and beyond without increasing contact resistance [31]. The molybdenum film
acts as the source and drain for the FETs and reacts with the CNT to form a carbide
contact. Figure 6g shows the schematic of such carbide contact. Figure 6h shows a
false-colored SEM image of a set of transistors with such carbide contact, and
Fig. 6i shows the corresponding transfer characteristics. The molybdenum nanotube
end-bonded contact exhibited no Schottky barrier. Using the bonded contact
method, a p-type SWNT transistor with sub-10-nanometer contact length was also
fabricated, showing high performance of channel resistance below 36 kX and on
current above 15 lA per tube. Recently, Qiu et al. at Peking University further
scaled the gate length of single SWNT FETs down to 5–10 nm [97]. Figure 6j, k
shows the TEM images of the cross-sections of p-type and n-type transistors with a
gate length of 10 nm, respectively. The transfer characteristics of the p-type and
n-type transistors are shown in Fig. 6l. The p-type and n-type transistors exhibited
nearly symmetric performance. In addition, the on-state current was as high as
17.5 lA for the p-type FET and 20 lA for the n-type FET at a relatively low bias of
0.4 V, demonstrating the potential of the SWNT FETs for low-power applications.

3.2 N-Type SWNT Transistors

In logic circuit applications, CMOS operation is highly preferable for the sake of
various advantages including rail-to-rail swing, large noise immunity, and small
static power consumption. Given the fact that SWNT transistors typically exhibit
p-type behavior due to oxygen exposure [98], it is equally important to reliably
convert nanotube devices into n types. One approach is to use low work function
(UM) metals as the contacts, in a way the Fermi level of the electrodes can be
aligned with the conduction band edge of SWNTs, giving ohmic contacts for
electron carrier transport. A variety of low work function metals have been

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Fig. 6 Single nanotube transistor. a–c Effects of channel length scaling on nanotube transistor
performance a SEM image of a set of transistors on the same nanotube with different channel lengths.
b Subthreshold ID–VLBG curve from devices with channel lengths of *15 nm, 300 nm, and 3 mm.
c Output ID–VDS characteristics of devices in (b). d–f Effects of contact length scaling on nanotube
transistor performance. d SEM image of a set of transistors on the same nanotube with different contact
lengths. e Subthreshold ID–VLBG curve from devices with contact lengths of 100, 70, 50, 30, and 20 nm.
Inset shows the dependence of gm on Lc. f Output ID–VDS characteristics of devices in (e). Adapted with
permission from Ref. [29]. Copyright (2010) Nature Publishing Group. (g–i) Mo end-contacted SWNT
transistors. g Schematics showing the SWNT is attached to the bulk Mo electrode through carbide bonds
while the C atoms from the originally covered portion of the SWNT uniformly diffuse out into the Mo
electrode. h False-colored SEM images of a set of transistors fabricated on the same nanotube, with Lc
ranging from 20 to 300 nm. Scale bar 400 nm. i Collection of transfer characteristics from a set of Mo
end-contacted single-nanotube transistors with different Lc plotted in both linear (lines, left axis) and
logarithmic (symbols, right axis) scales with applied VDS of -0.5 V. Adapted with permission from Ref.
[31]. Copyright (2015) American Association for the Advancement of Science. j, k TEM images showing
the cross-sections of a p-type FET and n-type FET; gate length 10 nm, channel length 20 nm. l Transfer
characteristics (drain current Ids versus gate voltage Vgs) of typical CMOS FETs fabricated on a single
SWNT with a diameter of 1.3 nm at a drain bias Vds = ±0.4 V. The solid blue and olive curves represent
SWNT p-type and n-type FETs, respectively. j–l Adapted with permission from Ref. [97]. Copyright
(2017) American Association for the Advancement of Science

investigated, including gadolinium [36], yttrium [37], scandium [38], and erbium
[39]. Ding et al. used yttrium as the source and drain contacts for top-gate FETs

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with a single SWNT as the channel, and demonstrated n-type transistors with
subthreshold swing (SS) of 73 mV/dec and drain-induced barrier lowering (DIBL)
of 105 mV/V, as shown in Fig. 7a, b [37]. Shahrjerdi et al. performed a thorough
experimental study of n-type contacts for SWNT FETs based on erbium (Er,

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b Fig. 7 N-type transistors from Ref. [37, 39–41, 43]. Schematic (a, c, e, g, i) and characteristics (b, d, f, h,
j) of low work function metal, low work function metal aligned SWNT array, gate dielectric doping, and
chemical doping N-type transistors, respectively. a, b Adapted with permission from Ref. [37]. Copyright
(2009) American Chemical Society. c, d Adapted with permission from Ref. [39]. Copyright (2013)
American Chemical Society. e, f Adapted with permission from Ref. [40]. Copyright (2011) American
Chemical Society. g, h Adapted with permission from Ref. [41]. Copyright (2014) American Chemical
Society. i, j Adapted with permission from Ref. [43]. Copyright (2016) American Chemical Society

UM = 3.0 eV), lanthanum (La, UM = 3.5 eV), and yttrium (Y, UM = 3.1 eV) [39].
Figure 7c shows the schematic of the bottom gate SWNT n-type FET (n-FET) and
the corresponding high-resolution TEM image, which gives details of the Er contact
with the oxidation layer and the Al encapsulation layer. The results suggest that by
employing Er contacts, significant improvements in device characteristics can be
achieved. Figure 7d shows the effect of partial oxidation of Er (left) and Y (right)
electrodes on device performance. Due to rapid oxidation, the device performance
degrades with increasing contact layer thickness. Controlling process parameters
such as low base pressure and high deposition rate can help mitigate the oxidation
effects. The electrical characteristics of n-FET devices with Er electrodes were
shown to remain stable upon storage in air by employing a hydrophobic polymer
deposited at 150°C. It is worthwhile to note that the technique of applying low work
function metal to achieve n-type transistors can be applied to both a single nanotube
and also an array of aligned tubes. A small work function metal gadolinium (Gd)
with a work function of *3.1 eV has been used by Wang et al. in aligned nanotube
transistors [40]. Figure 7e shows the schematic of Gd used as n-type contact in air-
stable, n-type, aligned nanotube transistors. The transistor transfer characteristics
are shown in Fig. 7f, and the linear output characteristics indicate good ohmic
contacts between SWNTs and the Gd contacts.
Another approach is to take advantage of the gate dielectric to give rise to n-type
doping in SWNTs. Liyanage et al. applied low work function metal oxides (Y2O3)
as the gate dielectrics to SWNT FETs [41]. This novel and very-large-scale-
integrated (VLSI)-compatible doping technique enables wafer-scale fabrication of
high performance n-type SWNT transistors. The partially oxidized yttrium gives
rise to n-type doping in SWNTs. Figure 7g shows the schematic of the Y2O3 gate
dielectric SWNT FETs. From Fig. 7h, we can see the transistors demonstrate good
n-type behavior with high performance of a large on current, high on/off ratio, and
small subthreshold voltage swing.
The third approach is to apply chemical and electrostatic doping methods to
provide excess electrons to promote electron tunneling and conduction [42].
Recently, Geier et al. reported the controlled n-type doping of SWNT thin-film
transistors with a solution-processed pentamethylrhodocene dimer [(RhCp*Cp)2]
[43]. Its molecular-scale thickness enables large-area arrays of top-gated, high-
yield, n-type SWNT transistors, as shown in Fig. 7i. Figure 7j shows the transfer
curves for the top-gated SWNT TFTs for different exposure times, which shows the
conversion of the top-gated SWNT TFTs into n-types under 10-min dopant
exposure. The air-stable n-type dopant study will thus facilitate ongoing efforts to
realize high-density SWNT integrated circuits.

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3.3 Transistors and Digital Circuits Based on Aligned SWNTs

In spite of the great potential of SWNTs demonstrated by single SWNT transistors,

in terms of commercial applications, the device-to-device variation can undermine
their benefits. Different factors can contribute to the variations, such as chirality,
oxygen adsorption, and defects. Multiple aligned SWNTs within the same device
channel can average out the SWNT properties and greatly reduce device variation.
Another advantage of aligned nanotube arrays is the simultaneous contribution to
the device current by multiple SWNTs, which can multiply the device conductance.
CVD-grown SWNTs on crystalline substrates like quartz and sapphire can yield
highly aligned nanotubes. Using the massive aligned nanotube arrays grown by
CVD on sapphire, our group reported a high yield and registration-free nanotube-
on-insulator approach, analogous to the silicon-on-insulator approach adopted by
the semiconductor industry [32]. To overcome the drawbacks of small sample size,
large millimeter-scale channel length, and unavailability of controlled doping, our
group reported a full-wafer scale CMOS analogous fabrication with SWNT
transistors feature size down to 0.5 lm [33]. After nanotube synthesis and transfer,
the SWNT transistors employ the top-gate structure, and the metallic nanotubes
inside the channel regions are removed by electrical breakdown to improve the
current on/off ratio. P-type SWNT transistors are converted to n-type by potassium
and electrostatic doping. Combining all the advantages, CMOS inverters, NAND,
and NOR gates based on aligned SWNT array transistors are demonstrated in
Fig. 8a. To demonstrate the feasibility of SWNT FET circuits at a highly scaled

Fig. 8 Transistors and digital circuits based on aligned nanotubes. a Optical images of SWNT transistors
and circuits built on a 4-inch Si/SiO2 wafer: 1 back-gated transistor; 2 top-gated transistor; 3 CMOS
inverter; 4 NOR logic gate; 5 NAND logic gate. Adapted with permission from Ref. [33]. Copyright
(2009) American Chemical Society. b SEM of an integrated SWNT FET IR sensor and interface circuit
(left), along with processing steps (right). Adapted with permission from Ref. [34]. Copyright (2014)
American Chemical Society. c SEM of the SWNT computer. Adapted with permission from Ref. [35].
Copyright (2013) American Association for the Advancement of Science

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technological node, Shulaker et al. at Stanford reported the first VLSI-compatible

approach for SWNT FETs with devices as small as sub-20-nm channel lengths [34].
They demonstrated inverters functioning at 1 MHz and a fully integrated SWNT
FET infrared (IR) light sensor and interface circuit at 32-nm channel length. The
SEM images of the integrated SWNT FET IR sensor and interface circuit are shown
in Fig. 8b. This demonstration is one step closer to highly scaled SWNT FET
circuits as a digital VLSI technology.
In terms of the circuit complexity, the first SWNT computer has been
demonstrated by the same Stanford group as an important milestone in the practical
application of SWNT digital electronics [35]. The SWNT computer runs an
operating system and achieves multitasking of counting and integer sorting
simultaneously. The SEM of the computer comprising of instruction fetch, data
fetch, arithmetic operation, and write back system is shown in Fig. 8c. Despite the
fact that the first computer still has many aspects to improve, such as the PMOS-
only logic and the low clock speed, the experimental demonstration of a SWNT
computer is a breakthrough in the next generation of SWNT-based, highly energy-
efficient electronic systems.

3.4 Large-scale Assembly of SWNTs

The materials challenges in the alignment and placement of SWNTs, as well as in

the removal of metallic SWNTs, have prevented SWNTs from fully achieving their
exceptional electronic properties. Joo et al. reported a novel yet simple method to
deposit aligned semiconducting SWNTs on substrates via a dose-controlled, floating
evaporative self-assembly (FESA) method [99]. The process starts from sorted
SWNT solution with semiconducting purity of more than 99.9%. When dropping
the solvent with semiconducting SWNT solution at a certain dose onto the water
surface, the dose-covered air/water interface will spread out and reach the substrate.
The solvent of the SWNT solution will evaporate, and SWNTs will stay on the
substrate and align with the air/water interface. Repeatedly applying the solution
dose and pulling out the receiving substrate at optimized speeds can give stripes of
aligned nanotubes on the substrate. The FESA method can give high-density,
aligned SWNTs with high semiconducting purity and few defects. The FESA steps
are illustrated in Fig. 9a. The density of the assembled aligned tubes can be as high
as 40–50 tubes/lm. Based on the FESA platform, Grady et al. studied superior
back-gated FET performance fabricated from these SWNT arrays, and achieved
high on-conductance and a high on/off ratio simultaneously [100]. The schematic of
the gate structure and the SEM image of the device channel area are shown in
Fig. 9b, c, respectively. For a channel length (Lch) of 240 nm, the on-conductance
(Gon) per width and an on/off ratio (Gon/Goff) are as high as 261 lS/lm and
2 9 105, respectively (Fig. 9d), and for an Lch of 1 lm, the corresponding
performances are 116 lS/lm and 1 9 106, respectively (Fig. 9e).

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Fig. 9 Large-scale assembling of CNTs. a Schematic illustration of the iterative (FESA) process used to
fabricate aligned nanotubes-SWNTs driven by the spreading and evaporation of controlled doses of
organic solvent at the air/water interface. Adapted with permission from Ref. [99]. Copyright (2014)
American Chemical Society. b Schematic of SWNT FET architecture. c Top–down SEM image of
SWNT spanning Pd electrodes of a 240-nm Lch SWNT FET (scale bar 100 nm). d, e Transfer
characteristics at VDS = -1 V (black) and -0.1 V (red) for a champion SWNT FET of Lch = 240 nm
and Wch = 3.8 lm in (d) and Lch = 1070 nm and Wch = 3.8 lm in (e). Adapted with permission from
Ref. [100]. Copyright (2014) American Chemical Society

3.5 3D Integration and Novel Structures of SWNT Transistors

In order to increase the transistor density and/or improve the SWNT FET
performance, different integration methods and gate structures have been proposed
and demonstrated. Wei et al. reported a scalable integration process for monolithic
3D integrated circuits (3D ICs) using SWNT FETs [44]. In their approach, SWNT
FETs with high ION/IOFF can be flexibly placed on arbitrary layers of monolithic 3D
ICs, and connected using conventional vias to build fully complementary
monolithic 3D logic gates and multi-stage logic circuits. The monolithic 3D logic
gates can operate correctly over a range of supply voltages from 3 to 0.2 V, which
shows the robustness of the method.
Constructing ICs along a single SWNT is another novel idea to minimize the
effect of variation in different nanotubes and shows SWNT FETs can be used as a
building block for electronics [101–104]. In 2001, Derycke et al. reported both p-
and n-type transistors on the same nanotube for the first complementary nanotube-
based inverter logic gate [102]. In 2006, Chen et al. demonstrated a CMOS 5-stage
ring oscillator built entirely on a single 18-lm-long SWNT [103]. Later in 2014, Pei
et al. reported an innovative modularized construction of ICs on individual CNTs
[104]. In their work, pass-transistor-logic style 8-transistor (8-T) units were built
and used as multifunctional function generators. The units have good tolerance to
inhomogeneity in the CNTs and were used as building blocks for general ICs. An
8-bits BUS system used to transfer data between different systems in a computer
was constructed.
Other possible novel SWNT gate structures with potential performance
advantages at the circuit level including FinFETs [45] and gates all around [46]

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have also been analyzed and studied. Furthermore, combining SWNT FETs with
other semiconductors such as silicon to achieve CMOS integration [47] shows the
promising future for high-performance digital logic applications.

4 SWNT Macroelectronics

4.1 Fabricated SWNT TFTs

The use of SWNT networks present a highly promising path for the realization of
high-performance TFTs for macro and flexible electronic applications. Using
SWNT random networks for TFTs has many significant advantages: SWNT thin
films are mechanically flexible, optically transparent, and can be prepared using
solution-based room-temperature processing, all of which cannot be provided by
amorphous and polysilicon technologies [48–61]. The most common assembly
methods for random nanotube networks including direct CVD growth [48, 62], dry
filtration [54], evaporation assembly [63], spin coating [64–66], drop coating
[56, 67–71], and printing [49, 50, 52, 72, 73].

4.1.1 Gaseous Phase-Based SWNT TFTs

As-grown nanotube networks usually contain both metallic and semiconducting

nanotubes [105, 106], which leads to a trade-off between charge carrier mobility
(which increases with greater metallic tube content) and on/off ratio (which
decreases with greater metallic tube content). Many research efforts have been
devoted to the successful realization of high-performance FETs comprised of
semiconducting-enriched SWNT random networks based on CVD synthesis
[48, 53, 90, 107]. Medium-scale SWNT thin-film integrated circuits on flexible
substrates have been demonstrated by Rogers’ group [48]. For this method, growth
substrates decorated with metal catalysts (Fe particles or ferritin) were placed in a
furnace at elevated temperatures ([800 °C). Then, a precursor containing carbon
feedstock, such as methane, ethylene, isopropyl alcohol, etc., was introduced into
the growth chamber for the dissociation of hydrocarbon molecule from the
feedstock. The hydrocarbon molecules then facilitated the growth of the CNTs on
the catalysts [48, 90]. Although the flexible SWNT TFTs and circuits shows
promising electrical performance, the existence of metallic nanotubes degrades the
on/off ratio of the devices.
Ohno’s group introduced a floating catalyst CVD technique with monoxide (CO)
as the carbon source, and achieved high-performance flexible nanotube TFTs and
D-flip-flop circuits [54]. In Fig. 10a, the nanotubes grown by plasma-enhanced
CVD were collected through a simple gas phase filtration process [53, 54, 108]. The
density of the nanotubes can be easily controlled by the collection time. The
SWNTs were subsequently transferred onto the device substrate by dissolving the
filter in acetone. The transferred CNT film has a network morphology consisting of
rather straight and long nanotubes, *10 lm in length, as shown in the SEM images
in Fig. 10b. The advantage of utilizing as-grown SWNTs directly for fabrication of

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devices is that there are more Y-type junctions between the nanotubes than the
X-junctions, which can result in a higher mobility of the transistors [54]. Figure 10c
shows the transfer and output characteristics of a bottom-gate TFT device. The
device showed p-type characteristics with a high on/off ratio (6 9 106) and an

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b Fig. 10 a Schematic diagram showing CNT growth, collection by filter, transfer, and patterning. b SEM
images of a CNT network on a Si/SiO2 substrate after transfer. c Transfer and output characteristics of
fabricated bottom-gate TFT based on the nanotube network shown in (b). a–c Adapted with permission
from Ref. [54]. Copyright (2011) Nature Publishing Group. d Schematic diagram showing the
configuration of a CNT TFT in which the CNT network is deposited using separated semiconducting
nanotube solution. e SEM images of an SWNT random network captured at different regions of a wafer
after SWNT deposition. f Output characteristics of an SWNT TFT. g Statistical study of on-state current
density and threshold voltage of as-fabricated SWNT TFTs. d–g Adapted with permission from Ref. [56].
Copyright (2009) American Chemical Society

effective device mobility of 35 cm2 V-1 s-1. The transfer process of the CVD
grown SWNTs is carried out at room temperature, which is desirable for the
fabrication of flexible electronics.

4.1.2 Solution-Based SWNT TFTs

In addition to CVD-based SWNT random network electronics, there are many

approaches in the area of solution-based SWNT electronics [55–57, 68, 70, 71, 109].
About one third of the as-grown SWNTs are metallic nanotubes [110], which can
cause significant leakage of current when the transistors are in the off state and
result in a low on/off ratio [111–114]. Thus, the metallic nanotubes should be
selectively removed, and high-purity semiconducting nanotubes are desired for
high-performance transistors. Separation between metallic and semiconducting
tubes, and even separation of single chirality nanotubes have been achieved by a
variety of methods, such as density gradient ultracentrifugation (DGU) [110, 113],
gel chromatography [115], and DNA-based chromatographic purification [116].
SWNT networks can be obtained by spin coating/dropping the nanotube solution
onto a spinning substrate [64]. The drawback with this method is scalability because
the deposited SWNTs often align along different orientations depending on the
location on the substrate, which leads to wafer-scale fabrication with low
uniformity. Drop coating is found to be a more promising solution-based SWNT
assembly method for large-scale applications of nanotube TFTs. In this method, the
substrates are first functionalized with amine-containing molecules, which are
effective adhesives for SWNTs. By simply immersing the substrate into the
nanotube solution, highly uniform nanotube networks can be obtained throughout
the wafer, enabling the fabrication of nanotube TFTs with high yield and small
device-to-device variation [56, 68, 70, 71].
Many research groups have systematically studied electrical performance of
SWNT TFTs based on the high-purity semiconducting SWNT solution
[7, 56, 63, 68, 79, 109]. The device characteristics of SWNT TFTs are heavily
dependent on the nanotube density [69, 70] and channel length [71, 117]. SWNT
TFTs with mobility greater than 100 cm2 V-1 s-1 have been reported [117–119],
which exceed the mobility of amorphous and organic FETs by at least two orders of
magnitude. The fact that such high-mobility SWNT TFTs can be fabricated using a
facile solution-based process and processed at room temperature makes the
nanotube TFTs ideal for a wide range of applications.

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We are among the first few research groups to demonstrate SWNT TFTs
comprised of an enriched semiconducting SWNT random network. Figure 10d
illustrates a common back-gated TFT based on a random network of separated
SWNT solution [56]. The SWNT solution was uniformly deposited onto the device
substrate by first functionalizing with aminopropyltriethoxy to terminate the surface
of the substrate with a layer of amino groups, which enhances the attraction between
the SWNTs and the surface [65]. As can be observed in Fig. 10e, the SWNT thin
film can be deposited invariantly over the entire surface of a 3-inch Si/SiO2 wafer,
as shown by the SEM images captured at different regions of the wafer after SWNT
deposition. This proves that the deposition process is scalable, and can be used in
industrial-scale fabrication. The geometry of the channel of the transistors can be
defined by standard photolithography, followed by O2 plasma etching of the SWNT
film in the region outside the channel. This technique eliminates the issue of
assembly of the nanotubes. The transistors fabricated with the 98% enriched SWNT
solution exhibited ideal p-type behavior with mobility as high as 52 cm2 V-1 s-1,
while maintaining a current on/off ratio of 104. Although the mobility of the devices
is not as high as that exhibited by silicon transistors, it is still an invaluable thin film
material for applications such as drivers for display, or flexible electronics [120].
The output characteristic of the SWNT TFTs is exhibited in Fig. 10f. As can be
observed in the plot, the output curves can be fully saturated. The uniformity of the
devices is illustrated in Fig. 10g. The normalized on current (Ion/W) and threshold
voltage (Vth) of 10 SWNT TFTs were delineated in the figure. The results provided
evidence for the applicability to implement the separated CNT thin films in large-
scale fabrication processes.

4.2 Printed SWNT TFTs

SWNTs, which are intrinsically printable at room temperature, show its great
advantage over amorphous silicon and polysilicon for printed electronics [49, 83]
Compared with other printable organic materials, SWNTs have much higher
mobility and are chemically stable in ambient [58, 86, 121]. Thanks to the great
progress made in SWNT separation [122, 123], semiconducting SWNT-enriched
solution has been realized, which leads to feasibility of printing high-performance
SWNT TFTs for macro and display electronic applications [49, 84–89].
To realize fully printed high-performance SWNT TFTs, selection of materials for
electrodes and gate dielectrics is critical. In terms of electrodes, silver and gold
based nanoparticle inks are mostly selected for their system because of their high
conductivity and the formation of Ohmic contact between electrodes and SWNTs
[84, 124, 125]. Although nanomaterials such as metallic SWNTs have been used as
electrodes [126], the performance was rather moderate and therefore hard to be
applied for macro and display electronics. For printing gate dielectrics, mixtures
composed of high-j metal oxide nanoparticles and organic binders are commonly
used to achieve relatively high capacitance [86, 125], which can reduce the
operation voltage of printed TFTs. Another group of dielectric materials is
electrolyte, which have been reported by Frisbie and Hersam’s groups [50, 88]. The
most important advantage of employing electrolyte as the gate dielectric is the high

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capacitance regardless of its rather large physical thickness. As a result, the

performance of such printed electrolyte-gated SWNT TFT is superior in terms of
on-state current density, on–off ratio and low operation voltage [127].
Multiple printing technologies reported for fabricating SWNT TFTs can be
mainly divided into two groups [86]. The first one is of high registration accuracy
represented by aerosol-jet printing and inkjet printing. The second one is of high
scalability and throughput represented by gravure printing and flexographic
printing. On one hand, for printing SWNTs as channel materials, ink-jet and
aerosol-jet printing are main-stream technologies using relatively low viscosity inks
to pattern an ultrathin and uniform film. On the other hand, ink-jet printing, aerosol-
jet printing, screen printing, gravure printing and flexographic printing have all been
employed for patterning gate dielectric and electrodes to achieve fully printed
SWNT TFTs. Up until now, the fully-printed high-performance SWNT TFT has
been used for macro, display, and sensor electronics. Our group made great efforts
to developing fully printed SWNT TFTs for OLED driving using ink-jet printing
(Fig. 11a) and screen printing (Fig. 11b) [49, 86]. Javey and Cho’s groups
pioneered in gravure printed SWNT electronics (Fig. 11c), realizing D flip-flop
[52], full adder [51], and fully printed backplane for electronic skin [76]. Hersam’s
group reported high-performance printed ring oscillators using aerosol-jet printing
[85, 128, 129]. Ohno’s group made great efforts on developing fully flexographic
printed SWNT TFTs with CVD grown nanotubes (Fig. 11d) [130]. Overall, such

Fig. 11 a Schematic diagram showing the process of fully ink-jet printed SWNT TFTs 1 printing first
silver electrodes. 2 Printing SWNT network. 3 Printing second layer of silver electrodes. 4 Printing ionic
gel as dielectric material. Adapted with permission from Ref. [49]. Copyright (2011) American Chemical
Society. b Schematic diagram of screen printer and an optical image of screen printed SWNT TFT array
on a PET substrate. Adapted with permission from Ref. [86]. Copyright (2014) American Chemical
Society. c Schematic diagram outlining gravure printing process of SWNT TFTs and images of printed
TFT and nanotube network on a PET substrate. Adapted with permission from Ref. [125]. Copyright
(2013) American Chemical Society. d Schematic diagram of flexographic printing and an optical image
of flexographic printed CNT TFT electronics on a PET substrate. Adapted with permission from Ref.
[130]. Copyright (2011) Japan Society of Applied Physics

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cost-effective and solution-based printing technologies have been attracting more

and more research interest and are promising for practical applications.

4.3 Applications Based on SWNT TFTs

SWNT TFTs show great potential in a wide range of applications, ranging from
digital circuits, active-matrix backplanes for display electronics and sensors, to
flexible electronics. Over the past years, tremendous efforts have been devoted into
SWNT TFT research, trying to make it a real technology. Here, we will review the
potential applications of SWNT TFTs, including (1) digital circuits, (2) active-
matrix backplanes for display electronics and sensors, and (3) flexible electronics.

4.3.1 Digital Circuits

The extremely high intrinsic carrier mobility and current-carrying capacity make
SWNTs a promising channel material for next-generation digital circuits. Many
groups have made significant progress by successfully fabricating integrated circuits
based on p-type SWNT TFT platforms [48, 53, 54, 68, 71, 131]. In 2008, Cao et al.
successfully demonstrated the first medium-scale SWNT-based integrated digital
circuits, a four-bit row decoder composing of 88 SWNT TFTs, on polyimide
substrates [48]. Random SWNT networks were initially synthesized by CVD, and
then transferred to polyimide substrate as the channel materials. Figure 12a shows
the optical image of a flexible SWNT integrated circuit chip bonded to a curved
surface and high-magnification photographic image of the fabricated four-bit row
decoder consisting of 88 SWNT transistors. Moreover, Sun et al. successfully
realized the fabrication of SWNT-based TFTs and logic circuits on flexible
substrates, such as 21-stage ring oscillator and master–slave delay flip-flops, using a
floating-catalyst CVD SWNT deposition method followed by gas phase filtration
and a transfer process [54]. Based on the platform of gas phase-synthesized
nanotube networks, they further demonstrated the first all-carbon XOR gates and
1-bit static random access memory (SRAM) [53]. Later on, instead of using CVD-
synthesized SWNTs, Wang et al. used separated high-purity semiconducting-
enriched SWNTs as the channel material for high-performance SWNT TFTs and
demonstrated separated nanotube-based integrated logic gates, including an
inverter, NAND, and NOR gates, serving as a good platform to bypass the issue
of the coexistence of both metallic and semiconducting nanotubes in the as-
synthesized SWNTs [68]. After that, solution-processed semiconducting SWNT
thin films have drawn much more attention from researchers, because solution-
processed separated SWNTs offer high electrical performance, good mechanical
flexibility, relatively low cost, and ambient compatibility simultaneously. Wang
et al. successfully demonstrated high-performance logic gates, including inverters,
NAND, NOR gates, with superior bending stabilities [71]. A recent breakthrough
was made by Chen et al. by realizing a 4-bit adder which consists of 140 p-type
SWNT TFTs and a 2-bit multiplier for the first time [77]. Thanks to the high
uniformity and desirable threshold voltage of the CNT TFTs, the integrated circuits
based on these TFTs can be operated by a small voltage down to 2 V.

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Fig. 12 a Optical image of a flexible SWNT integrated circuit chip bonded to a curved surface and high-
magnification photographic image of the decoder consisting of 88 CNT transistors. Adapted with
permission from Ref. [48]. Copyright (2008) Nature Publishing Group. b Optical micrograph, read
margin measurement, folded read margin measurements, and hold operation of a fabricated SWNT
CMOS SRAM cell. Adapted with permission from Ref. [81]. Copyright (2015) Nature Publishing Group.
c Hybrid integration of IGZO TFT and SWNT TFT for a CMOS inverter. Adapted with permission from
Ref. [82]. Copyright (2014) Nature Publishing Group

Large hysteresis, a commonly observed phenomenon in the transfer character-

istics of SWNT TFTs, is highly undesired in the operation of transistors and
integrated logic gates, because hysteresis often results in the shift of threshold
voltage as the voltage sweeping direction and range changes. Multiple factors can
cause hysteresis in a SWNT-based TFT, including interface-trapped charges and
trapped charges induced by the absorption of water molecules inside the channel
[78]. Therefore, hysteresis-free nanotube-based TFTs are highly desired for the
stable operations of SWNT-based TFTs and digital circuits. Ha et al. developed a
promising approach of using fluorocarbon polymer as the encapsulation layer for
hysteresis-free SWNT devices, which showed great device stability in both air and
water [78]. Thanks to the high hydrophobicity of this Teflon-like polymer, the water
molecules absorbed in the nanotubes can be effectively removed, which yields
hysteresis-free SWNT TFTs. Recently, Chen et al. discovered an alternative
approach for hysteresis-free SWNT devices by using Y2O3 thin film as the gate
dielectric layer, which was oxidized from e-beam-evaporated yttrium film [77].
Their results showed that Y2O3 can offer very high gate efficiency and high

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uniformity for SWNT-based TFTs, which paves the way for large-scale integration
of SWNT-based TFTs.
CMOS integrated circuits have many advantages, especially their low static
power consumption. Over the past two decades, many groups including our group
have devoted a lot of efforts into trying to convert p-type SWNT TFTs into air-
stable n-type TFTs aiming for integrated CMOS logic gates. Here, we will review
some recent progress in CMOS integrated circuits consisting of n-type and p-type
SWNT TFTs as the NMOS and PMOS, respectively. Ryu et al. reported a fully
integrated CMOS inverter and NAND and NOR gates by using chemical doping to
convert p-type aligned nanotube transistors to n-types [33]. Later on, Zhang et al.
developed a new approach of using a thin layer of high-j oxide passivation layer,
deposited by atomic layer deposition, to convert separated SWNT TFTs from p-type
to air-stable n-type [79]. Interestingly, the converted n-type transistors and the
p-type transistors show symmetric electrical performance, regarding device
mobility, on-state current, and on/off ratio. They further demonstrated a CMOS
inverter with rail-to-rail output, large noise margin, and symmetric input/output
behavior. Recently, Ha et al. reported a novel strategy of achieving air-
stable n-doping SWNTs with SiNx thin films deposited by plasma-enhanced
chemical vapor deposition [80]. The n-type nanotube transistors are highly air-
stable and show very good uniformity over large areas, which is an important factor
for integrated circuit applications. In 2015, a great breakthrough was achieved by
Geier et al. whom demonstrated the first solution-processed SWNT thin film-
complementary SRAM [81] (Fig. 12b). The uniform and stable electronic perfor-
mance of the complementary p-type and n-type SWNT TFTs is attributed to the
well-controlled adsorbed atmospheric dopants and robust encapsulation layers.
Recently, Yang et al. reported CMOS ICs by using Sc or Pd as the source/drain
contacts to selectively inject carriers into the CNT network channels for NMOS and
PMOS, respectively [132]. They demonstrated a 4-bit full adders consisting of 132
CMOS TFTs with 100% yield, showing the potential of medium-scale CNT
network film-based ICs.
Considering metal oxide semiconductors have gradually emerged as a mature
technology platform for n-type TFTs, Chen et al. demonstrated the first large-scale
hybrid integration of p-type CNT and n-type indium–gallium–zinc–oxide thin-film
transistors to realize 501-stage ring oscillators, consisting of more than 1000
transistors, on both rigid and flexible substrates (Fig. 12c) [82]. In this hybrid
integration approach, the strength of the p-type nanotube and n-type indium–
gallium–zinc-oxide are successfully combined together to achieve high uniformity
and high yield.

4.3.2 Active-Matrix Backplanes for Display Electronics and Sensors

Separated semiconducting-enriched SWNT thin films possess great potential for

TFTs and active-matrix backplanes for display electronics and sensors, due to their
high semiconducting purity, high mobility, and room-temperature processing
compatibility. As early as 2009, Wang et al. made the first conceptual demonstration
of an organic light-emitting diode (OLED) control circuit with a nanotube TFT,

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with the output light intensity exceeding 104, which paves the way for using
nanotube TFTs for display electronics [56]. Active-matrix organic light-emitting
diode (AMOLED) display exhibits great potential as a competitive candidate for
next-generation display technologies due to its high light efficiency, light weight,
high flexibility, and low-temperature processing compatibility. Later, Zhang et al.
further successfully demonstrated monolithically integrated AMOLED display
elements, consisting of 500 pixels driven by 1000 nanotube TFTs [57]. The optical
image of an AMOLED substrate containing 7 AMOLED elements, each with
20 9 25 pixels, is shown in Fig. 13a. Figure 13b is a photograph showing the pixels
on an integrated AMOLED. The electrical characteristics of the OLED controlled
by a single pixel circuit is shown in Fig. 13c. Figure 13d shows the plot of the
current through the OLED (IOLED; red line) and OLED light intensity (green line)
versus VDATA with VDD = 8 V. This approach may serve as a critical foundation for
using separated CNT thin-film transistors for display applications in the future.
Later on, inkjet-printed [49] and screen-printed [86] OLED control circuits were
demonstrated, showing a low-cost approach to realize OLED driving capability.
Recently, Zou et al. reported first CVD-grown SWNT network-based TFT driver

Fig. 13 AMOLED using SWNT TFTs. a Optical image of an AMOLED substrate containing 7
AMOLED elements, each with 20 9 25 pixels. b Photograph showing the pixels on an integrated
AMOLED. c Characteristics of the OLED controlled by a single pixel circuit. d Plot of the current
through the OLED (IOLED; red line) and OLED light intensity (green line) versus VDATA with
VDD = 8 V. Adapted with permission from Ref. [57]. Copyright (2011) American Chemical Society

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circuits for both static and dynamic 6 9 6 AMOLED displays, which further proved
the suitability and capability of SWNT-TFTs for future OLED applications [74].
Additional great progress in this field was made by Wang et al. by demonstrating
the first user-interactive electronic skin which can give simultaneously spatial-
pressure mapping and visual response through a built-in AMOLED controlled by an
SWNT-TFT-based active matrix (Fig. 14) [55]. In this system, the OLED arrays can
be turned on locally at the location where there is pressure applied, and the intensity

Fig. 14 User-interactive electronic skin based on SWNT TFTs. a, b Schematic diagrams showing the
configuration of a pixel, consisting of a nanotube TFT, an OLED, and a pressure sensor (PSR) integrated
vertically on a polyimide substrate. c Circuit schematic of the e-skin matrix. d Photograph of a fabricated
device (16 9 16 pixels). e Green, blue, and red color interactive e-skins are used to spatially map and
display the pressure applied with C- (left), A- (center), and L- (right) shaped PDMS slabs, respectively.
Adapted with permission from Ref. [55]. Copyright (2013) Nature Publishing Group

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of the emission light can be used to quantify the pressure applied to the surface. This
work represents a successful large-scale demonstration of three different electronic
components, including nanotube TFTs, pressure sensors, and OLED arrays, which
are monolithically integrated over large areas on plastic substrates. This electronic
skin has great potential to be used for a range of applications, such as medical
monitoring devices, interactive input/output devices, etc.
As early as 2011, Takahashi et al. reported fabrication of SWNT thin-film-based
12 9 8 active-matrix backplanes for pressure mapping with a pressure sensitive
rubber as the active sensor element [70]. After that, they further demonstrated a
flexible nanotube active-matrix backplane for visible light and X-ray imagers [75].
Recently, they realized large-area pressure mapping by the large-scale integration of
a printed SWNT active-matrix backplane with tactile sensor arrays, indicating a
scalable, low-cost approach towards electronic skin applications using CNT TFTs
[76].

4.3.3 Flexible Electronics

Recently, flexible electronics have been widely explored for new applications which
are impossible to be realized using the conventional rigid substrates. Due to the
intrinsic flexibility of SWNTs, nanotube TFTs have attracted many people’s
attention and emerged as a promising technology platform for flexible electronics.
To achieve good flexibility, a very thin layer of high-quality dielectric on plastic
substrate is highly desired. Here, we will review some recent progress achieved in
nanotube-TFT-based flexible electronics.
As early as 2006, Cao et al. reported mechanically flexible, optically transparent
‘‘all-tube’’ TFT on flexible substrates fabricated using layer-by-layer transfer
printing of CVD-grown SWNT networks as both electrodes and channel materials
[133]. Elastomeric dielectrics and flexible substrates were used to achieve high
flexibility. In 2012, Wang et al. demonstrated extremely bendable, high-perfor-
mance integrated inverters, NAND, and NOR logic gates, analog, and radio
frequency applications using semiconducting-enriched SWNTs [71]. Later, Lau
et al. further reported fully printed SWNT-based TFTs on flexible substrates, and
the devices showed no measurable change in electrical performance under a bending
radius as small as 1 mm [125]. Afterwards, all-carbon integrated circuits were
demonstrated by Sun et al. for the first time [53]. The devices were entirely
composed of carbon-based materials with active channels and passive elements
fabricated using stretchable and thermostable assemblies of SWNTs, plastic
polymer dielectric layers, and plastic substrates. Surprisingly, functional integrated
circuits have also been successfully made into a 3D dome. Another interesting
progress was reported by Chae et al. demonstrating a highly stretchable and
transparent FET which combined graphene/SWNT hybrid electrodes and an SWNT
network channel with a wrinkled Al2O3 dielectric layer [134]. The authors claimed
that the wrinkled Al2O3 layer contained effective built-in air gaps, offering a gate
leakage current as small as 10-13 A. Thanks to the wrinkled dielectric layer, the
devices retained their good performance under strains as large as 20% without
noticeable leakage current increases or performance degradations. Furthermore, the

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devices showed no significant degradation after over 1000 cycles of stretch-release

process. Recently, Cao et al. successfully demonstrated ultraflexible and imper-
ceptible p-type nanotube transistors and integrated circuits with a bending radius
down to 40 lm [131]. The as-fabricated ultralight-weight (\3 g/m2) nanotube
transistors showed high mechanical robustness which can accommodate severe
crumping and compressive strain of 67%. Moreover, the nanotube circuits remained
properly functional under 33% compressive strain, showing great potential as
indispensable components for ultraflexible complementary electronics.

5 Summary and Outlook

In summary, SWNTs are highly promising for future RF electronics, digital

electronics, and macroelectronics applications due to their excellent electrical,
mechanical, and thermal properties. In regard to RF electronics, RF performance of
SWNT transistors ready for some practical applications have been achieved, and RF
circuits and systems based on SWNTs have been demonstrated [11, 23]. For SWNT-
based nanoelectronics, ballistic SWNT transistors provide a good platform for
further pushing forward Moore’s law [2]. For macroelectronics, SWNT random
network TFTs have been demonstrated in various applications, including digital
circuits, active-matrix backplanes for display electronics and sensors, as well as
flexible electronics. In spite of the significant progress achieved, several further
developments are needed before SWNTs can be adopted by industry. First, it is of
key importance to achieve aligned SWNT arrays with both high density (150–200
tubes/lm) and ultrahigh-purity semiconducting ([99.9999%) for SWNT RF and
digital electronics. With the advancement in the nanotube alignment technologies,
multiple transfer of high-density and ultrahigh-purity semiconducting aligned
SWNT arrays provides a promising way to reach the goal. Second, for all
applications, hysteresis can be an issue compromising SWNT performance. Further
optimization of dielectric materials for SWNT transistors to achieve hysteresis-free
operations while maintaining excellent transistor performance is also necessary. In
addition, passivation, integration, and stability of SWNT transistors require
systematic investigations to cooperate with other functional parts. Moreover,
developing reliable and small-area metal contacts for both p-type and n-type SWNT
FETs in a sub-10-nm channel length also requires great research efforts to achieve
energy-efficient digital electronics. With the advancement in the above develop-
ments, SWNT electronics will finally become an indispensable part of future
electronics.

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