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Lecture 5 VHDL

Logic Circuit Design (City University of Hong Kong)

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EE2000 Logic Circuit Design

VHDL

VHDL and EDA

• Digital design could be very complicated and
time-consuming. Modern complex system
designs rely on EDA (Electronic Design
Automation_ tools.
• EDA resources can be reused and it shorten the
complexity and design time. Design time is the most
critical factor in determining the market share and
profits.
• EDA tools are used at all stages in the design
process, including design capture, logic synthesis,
simulation, layout placement and routing, layout
verification.
• VHDL is one of the most commonly EDA tools.

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Basic Logic Gat es using VHDL

• 5.1 Hardware Descript ion Language (HDL)
• 5.2 VHDL Code St ruct ure
• 5.3 Basic Logic Gat es Using VHDL
• 5.4 VHDL Dat a Types
• 5.5 VHDL Operat ors - Boolean / Relat ional / Arit hmet ic
• 5.6 VHDL Synt ax for Boolean expressions / Logic Circuit s
• 5.7 VHDL Module
• 5.8 VHDL Format & Synt ax

5.1 Hardware Descript ion Language (HDL)

• Two popular HDLs—VHDL and Verilog

• VHDL – Very High Speed Int egrat ed Circuit
Hardware Descript ion Language (VHSIC-HDL).
• Developed by U.S. Depart ment of Defense (DoD).
• St andardized by IEEE.
• Widely used t o t ranslat e designs int o bit pat t erns
t hat configure t he act ual devices.

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5.1 Hardware Descript ion Language (HDL)

• HDL – Hardware Descript ion Language is a soft ware programming
language t hat is used t o model a piece of hardware
• VHDL is an HDL used t o describe a digit al syst em at several
different levels: behavioral, dat a flow, and st ruct ural.
• VHDL leads nat urally t o a t op-down design met hodology.
• The Vivado design t ool from Xilinx will be used t o design
simulat ion and synt hesize t he logic circuit / syst em in t his course.

5.2 VHDL Code St ruct ure – Illust rat ion

Module A

Module B Module C

Module D Module D

Like breaking down a complicat ed circuit int o a number of

smaller circuit s, wit h each module describe a smaller circuit . The
modules are connect ed t hrough port s t o form t he final circuit .
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5.2 VHDL Code St ruct ure – Illust rat ion

Module

Port Ent it y Block [AA]

Archit ect ure Block 1 [XX]

Port
Archit ect ure Block N [YY]

5.2 VHDL Code St ruct ure

{Li br ar y Declar at i on}
{Ent i t y Declar at i on}
{Ar chi t ect ur e Declar at i on}

Library declarat ion: locat e t he syst em library, IEEE

St andard library is oft en included in t he VHDL code.
STD_LOGIC_1164 cont ains STD_LOGIC t ypes & relat ed
funct ions. You can creat e your own library.

Ent it y declarat ion: defines t he ext ernal int erface t o

t he current design [input (port ) / out put (port )].

Archit ect ure declarat ion: describes t he int ernal circuit

of t he corresponding ent it y [logic circuit ].
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5.2 VHDL Code St ruct ure – Illust rat ion

library ieee; logic_c

use ieee.std_logic_1164.all;

entity logic_c is
port(
x1,x2,x3,x4,x5 : in bit;
f : out bit
);
end logic_c;

architecture Behavior of logic_c is

begin
f <=((x1 or x2) and (x3 and x4) or x5);
end Behavior; 9

5.3 Basic Logic Gat es using VHDL

Circuit descript ion wit h an archit ect ure

The descript ion of t he logic circuit operat ion as in

“ Funct ional code” is enclosed by BEGIN and END.

ARCHITECTURE XX of AA IS ARCHITECTURE YY of AA IS

BEGIN BEGIN
Funct ional code Funct ional code
END XX; END YY;

AA: ent it y name

XX, YY: archit ect ure name
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5.3 Basic Logic Gat es using VHDL

Example:

architecture Behavior of nand_gate is

begin
f <= not (x1 and x2);
end Behavior;

Alternative: f <= x1 nand x2;

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5.3 Basic Logic Gat es using VHDL

VHDL is “ case insensit ive” .

archit ect ure Behavior of nand_gat e is

begin
f <= x1 nand x2;
end Behavior;

The above code is ident ical t o t he following:

ARCHITECTURE Behavior of NAND_GATE IS

BEGIN
F <= x1 NAND x2;
END Behavior;

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5.3 Basic Logic Gat es using VHDL

VHDL language t ranslat es logic circuit int o Look-up Table

O = I0 and I1

A t ypical Schemat ic Diagram for a logic gat e in t he CAD t ool –

e.g. Xilinx Vivado Soft ware

I0, I1, O int ernal port names are generat ed by Vivado soft ware

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5.4 VHDL Dat a Types

Nat ure of input and out put signals

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5.4 VHDL Dat a Types

Select ed Dat a t ypes:
1) Predefined t ypes
2) User-defined t ypes
Ty p e D e scr i p t i o n
bit ‘0’ or ‘1’
boolean FALSE or TRUE
integer an integer in the range −231 to +(231 − 1)
natural integer in the range 0 to +(231 − 1)
positive integer in the range 1 to +(231 − 1)
real floating-point number in the range −1.0E38 to +1.0E38
character any legal ASCII character including upper and lowercase
letters, digits, and special characters
time An integer with units fs, ps, ns, us, ms, sec, min, or hr
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5.4 VHDL Dat a Types

A physical t ype allows user t o define measurement unit s for
some physical quant it y, like lengt h, t ime, pressure, capacit y,
et c.
-- EXAMPLE : physical t ype definit ions AFTER t he t ype Dist ance defined,
t ype Dist ance is range 0 t o INTEGER'HIGH
“ inch” , “ millimet re” , “ Dist ance” can
unit s be recognized by t he VHDL design t ool
micron; and we can declare signal Dist 2 as
millimet re = 1000 micron; following:
cent imet re = 10 millimet re;
met re = 100 cent imet re;
inch = 25400 micron; -- EXAMPLE : signal declarat ion and
foot = 12 inch; calculat ion
yard = 3 foot ;
mile = 5280 foot ; signal Dist 2 : Dist ance := 2 inch - 1
end unit s Dist ance; millimet re;

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5.4 VHDL Dat a Types

Let ’s begin wit h simple t hings first .
Signal declarat ion synt ax:
signal <name> : <type>;

Signal declarat ion examples for archit ect ure:

signal x1 : bit ;
signal C : bit _vect or (3 t o 0);
signal D : bit _vect or (7 downt o 0);

bit & bit _vect or are predefined in VHDL st andards IEEE library.
bit : a bit obj ect is eit her of value 0 or 1.
bit _vect or: represent mult i-bit dat a by an array of bit obj ect s
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5.4 VHDL Dat a Types – bit / bit _vect or

signal x1 : bit ;
signal C : bit _vect or (3 t o 0);
signal D : bit _vect or (7 downt o 0);
Signal assignment examples:
x1 <= ‘ 1’ ;
C <= “ 1010” ;
D <= “ 11001010” ;

• Signal represent physical int erconnect (wire) t hat

communicat e bet ween processes/ modules
• Signal assignment operat or “ <=”
• You can assign ‘ 1’ t o a single bit value, and “ 1010” t o an
array of bit values.
• You can use (3 t o 0) or (7 downt o 0) t o index t he array values.

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5.4 VHDL Dat a Types – bit _vect or

Dat a array is assigned as bit vect or in VHDL.
Here is a dat a array A:
A[ 7] A[ 6] A[ 5] A[ 4] A[ 3] A[ 2] A[ 1] A[ 0]

signal C: bit _vect or (0 t o 3);

signal D: bit _vect or (3 downt o 0);
signal A: bit _vect or (7 downt o 0);

C <= "1101"; C(0)=1 C(1)=1 C(2)=0 C(3)=1

D <= C; D(3)=1 D(2)=1 D(1)=0 D(0)=1
A(6 downt o 3) <= D; A(6)=1 A(5)=1 A(4)=0 A(3)=1

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5.4 VHDL Dat a Types – (Number t ype)

VHDL Decimal equivalent Bit Pat t ern

B” 101” 122+02+1=5 101

X” 101” 1162+016+1=257 100000001
101 101 1100101
These numeric values are referred t o as scalars or lit erals. Binary
(prefix of B), Hex (prefix of X), Decimal (no prefix).
A signal may opt ionally be declared wit h an init ial value:
Synt ax: signal <name> : <t ype> := <init ial_value>;
Example:
signal d : bit_vector(15 downto 0) := X"1234";
:=  is signal init ializat ion operat or
Bit array or bit vect or is assigned t o a signal (d) wit h hexadecimal
value of X"1234".
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5.4 VHDL Dat a Types – st d_logic / st d_logic_vect or

St andard Library defined by IEEE

library ieee;
use ieee.std_logic_1164.all;

Type Descript ion

U uninit ialized. This signal hasn't been set yet
X unknown. Impossible t o det ermine t his value/ result
0 logic 0
1 logic 1
Z High Impedance (Tri-st at e)
W Weak signal, can't t ell if it should be 0 or 1
L Weak signal t hat should probably go t o 0
H Weak signal t hat should probably go t o 1
- Don't care 21

5.4 VHDL Dat a Types – Logic signal

Two mult i-bit signals can be AND-ed t o form an out put
signal. They all have t he same bit lengt h.

SIGNAL A :BIT_VECTOR (7 DOWNTO 0); BIT_VECTOR:

SIGNAL B :BIT_VECTOR (7 DOWNTO 0); Wit h well defined
SIGNAL S :BIT_VECTOR (7 DOWNTO 0); logic value [0 / 1]
BEGIN
S <= A and B;
END;

SIGNAL A : STD_LOGIC_VECTOR (7 DOWNTO 0);

STD_LOGIC_VECTOR:
SIGNAL B : STD_LOGIC_VECTOR (7 DOWNTO 0);
logic out put [0 / 1 / Z
SIGNAL S : STD_LOGIC_VECTOR (7 DOWNTO 0);
/ U / et c…] as shown
BEGIN
in previous slide
S <= A and B;
END;
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5.5 VHDL Operat or - Boolean Operat ors

Logical operat ion Operat or Example

AND AND Z <= (A AND B);
NAND NAND Z <= (A NAND B);
NOR NOR Z <= (A NOR B);
NOT NOT Z <= NOT (A);
OR OR Z <= (A OR B);
XNOR XNOR Z <= (A XNOR B);
XOR XOR Z <= (A XOR B);

VHDL provides predefined operat ors for modeling hardware unit s.

Logical (Boolean), Arit hmet ic, Relat ional Operat ors

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5.5 VHDL Operat or - Relat ional Operat ors

Relat ional operat ion Operat or Example

Equal t o = If (A = B) Then
Not equal t o /= If (A /= B) Then
Less t han < If (A < B) Then
Less t han or equal t o <= If (A <= B) Then
Great er t han > If (A > B) Then
Great er t han or equal t o >= If (A >= B) Then

VHDL provides predefined operat ors for modeling hardware unit s.

Logical (Boolean), Arit hmet ic, Relat ional Operat ors

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5.5 VHDL Operat or - Arit hmet ic Operat ors

This part will be covered in t he lat er chapt er.

Arit hmet ic operat ion Operat or Example

Addit ion + Z <= A + B;
Subt ract ion - Z <= A - B;
Mult iplicat ion * Z <= A * B;
Division / Z <= A / B;
Exponent iat ing ** Z <= 4 ** 2;
Modulus MOD Z <= A MOD B;
Remainder REM Z <= A REM B;
Absolut e value ABS Z <= ABS A;

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5.5 VHDL Operat or - Arit hmet ic Operat ors

REM:
5 rem 3 = 2  5/3 = 1 remainder is 2
(‐5) rem 3 = ‐2
5 rem (‐3) = 2
(‐5) rem (‐3) = ‐2
MOD:
5 mod 3 = 2 5 = 1*3 + 2
(‐5) mod 3 = 1  different from REM -5 = -2*3 + 1
5 mod (‐3) = ‐1  different from REM 5 = -2(-3) – 1
(‐5) mod (‐3) = ‐2 -5 = 1*(-3) -2

Then what is MOD used for?

The mod operat or gives t he residue for a division t o round down.

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5.5 Precedence of VHDL Operat ors

VHDL Operat ors:
1. Binary logical operat ors: and, or, nand, nor, xor, xnor
2. Relat ional operat ors: =, / =, <, <=, >, >= Sll = Shift Left Logical
Srl = Shift Right Logical
3. Shift operat ors: sll, srl, sla, sra, rol, ror Sra = Shift Right Arit hmet ic
rol = Rot at e Right logical
4. Adding operat ors: +, -, & (concat enat ion)
5. Unary sign operat ors: +, -
6. Mult iplying operat ors: *, / , mod, rem
7. Miscellaneous operat ors: not , abs, **
Class 7 has highest precedence, t hen 6, 5, 4, …
Operat ors in t he same class are applied left t o right
Parent heses change t he order of precedence
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5.5 VHDL Operat ors - Example

Operat ors wit h t he highest precedence are applied
first , wit hout t he presence of parent heses.

Example:

f <= a AND NOT(b) OR NOT(a) AND b;

ab’ + a’ b

f <= a AND (NOT(b) OR NOT(a)) AND b;

a(b’ + a’ )b

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5.6 VHDL Synt ax for Boolean Expressions

• VHDL code describes t he circuit design wit h Boolean
expressions.
• Itis different from comput er program which is composed of
a sequence of inst ruct ions for CPU t o execut e.
• VHDL Boolean expressions are st at ement s only for
configuring t he FPGA chip (no CPU t o execut e t hese
st at ement s ).
BEGIN

St at ement

St at ement

St at ement

END
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5.6 VHDL Synt ax for Boolean Expressions

VHDL models combinat ional circuit using concurrent st at ement s.
Concurrent st at ement s:
A change(s) at t he input (s) will cause t he out put change
accordingly.

Sequent ial st at ement s will be covered lat er.

VHDL St at ement s

Concurrent St at ement s Sequent ial St at ement s

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5.6 VHDL Synt ax for Boolean Expressions

C <= A and B aft er 5 ns;

E <= C or D aft er 5 ns;

Concurrent st at ement s (cont inuous assignment s) example:

A signal assignment st at ement has t he form:

signal_name <= expression [after delay];

Square bracket is opt ional and it is for indicat ing t he

propagat ion delay.
Signal on t he left is updat ed aft er delay, if included.

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5.6 VHDL Synt ax for Boolean Expressions

Examples of Boolean expressions converted into VHDL Boolean expressions.

Boolean VHDL Boolean

𝑌 𝐴𝐵 Y <= NOT(A AND B);
or
Y <= A NAND B;
𝑌 𝐴 𝐵 Y <= NOT(A OR B);
or
Y <= A NOR B;
𝑌 𝐴 𝐵𝐶 Y <= A OR (B AND C);
𝑌 𝐶𝑋 𝐷 Y <= C AND NOT (X OR D);
𝑌 𝐴𝐵 𝐶 𝐴̅ 𝐵 𝐶 𝐴𝐵𝐶 Y <= (A AND NOT B AND C) OR
(NOT A AND NOT B AND C) OR
(NOT (A AND B) AND C);

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5.6 VHDL Synt ax for Logic Circuit

Example of 3 concurrent st at ement s:

Precedence order is NOT import ant for concurrent st at ement s !!

sig1 <= (a and b); out 1 <= (sig1 or c);

out 1 <= (sig1 or c);  sig1 <= (a and b);
out 2 <= (not d); out 2 <= (not d);
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5.6 VHDL Synt ax for Logic Circuit -

Exercise

Writ e your own VHDL st at ement t o describe t he

above t wo logic circuit s.
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5.6 VHDL Synt ax for Logic Circuit -

Exercise
S1

S2

S1 <= x1 OR x2;
S2 <= x3 AND x4; OR F <= (x1 OR x2) XOR (x3 AND x4);
F <= S1 XOR S2;

• Left hand st yle is more readable and t raceable but need t o declare t wo
more signals.
• In cont rast , Right hand st yle use less lines of code but a bit difficult for
debugging.
• They bot h have same result aft er synt hesize. 35

5.6 VHDL Synt ax for Logic Circuit -

Exercise

Sig1

Sig3
Sig2

Sig1 <= x XOR y;

Sig2 <= x AND y;
Sig3 <= Sig1 AND Cin;
s <= Cin XOR Sig1;
Cout <= Sig3 OR Sig2;

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5.7 VHDL Module

A Logic circuit consist s of one or mult iple modules.
Each module consist s of only one ent it y wit h archit ect ure(s).
Ent it y descript ion declares t he input and out put signals.
Each ENTITY has a unique name !!
Port declarat ion specifies t he input signals and out put signals
for t he module.

ENTITY name IS
PORT( … );
END name;

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5.8 VHDL Format and Synt ax – Example

ENTITY and_gate IS
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
S : out STD_LOGIC
);
END and_gate;

Mode indicat es t he direct ion (in, out , and inout ) of port signals
Type specifies t he dat a t ype (bit , bit _vect or) t hat can be
communicat ed

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5.7 VHDL Modules – Ent it y Example

Example for a circuit named logic_c :

logic_c

ent it y logic_c is
port (
x1,x2,x3,x4,x5 : in st d_logic;
f : out st d_logic
);
end logic_c;
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5.7 VHDL Modules – Ent it y Example

Example for a Full Adder:

ent it y FullAdder is
port (
X, Y, C_in : in st d_logic;
C_out , Sum : out st d_logic
);
end FullAdder;

In t his example, t he VHDL assignment st at ement s for Sum

and C_out represent t he logic expressions for t he full adder.
Sum and C_out are described by archit ect ures.
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5.8 VHDL Format and Synt ax – Example

Every ENTITY must at least cont ain one
ARCHITECTURE associat ed wit h it .
Each ARCHITECTURE has a unique name.

ARCHITECTURE ckt OF and_gate IS

BEGIN
y <= a AND b;
END ckt;

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5.8 VHDL Format and Synt ax

– Complet e Module Code
library ieee;
use ieee.std_logic_1164.all;

ENTITY and_gate IS
PORT ( a,b :IN STD_LOGIC;
s :OUT STD_LOGIC)
;)
END and_gate;

ARCHITECTURE ckt OF and_gate IS

BEGIN
s <= a AND b;
END ckt;
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*
Writ e a complet e VHDL design module t o implement a
circuit wit h t he following Boolean expressions. Assign a
signal name sigW1 t o represent t he common logic t erm in
your design.

A = (XYZ’ )’ + XZ
B = (XYZ’ )’ (X + Z)
C = ((XYZ’ )’ +X’ )’

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*Example

A = (XYZ’ )’ + XZ
B = (XYZ’ )’ (X + Z)
C = ((XYZ’ )’ +X’ )’

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6. Component s and Inst ant iat ion

• Structural or modular design of a complex system

• Starting from small module or subcircuits.
• Resources reused make easier.

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Component Declarat ion

• In modular design, an architecture may contain multiple
components.
• They need to be define globally.
architecture [name] …
[signal]

component X -- Component X declaration

…
end component;

component Y -- Component Y declaration

…
end component;

begin
… -- Component instantiation
end [name];
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Full Adder Design Inputs Outputs

a b c s
There are two half‐adders(HAs) in a full 0 0 0 0
adder, use half‐adder as a component 0 1 0 1
for modular design. The HA logic is: 1 0 0 1

s 𝑎⊕ 𝑏 c 𝑎𝑏 1 1 1 0

entity HA is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC
);
end HA;

architecture Behavioral of HA is begin

s <= a xor b;
c <= a and b;
end Behavioral;
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entity FA is
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic
);
end FA;

architecture behavior of FA is
component HA
port(
a : in std_logic;
b : in std_logic;
sum : out std_logic;
cout : out std_logic
);
end component;

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• Two HAs are needed to be connected in certain way.

• Use internal signals s1,c1,c2 to connect the two HAs.
• The signal pass to HAs via port map.

declare internal signal

signal s1,c1,c2 : std_logic:='0’;

begin

HA1 : HA port map (a,b,s1,c1);

HA2 : HA port map (s1,cin,sum,c2);
carry <= c1 or c2; Final carry
end;

Port mapping for

Instantiation, use each half-adder.
different name for
each half-adder.
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entity FA is
port (a : in std_logic; entity HA is
b : in std_logic; port (a : in STD_LOGIC;
cin : in std_logic; b : in STD_LOGIC;
sum : out std_logic; s : out STD_LOGIC;
cout : out std_logic c : out STD_LOGIC
); );
end FA; end HA;

architecture Behavioral of HA is
architecture behavior of FA is begin
component HA s <= a xor b;
port( c <= a and b;
a : in std_logic; end Behavioral;
b : in std_logic;
sum : out std_logic;
cout : out std_logic
);
end component;
signal s1,c1,c2 : std_logic:='0’;

begin
HA1 : halfadder port map (a,b,s1,c1);
HA2 : halfadder port map (s1,c1,sum,c2);
carry <= c1 or c2;
end; 12

Design a 2-to-4 Line Decoder using 1-to-2 Line Decoder

D0
(LSB) A0 D1
(MSB) A1
D2
D3

Inputs Outputs
A1 A0 D0 D1 D2 D3 D0 = A1’A0’
(LSB) A 0
0 0 1 0 0 0 D1 = A1’A0
(MSB) A 1
0 1 0 1 0 0
1 0 0 0 1 0 D2 = A1A0’
1 1 0 0 0 1
D3 = A1 A0

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The flow:
The t arget module

The component declaration is similar to an

entity declaration.

The component declaration statement must

Pick a
component be first declared in the architecture of a
module so that the VHDL tools can check
the component to have the same ports as the
entity as declared.

Pick some
wires for
connect ion

The flow:
The t arget module

Pick a
component

Component instantiation
statement performance component
numbering/labelling and signals name
assignment such as the physical part
placements and wire connections.

Place
component s and
connect ing
wires t o
component s

Connect ing
component s’ D0
out put t o produce
t he circuit module
out put

D1

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Solution:

D0 =A1’A0’
D1 = A1’A0
D2 = A1A0’
D =A A

Inputs Outputs
A1 A0 D0 D1 D2 D3

0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

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