INTERNATIONAL UNIVERSITY

SCHOOL OF ELECTR ICAL ENGINEERING

DIGITAL LOGIC DESIGN LABORATORY

Lab 5

FLIP FLOPS &

COUNTERS

Date: .........29/05/2024....................
Group: .....8.......

Student’s Name: ....Tạ Thanh Vũ …..ID: ITITIU21352

Student’s Name: ......Lê Ngọc Đăng Khoa..... ID: ITITIU20230
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I/ OBJECTIVES
Upon completion of this experiment, you are able to know:
• The operation of flip-flops.
• How to convert a flip-flop into other flip-flop.
• The operation of 7-segment LED, decoder IC and how to design counters
using flip-flops.

II/ COMPONENTS REQUIRED

1. Main board and sub board of Digital System Kit
2. IC 74LS112 : 2 JK-FFs.
3. IC 74LS74 : 2 D-FFs.
4. IC 74LS47 : BCD to 7-Segment Decoder/Driver
5. IC 74LS04 : 6 NOT gates.
6. IC 74LS00 : 4 NAND gates.
7. IC 74LS86 : 4 XOR gates.
8. IC 74LS32 : 4 OR gates.
9. IC 74LS02 : 4 NOR gates.

III/ CONTENTS
1. Flip Flops
a. The operation of JK – FF.
b. The operation of D – FF.
c. Convert JK-FF into D-FF.
2. Design asynchronous counters
a. Implement an asynchronous 3-bit up counter having M = 8 by using IC
74LS112
b. Implement an asynchronous 3-bit up counter having M = 5 by using IC
74LS112
c. Implement an asynchronous 3-bit down counter having M =8 by using IC
74LS112.
d. Implement an asynchronous 3-bit up counter having M=8, with a control
input for up/down counting using 74LS112 and 74LS86
3. Synchronous counters
a. Analyse and implement a synchronous counter
b. Design and implement a synchronous 2-bit counter M = 3

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IV/ PRE-LAB
- Pre-lab includes reading the lab assignment in advance, answering the
questions or doing the calculations, and if necessary reviewing the material in the
textbook. All pre-lab preparation must be recorded and dated in the pre-lab sheet
prior doing the lab. The lab instructor will check your pre-lab write-up and sign
your pre-lab sheet.
- Answering all the questions and comments, draw the waveforms and
circuits, fulfill the truth tables and present diagrams on this experiment before doing
the lab.
- If you don’t prepare the pre-lab, you will not be allowed to do
experiment.

V/ EXPERIMENT
1. FLIP FLOPS
a. JK-FF (74LS112)

SW0

J K Q Q+
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 1
0 0 1 1
0 1 1 0
U2A 1 0 1 1
4
74LS112
SW2LED DISPLAY 3
J
PRE
Q
5
1 1 1 0
1
SW4/PULSE CLK
CLR
2 6
K Q
SW3LED DISPLAY
15

SW1

Figure 1. JK-Flip flop Table 1. Truth Table of JK-FF

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Implement the circuit shown in figure 1

▪ Check the active state of the signals PRE and C LR :

PRE ....... On the JK Flip-Flop, this was utilized to immediately insert a "1" in the Q
output.

CLR ........ On the JK Flip-Flop, this was utilized to immediately insert a "1" in the Q
output.
+ the CKC is a positive-triggered.
b. D-FF (7474)
SW0

D Q Q+
0 0 0
1 0 1
0 1 0
1 1 1

U19A
4
2 PRE 5
CKLED DISPLAY D Q
Pulse SW 3
CLK
CLR
6 LED DISPLAY
Q

74LS1
74

SW1

Figure 2. D-Flip flop Table 2. Truth Table of D-FF

▪ Implement the circuit shown in figure 2

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INPUTS OUTPUTS
PR CLR CLK D Q Q
0 1 X X 1 0
1 0 X X 0 1
0 0 X X X X
1 1 ↑ 0 1 0
1 1 ↑ 1 0 1

- PRE: On the JK Flip-Flop, this was utilized to immediately insert a "1" in the Q
output.

- CLR: On the JK Flip-Flop, this was utilized to immediately insert a "1" in the Q
output.

c. Convert JK-FF into D-FF

Figure 3 - Convert JK-FF into D-FF

- The circuit via simulation software:

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Figure 4 - Logic diagram convert JK-FF into D-FF

D Q Q+
0 0 0
1 0 1
0 1 0
1 1 1

Table 3 - True Table of the new FF

- When D = 0, J = 0 and K = 1 (because K = D̅ ).
If Q = 0, JK inputs are 0 and 1, leading Q+ to be 0 (Reset condition).
If Q = 1, JK inputs are 0 and 1, leading Q+ to be 0 (Reset condition).
- When D = 1, J = 1 and K = 0 (because K = D̅ ).
If Q = 0, JK inputs are 1 and 0, leading Q+ to be 1 (Set condition).
If Q = 1, JK inputs are 1 and 0, leading Q+ to be 1 (Set condition).

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2. ANALYSE AND DESIGN ASYNCHRONOUS COUNTERS

a. Implement an asynchronous up counter having M = 8 by using IC 74LS112

Figure 5 - Logic diagram

Implement the circuit via simulation software and paste the result in here

An asynchronous counter works by having the clock input of each flip-flop driven by
the output of the preceding flip-flop, causing a ripple effect as the state change
propagates through the flip-flops.

In contrast, a synchronous counter has all flip-flops' clock inputs connected to the
same clock source, ensuring simultaneous state changes, and avoiding the ripple
effect. This leads to faster and more predictable operation in synchronous counters.

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b. Design an asynchronous up counter having M = 6 by using IC 74LS112

▪ Show the way to make it (step by step)
- You can use the counter in the previous section for design an asynchronous up
counter having M = 6
+ Step 1: Redefine the limit of the counter, in this case M = 6 means the limit of the
counter is 101.
+ Step 2: Use AND gate to set limit of counter, as it has to be reset when limit is
reached, in this case we can set AND gate with 2 inputs Q2 and Q1, and output
connected to CLR by 1 XOR gate.
+ Step 3: Run and complete.

- The circuit via simulation software:

c. Implement an asynchronous 3-bit down counter having M = 8 by using IC

74LS112.

Figure 7 - Asynchronous 3-bit down counter having M=8

- The circuit via simulation software:

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▪ Implement the above circuit shown in figure 7. The PR (SW1) and CL

(SW2) inputs are in the appropriate states to make the circuit operate:
PR: ...... This input should be set to LOW (0V) to ensure the flip-flops are
not asynchronously preset........
CL: ........This input should be set to HIGH (5V) to ensure the flip-flops
are not asynchronously cleared….
▪ Observe the results and give conclusions:
- This circuit is quite similarr to the previous one, only the CLK gate will take input from Q
instead of Q as in the prior one. The result will be reversed, and the circuit will begin to
count down.

d. Implement an asynchronous 3-bit counter having M = 8, with a control for

up/down counting

Figure 8 – Asynchronous 3-bit up counter having M = 8

▪ Implement the above circuit shown in figure 8 (using IC74LS112 and 74LS86).
The PR (SW1) and CL (SW2) inputs are in the appropriate states to make the
circuit operate:

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PR : This input should be set to HIGH (5V) to ensure the flip-flops are not
asynchronously preset.
CL: This input should be set to HIGH (5V) to ensure the flip-flops are not
asynchronously cleared.

Observe the results when C = 0 and C = 1 and give conclusions

When C = 0;
The circuit will function as an up-counter. The JK Flip-Flops will count upwards with
each clock pulse.
The output LEDs will indicate the binary count from 000 to 111 (0 to 7).

When C = 1;
The circuit will function as a down-counter. The JK Flip-Flops will count downwards
with each clock pulse.
The output LEDs will indicate the binary count from 111 to 000 (7 to 0).
Conclusions
By setting the control input (C) to 0, the circuit counts upwards, incrementing the
binary value with each clock pulse.
By setting the control input (C) to 1, the circuit counts downwards, decrementing the
binary value with each clock pulse.
This demonstrates the versatility of the asynchronous counter in handling both up-
counting and down-counting modes based on the control signal.

3. ANALYSE AND DESIGN SYNCHRONOUS COUNTERS

a. Analyse the counter shown in figure 9

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Figure 9

Implement the circuit shown in figure 9. The K inputs of FF 0 and FF2 areconnected
to High level. The PR (SW1) and CL (SW2) inputs are in the appropriate states to
make the circuit operate.

When the clock is active:

- FF0: This flip-flop will toggle its state with every clock pulse because its J and K
inputs are both high (J = 1, K = 1), making it a T flip-flop.
- FF1: This flip-flop will toggle its state based on the output of FF0. It toggles when
both inputs (J and K) are high, which is controlled by the Q output of FF0.
- FF2: This flip-flop is connected in a similar manner and will toggle based on the
combined outputs of FF0 and FF1 through the AND gate. The AND gate ensures FF2
only toggles when both FF0 and FF1 outputs are high.
The excitation (trigger) input equations of all flip-flops:

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J0 =Q'2; K0 = 0

J1 = Q0; K1 = Q0
J2 = Q0 Q1; K2 = 0
Present State Next State
Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 Q2 Q1 Q0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 1 0 0 1 1 1 0 0 1 1
0 1 0 0 0 0 0 1 0 0 1 1
0 1 1 1 0 1 1 1 0 1 0 1
1 0 0 0 0 0 0 0 0 1 0 0
1 0 1 0 0 1 1 0 0 1 1 1
1 1 0 0 0 0 0 0 0 1 1 0
1 1 1 1 0 1 1 0 0 1 0 1

Figure 10

▪ Draw the waveforms of the outputs: Q0 Q1 Q2 in figure 11 (Initial state: Q0 =

0, Q1 = 0, Q2 = 0).

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CLK
1

J0 0

K0 0

Q0 0

J1 0

K1 0

Q1 0

J2 0

K2 0

Q2 0

State 000

Q0Q1Q2
Figure 11 - Waveforms of the outputs Q0 Q1 Q2

b. Design and implement a synchronous 2-bit counter having M = 3 shown in

the following diagram (Figure 12) using JK-FFs (74112) and NAND gates
(7400):

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00 10

01 11

Figure 12– State diagram of synchronous 2-bit counter

Figure 13 - Logic diagram of synchronous 2-bit counter, M = 3

Transition Table
Present State Next State
Q1 Q0 J1 K1 J0 K0 Q1 Q0
0 0 1 X 0 X 1 0
1 0 X 1 X 0 0 1
0 1 1 X 1 X 1 1
1 1 X 0 0 1 1 0
the excitation (trigger) input equations of all flip-flops:
J0 =Q'1 Q 0; K0 = Q0

J1 =1; K1 =Q'0

Discussion of Results

- Discover the differences between J-K Flip Flops and D Flip Flops, as well as how to
convert J-K Flip Flops to D Flip Flops.
- Learn how to use J-K Flip Flops to construct simple counting circuits.

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