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Design of 8 bit Pipeline ADC in Cadence

Technical Report · January 2021

DOI: 10.13140/RG.2.2.21029.52960

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Design of 8 bit Pipeline ADC in Cadence

Arash Katourani

January 2021

Email: [email protected]

Shahid Beheshti University

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1-Pipeline Architecture ............................................................................... 3
2-Testing ..................................................................................................... 5
3-Design of Analog Parts ............................................................................ 7
4-Two Bit Flash ADC ................................................................................... 9
5-Two Bit DAC........................................................................................... 10
6-Gain-Stage………………….. ........................................................................ 12
7-Shift Register…….. .................................................................................. 13
8-Simulation Results…. ............................................................................. 14
9-FFT Calculation(SNR and ENOB) ............................................................ 19
10- DNL Calculation ……..………..................................................................28

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1- Pipeline Architecture

Fig. 1-6: One stage architecture

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Fig. 1-2: 6 bit architecture.

Fig. 1-2: One stage.

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 2- Testing
It is better to use ideal blocks for finding errors and flaws in sections such as Gain-Stage and
Subtractor. These sections are inherently analog and could be susceptible.
For this reason, Comparator and PEDFF have been designed with Verilog codes, and then for
the final design, the non-ideal replaced.

Fig. 2-1: Verilog code for PEDFF (For initial testing) real ones have been replaced after.

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Fig. 2-2: Verilog code for comparator (For initial testing) real ones have been replaced after.

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 3- Design of Analog Parts
Op-amp1:

Fig. 3-1: OTA for Gain-Stage, Track and Hold, and Subtractor.

1
R. S. Assaad and J. Silva-Martinez, "The Recycling Folded Cascode: A General Enhancement of the Folded Cascode
Page

Amplifier," in IEEE Journal of Solid-State Circuits, vol. 44, no. 9, pp. 2535-2542, Sept. 2009, doi:
10.1109/JSSC.2009.2024819.
 Track and Hold:

Fig 3-2: Track and Hold.

Subtractor:

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Fig 3-3: Subtractor.

 4- Two Bit Flash ADC

Fig. 4-1: 2 bit Flash ADC.

Clock Generator:

Fig. 4-2: Clock generator.

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5- Two Bit DAC

Fig. 5-1: One bit DAC.

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Fig. 5-2: Two bit DAC.

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Fig. 5-3: Transmission Gate.

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 6- Gain-Stage
According to Fig. 8-2 the gain of this stage should be 4 in order of full scale results.

Fig. 6-1: Gain Stage with gain=4

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7- Shift Register

Fig. 7-1: Shift Register for synchronizing the bits, using DFF.

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 8- Simulation Results
Results are for 8 mV, 10 micro-second input ramp with the clock of 50 MHz.

First stage:

Fig. 8-1: Digital output.

Fig. 8-2: Subtractor output.

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Second Stage:

Fig. 8-3: Comparators outputs.

Fig. 8-4: Digital output.

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 Fig. 8-5: Subtractor output.

Third Stage:

Fig. 8-6: Comparator output.

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 Fig. 8-7: Digital output.

Fig. 8-8: Subtractor output.

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Fourth Stage (last stage):

Fig. 8-9: Comparators and Digital output

Fig. 8-10: 6 bit output – Shift Register output

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 9- FFT Calculation
The reason for calculating FFT is to obtain SFDR.
SFDR There is a gap between the main signal's amplitude and the largest Spur in the spectrum.
Spurs are unwanted noises because of switching or other noise generators; Larger SFDR is ideal.
To obtain FFT, you must do the following:
𝑓𝑠 is the clock frequency and 𝑓𝑖𝑛 is the input signal frequency:
𝑚
𝑓𝑖𝑛 = . 𝑓𝑠
𝑁
m and N could be any value but must be relatively prime numbers. Assume N as a power of 2 for
𝑚
ease of the calculation. The smaller the , the more precision of the output signal obtains2.
𝑁

The output signal is the output of an ideal 8 bit DAC (Fig. 9-1). This ideal block defines by
Verilog codes (Fig. 9-2).
In this project, 𝑁 = 213 and. m = 251 are assumed.
The reason for not increasing N was to not increase the simulation time.
Assuming the clock frequency is 50 MHz, 𝑓𝑖𝑛 is as follows:
251 251000000
𝑓𝑖𝑛 = × 50 𝑀𝐻𝑍 =
213 163.84
According to the output waveform and the time it takes 𝑡𝑑𝑒𝑙𝑎𝑦 , is 5 times greater than the clock.
1
𝑆𝑡𝑜𝑝𝑡𝑖𝑚𝑒 = 𝑁 × + 𝑡𝑑𝑒𝑙𝑎𝑦
𝑓𝑠
𝑆𝑡𝑜𝑝𝑡𝑖𝑚𝑒 = (213 ) × (20 𝑛𝑠) + (100 𝑛𝑠)
Finally, I set the strobepriod to 5% of the clock time, ie, 1ns. The lower the value, the more
accurate the simulation will be. After the simulation finishes, save the output waveform in a .csv
file and load in MATLAB, and calculate FFT and SFDR through the written code. Strobeperiod
is an indication for number of discreet sample of Output data. For example, in 40ns simulation
and for Strobeperiod =20 ns, 2 date could be extracted from Cadence to a .CSV file.
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2
Most of these concepts are related to DSP.
Test Bench:

Fig. 9-1: 8 bit ideal DAC.

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Fig. 9-2: 8 bit ideal DAC Verilog code.

Fig. 9-3: simulation time.

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 Fig. 9-4: Strobeperiod.

Simulation Results:

Fig. 9-5: Input signal (red) and ideal DAC output - Magnified.
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 Fig. 9-6: Extracting data for Matlab using calculator.

MATLAB Codes:
>> load FFT.txt
l=load('FFT.txt');
sgl=l(:,2);
N=8192;
m=251;
fs=50*10^6;
Ts=1/fs; % Ts=2*10^(-9)
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strobeperiod=1*10^(-9);
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dis0=Ts/strobeperiod; %dis0=20
dis=25;
for i=1:length(l)
if dis<=length(l)
signal(i)=sgl(dis);
dis=dis+dis0;
end
end
input_signal=signal(1:N);
lensi=length(input_signal);
fff_out = abs(fft(input_signal)); % fft
fff_out = fff_out(2:floor(length(fff_out))); % remove bin 1 (DC)
fff_out = 20*log10(abs(fff_out/max(fff_out)));
f = (0:length(fff_out)-1)/length(fff_out) ;
figure(1);
plot(f,fff_out)
ylabel('Output Spectrum (dB)');
xlabel('Normalized Frequency (fin/fs)');
fff_out2=fff_out(1:N/2);
[bin bin] = max(fff_out2);
dbfff_out2=[fff_out2(1:(bin-1)) fff_out2((bin+1):end)];
[bins bins] =max(dbfff_out2);
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SFDR = -dbfff_out2(bins);
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disp('SFDR')
disp(SFDR)
SFDR
14.6594

Fig. 9-7: Matlab codes.

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 Fig. 9-8: SFDR.

251000000
Results in Cadence for 𝐻𝑧 = 1.531982421875 𝑀𝐻𝑧: Using
163.84
measurement>spectrum

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Fig. 9-9: Spectrum in Cadence.

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Calculate SNR by Cadence Calculate ENOB by Cadence
10.47 dB 1.44 bit

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 10- DNL INL
For the test bench, the input signal is a triangle wave. Hence the ADC is 8 bit, for a ramp from 0
V 800 mV, there 28 quantized stages. Using this argument, we need the time 𝟐^𝟖 . 𝐂𝐥𝐨𝐜𝐤 for the
ramp. Strobeperiod is 20n for 256 sample in raising and 256 samples is falling.

Fig. 10-1: Input values.

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 Fig. 10-2: Transient setup.

Simulation Results:

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Fig. 10-3: Output Signal (red) and input signal.

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DNL Using Cadence Calculator:
Just for simplifying the process the rising part calculated, however it is necessary to consider
the falling part. Also because of transient behavior of the circuit in first 280ns (Fig. 10-5) no
codes extracted, therefore this duration eliminated by using the calculator option, shown in Fig.
10-4. For Matlab simulation, the mentioned superfluous data is removed.

Fig. 10-4: Cadence function for DNL (Just for rising).

Fig. 10-5: Superfluous data.

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 Fig. 10-5: DNL.

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