Combinational Logic Circuits

• The logic level at the output depends on the combination

of logic levels present at the inputs.
• A combinational circuit has no memory, so its output
depends only on the current value of its inputs.
 C.B. Pham 3-1
 Sum-of-Products Form (SOP)

• Sum  OR
• Product  AND
• Each of the sum-of-products expression
consists of two or more AND terms that
are ORed together.
• Note: one inversion sign cannot cover
more than one variable in a term. AB is
not allowed.

Q( A, B, C)  ABC  ABC  ABC  ABC Truth table

  m(1, 3, 4, 5)

 C.B. Pham 3-2

 Product-of-Sums Form (POS)

• Each of the product-of-sums expression consists of two

or more OR terms that are ANDed together.

Q A, B, C = A + B + C A + B + C A + B + C A + B + C
  M(0, 2, 6, 7)

SOP is more commonly used in logic

circuit simplification and design.

 C.B. Pham Truth table 3-3

 Simplifying Logic Circuits

Goal: reduce the logic circuit expression to a simpler form

so that fewer gates and connections are required to build
the circuit.

 C.B. Pham 3-4

 Algebraic Simplification

• Use the Boolean algebra theorems to help simplify the

expression for a logic circuit.
• Based on experience, often becomes a trial-and-error
process.
• No easy way to tell whether a simplified expression is in
its simplest form.

 C.B. Pham 3-5

 Designing Combinational Logic Circuits

• Step 1: Set up the truth table.

• Step 2: Write the AND term for each case where the
output is a 1.
• Step 3: Write the sum-of-products expression for the
output.
• Step 4: Simplify the output expression.
• Step 5: Implement the circuit for the final expression.

Problem: Design a logic circuit that has three input A, B

and C, and whose output will be HIGH only when a
majority of the inputs are HIGH.

 C.B. Pham 3-6

 Designing Combinational Logic Circuits

• Step 1: Set up the truth table. A B C F

0 0 0 0
• Step 2: Write the AND term 0 0 1 0
for each case where the 0 1 0 0
output is a 1. 0 1 1 1 ABC
1 0 0 0
1 0 1 1 ABC
1 1 0 1 ABC
1 1 1 1 ABC

• Step 3: Write the sum-of-products expression for the

output.
F  ABC  ABC  ABC  ABC
 C.B. Pham 3-7
 Designing Combinational Logic Circuits

• Step 4: Simplify the output expression.

F  ABC  ABC  ABC  ABC  ABC  ABC
     
 BC A  A  AC B  B  AB C  C  BC  AC  AB

• Step 5: Implement the circuit for the final expression.

F  BC  AC  AB

 C.B. Pham 3-8

 Designing Combinational Logic Circuits

Problem: Design a logic circuit that is to produce a HIGH

output when the voltage (represented by a four-bit binary
number ABCD) is greater than 6V.

• Step 1: Set up the truth table.

• Step 2: Write the AND term
for each case where the
output is a 1.
 C.B. Pham 3-9
 Designing Combinational Logic Circuits

• Step 3: Write the SOP

expression for the output.

• Step 4: Simplify the output expression.

 C.B. Pham 3-10

 Designing Combinational Logic Circuits

• Step 5: Implement the circuit for the final expression.

 C.B. Pham 3-11

 Karnaugh Map Method

• A graphical device to simplify a logic equation or to

convert a truth table to its corresponding logic circuit in a
simple, orderly process.
• Its practical usefulness is limited to six variables.

 Karnaugh map format

 C.B. Pham 3-12

 Karnaugh Map Method

• The K-map squares are labeled so that horizontally /

vertically adjacent squares differ only one variable.

 C.B. Pham 3-13

 Karnaugh Map Method

 C.B. Pham 3-14

 Looping

The expression for output X can be simplified by properly

combining those squares in the K map which contain 1s.
The process of combining these 1s is called looping.

 Looping a pair of adjacent 1s eliminates the variable that

appears in complemented and uncomplemented form.

 C.B. Pham 3-15

 Looping

 C.B. Pham 3-16

 Looping

 Looping a quad of adjacent 1s eliminates the two

variables that appears in both complemented and
uncomplemented form.

 C.B. Pham 3-17

 Looping

 C.B. Pham 3-18

 Looping

 Looping a octet of adjacent 1s eliminates the three

variables that appears in both complemented and
uncomplemented form.

 C.B. Pham 3-19

 Looping

 C.B. Pham 3-20

 Complete Simplification Process
• Step 1: Construct the K map and places 1s in those squares
corresponding to the 1s in the truth table.
• Step 2: Examine the map for adjacent 1s and loop those 1s
which are not adjacent to any other 1s.
• Step 3: Look for those 1s which are adjacent to only one other
1. Loop any pair containing such a 1.
• Step 4: Loop any octet even when it contains some 1s that
have already been looped.
• Step 5: Loop any quad that contains one or more 1s that have
not already been looped, making sure to use the minimum
number of loops.
• Step 6: Loop any pairs necessary to include any 1s have not
already been looped, making sure to use the minimum
number of loops.
• Step 7: Form the OR sum of all the terms generated by each
loop.
 C.B. Pham 3-21
 Complete Simplification Process

 C.B. Pham 3-22

 Complete Simplification Process

 C.B. Pham 3-23

 Complete Simplification Process

 C.B. Pham 3-24

 Don’t-Care Conditions
• Some logic circuits can be designed so that there are
certain input conditions for which there are no specified
output levels.
• A circuit designer is free to make the output for any don’t
care condition either a 0 or a 1 in order to produce the
simplest output expression.

 C.B. Pham 3-25

 Don’t-Care Conditions
Problem: design a logic circuit that controls an elevator
door in a 3-story building.

• M = 1 when the elevator is

moving.
• F1 = 1 when the elevator is lined
up level with the first floor.
• F2 = 1 when the elevator is lined
up level with the second floor.
• F3 = 1 when the elevator is lined
up level with the third floor.
• OPEN = 1 when the elevator door
is to be opened.
 C.B. Pham 3-26
 Don’t-Care Conditions

 C.B. Pham 3-27

 Exclusive-OR & Exclusive-NOR circuits

These are 2 special logic circuits that occur quite often in

digital systems.

 C.B. Pham 3-28

 Exclusive-OR & Exclusive-NOR circuits
x1 x0 y1 y0 z
0 0 0 0 1
Problem: design a logic circuit
0 0 0 1 0
that the output will be HIGH only 0 0 1 0 0
when the two inputs (binary 0 0 1 1 0
numbers X1X0 and Y1Y0) are 0 1 0 0 0
equal. 0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
 C.B. Pham 1 1 1 1 1 3-29
 Data selector / multiplexer

 C.B. Pham 3-30

 Demultiplexer / data distributors

 C.B. Pham 3-31

 Basic Characteristics of Digital ICs

• Digital ICs are a collection of resistors, diodes and

transistor fabricated on a single piece of semiconductor
material called a substrate, which is commonly referred
to as a chip.
• The chip is enclosed in a package.
• Dual-in-line package (DIP)

 C.B. Pham 3-32

 Integrated Circuits

Complexity Number of Gates

Small-scale integration(SSI) <12
Medium-scale integration(MSI) 12 to 99
Large-scale integration(LSI) 100 to 9999
Very large-scale integration(VLSI) 10,000 to 99,999
Ultra large-scale integration(ULSI) 100,000 to 999,999
Giga-scale integration (GSI) 1,000,000 or more

IC families: TTL and CMOS, dominating the field of SSI

and MSI devices.
 C.B. Pham 3-33
 Power and Ground

• To use digital IC, it is necessary to make proper

connection to the IC pins.
• Power: labeled Vcc for the TTL circuit (VCC: normally 5V),
labeled VDD for CMOS circuit (VDD: from 3 to 18V).
• Ground.
• For TTL, logic LOW: 0-0,8V, logic HIGH: 2-5V
• For CMOS, logic LOW : 0-1.5V, logic HIGH: 3.5-5V
• Unconnected Inputs: also called floating inputs.
 A floating TTL input acts like a logic HIGH, but
measures a DC level of between 1.4 and 1.8V.
 A CMOS input cannot be left floating.

 C.B. Pham 3-34

 Logic-Circuit Connection Diagrams

A connection diagram shows all electrical connections, pin

numbers, IC numbers, component values, signal names,
and power supply voltages.

 C.B. Pham 3-35