There is a tremendous variety of Historically the distinction

products, from single-chip between architecture and

microcomputers costing a few organization has not been an
dollars to supercomputers costing important one.
tens of millions of dollars that can
a. True
rightly claim the name
"computer". b. False
a. True
b. False A particular architecture may span
many years and encompass a
The variety of computer products
number of different computer
is exhibited only in cost.
models, its organization changing
a. True with changing technology.
b. False a. True
Computer organization refers to b. False
attributes of a system visible to
A microcomputer architecture and
the programmer.
organization relationship is not
a. True very close.
b. False a. True
Changes in computer technology b. False
are finally slowing down.
Changes in technology not only
a. True influence organization but also
result in the introduction of more
b. False
powerful and more complex
The textbook for this course is architectures.
about the structure and function
a. True
of computers.
b. False
a. True
The hierarchical nature of
b. False
complex systems is essential to
The number of bits used to both their design and their
represent various data types is an description.
example of an architectural
a. True
attribute.
b. False
a. True
Both the structure and functioning
b. False
of a computer are, in essence,
Interfaces between the computer simple.
and peripherals is an example of
a. True
an organizational attribute.
b. False
a. True
b. False
A computer must be able to d. memory technology used
process, store, move, and control
_________ attributes include
data.
hardware details transparent to
a. True the programmer.
b. False a. Interface
When data are moved over longer b. Organizational
distances, to or from a remote
c. Memory
device, the process is known as
data transport. d. Architectural
a. True It is a(n) _________ design issue
whether a computer will have a
b. False
multiply instruction.
The IAS is the prototype of all
a. architectural
subsequent general-purpose
computers. b. memory
a. True c. elementary
b. False d. organizational
The major drawback of the EDVAC
was that it had to be programmed
Computer technology is changing
manually by setting switches and
at a __________ pace.
plugging and unplugging cables.
a. slow
a. True
b. slow to medium
b. False
c. rapid
d. non-existent
It is a(n) _________ issue whether
Computer _________ refers to those the multiply instruction will be
attributes that have a direct implemented by a special multiply
impact on the logical execution of unit or by a mechanism that
a program. makes repeated use of the add
unit of the system.
a. organization
a. architectural
b. specifics
b. memory
c. design
c. mechanical
d. architecture
d. organizational
Architectural attributes include
_________ . A __________ system is a set of
interrelated subsystems.
a. I/O mechanisms
a. secondary
b. control signals
b. hierarchical
c. interfaces
c. complex
d. functional b. system bus
An I/O device is referred to as a c. data transport
_______.
d. control device
a. CPU
A _________ is a mechanism that
b. control device provides for communication
among CPU, main memory, and
c. peripheral
I/O.
d. register
a. system interconnection
When data are moved over longer
b. CPU interconnection
distances, to or from a remote
device, the process is known as c. peripheral
__________.
d. processor
a. data communications
_____ provide storage internal to
b. registering the CPU.
c. structuring a. Control units
d. data transport b. ALUs
The _________ stores data. c. Main memory
a. system bus d. Registers
b. I/O The __________ performs the
computer's data processing
c. main memory
functions.
d. control unit
a. Register
The IAS operates by repetitively
b. CPU interconnection
performing an instruction cycle.
c. ALU
a. True
d. system bus
b. False
The world's first general-purpose
The __________ moves data
electronic digital computer was
between the computer and its
designed and constructed at The
external environment.
Ohio State University.
a. data transport
a. True
b. I/O
b. False
c. register
d. CPU interconnection
John Mauchly and John Eckert
A common example of system designed the ENIAC.
interconnection is by means of a
a. True
_______.
b. False
a. register
Backward compatible means that b. False
the programs written for the older
machines can be executed on the
new machine. Designers wrestle with the
challenge of balancing processor
a. True
performance with that of main
b. False memory and other computer
components.
A vacuum tube is a solid-state
device made from silicon. a. True
a. True b. False
b. False The Intel x86 evolved from RISC
design principles and is used in
Computers are classified into
embedded systems.
generations based on the
fundamental hardware technology a. True
employed.
b. False
a. True
A common measure of
b. False performance for a processor is the
rate at which instructions are
System software was introduced
executed, expressed as billions of
in the third generation of
instructions per seconds (BIPS).
computers.
a. True
a. True
b. False
b. False
The ______ was the world's first
A wafer is made of silicon and is
general-purpose electronic digital
broken up into chips which
computer.
consists of many gates and/or
memory cells plus a number of a. UNIVAC
input and output attachment
b. MARK IV
points.
c. ENIAC
a. True
d. Hollerith's Counting Machine
b. False
The Electronic Numerical
IBM's System/360 was the
Integrator and Computer project
industry's first planned family of
was a response to U.S. needs
computers.
during _________.
a. True
a. the Civil War
b. False
b. the French-American War
Intel's 4004 was the first chip to
c. World War I
contain all of the components of a
CPU on a single chip. d. World War II
a. True The ENIAC used __________.
a. vacuum tubes During the _________ the opcode of
the next instruction is loaded into
b. integrated circuits
the IR and the address portion is
c. IAS loaded into the MAR.
An I/O module cannot exchange a. execute cycle
data directly with the processor.
b. fetch cycle
a. True
c. instruction cycle
b. False
d. clock cycle
The ENIAC is an example of a
Second generation computers
________ generation computer.
used _____.
a. first
a. integrated circuits
b. second
b. Transistors
c. third
c. vacuum tubes
d. fourth
d. large-scale integration
The __________ interprets the
The __________ defines the third
instructions in memory and
generation of computers.
causes them to be executed.
a. integrated circuit
a. main memory
b. vacuum tube
b. control unit
c. transistor
c. I/O
d. VLSI
d. arithmetic and logic unit
The use of multiple processors on
The memory of the IAS consists of
the same chip is referred to as
1000 storage locations called
______ and provides the potential
__________.
to increase performance without
a. opcodes increasing the clock rate.
b. wafers a. multicore
c. VLSIs b. GPU
d. words c. data channels
The __________ contains the 8-bit d. MPC
opcode instruction being
With the __________, Intel
executed.
introduced the use of superscalar
a. memory buffer register techniques that allow multiple
instructions to execute in parallel.
b. instruction buffer register
a. Core
c. instruction register
b. 8080
d. memory address register
c. 80486
d. Pentium a. data and instructions are stored
in a single read-write memory
The __________ measures the
ability of a computer to complete b. the contents of this memory are
a single task. addressable by location
a. clock speed c. execution occurs in a sequential
fashion
b. speed metric
d. all of the above
c. execute cycle
The TL supports which of the
d. cycle time
following address spaces?
It is not possible to connect I/O
a. memory
controllers directly onto the
system bus. b. I/O
a. True c. message
b. False d. all of the above
ARM processors are designed to With asynchronous timing the
meet the needs of _________. occurrence of events on the bus is
determined by a clock.
a. embedded real-time systems
a. True
b. application platforms
b. False
c. secure applications
The interconnection structure
d. all of the above
must support which transfer?
One increment, or pulse, of the
a. memory to processor
system clock is referred to as a
_________. b. processor to memory
a. clock tick c. I/O to or from memory
b. cycle time d. all of the above
c. clock rate The data lines provide a path for
moving data among system
d. cycle speed
modules and are collectively
The __________ are used to called the _________.
designate the source or
a. control bus
destination of the data on the
data bus. b. address bus
a. system lines c. data bus
b. data lines d. system bus
c. control lines The unit of transfer at the link
layer is a phit and the unit transfer
d. address lines
at the physical layer is a flit.
The von Neumann architecture is
a. True
based on which concept?
b. False d. John Eckert
A key characteristic of a bus is Each data path consists of a pair
that it is not a shared transmission of wires (referred to as a
medium. __________) that transmits data
one bit at a time.
a. True
a. lane
b. False
b. path
Interrupts do not improve
processing efficiency. c. line
a. True d. bus
b. False A(n) _________ is generated by
some condition that occurs as a
A(n) _________ is generated by a
result of an instruction execution.
failure such as power failure or
memory parity error. a. timer interrupt
a. I/O interrupt b. I/O interrupt
b. hardware failure interrupt c. program interrupt
c. timer interrupt d. hardware failure interrupt
d. program interrupt A ____ is the high-level set of rules
for exchanging packets of data
The basic function of a computer
between devices.
is to execute programs.
a. bus
a. True
b. protocol
b. False
c. packet
The processing required for a
single instruction is called a(n) d. QPI
__________ cycle.
The QPI _________ layer is used to
a. execute determine the course that a
packet will traverse across the
b. fetch
available system interconnects.
c. instruction
a. link
d. packet
b. protocol
Virtually all contemporary
c. routing
computer designs are based on
concepts developed by __________ d. physical
at the Institute for Advanced
A sequence of codes or
Studies, Princeton.
instructions is called _______.
a. John Maulchy
a. software
b. John von Neumann
b. memory
c. Herman Hollerith
c. an interconnect
d. a register The method of using the same
lines for multiple purposes is
A bus that connects major
known as time multiplexing.
computer components (processor,
memory, I/O) is called a a. True
__________.
b. False
a. system bus
In general, the more devices
b. address bus attached to the bus, the greater
the bus length and hence the
c. data bus
greater the propagation delay.
d. control bus
a. True
The _____ receives read and write
b. False
requests from the software above
the TL and creates request Computer systems contain a
packets for transmission to a number of different buses that
destination via the link layer. provide pathways between
components at various levels of
a. transaction layer
the computer system hierarchy.
b. root layer
a. True
c. configuration layer
b. False
d. transport layer
Program execution consists of
A key requirement for PCIe is high repeating the process of
capacity to support the needs of instruction fetch and instruction
higher data rate I/O devices such execution.
as Gigabit Ethernet.
a. True
a. True
b. False
b. False
At a top level, a computer consists
Because all devices on a of CPU, memory, and I/O
synchronous bus are tied to a components.
fixed clock rate, the system
a. True
cannot take advantage of
advances in device performance. b. False
a. True No single technology is optimal in
satisfying the memory
b. False
requirements for a computer
Timing refers to the way in which system.
events are coordinated on the
a. True
bus.
b. False
a. True
A typical computer system is
b. False
equipped with a hierarchy of
memory subsystems, some
internal to the system and some Secondary memory is used to
external. store program and data files and
is usually visible to the
a. True
programmer only in terms of
b. False individual bytes or words.
External memory is often equated a. True
with main memory.
b. False
a. True
The L1 cache is slower than the L3
b. False cache.
The processor requires its own a. True
local memory.
b. False
a. True
With write back updates are made
b. False only in the cache.
Cache is not a form of internal a. True
memory.
b. False
a. True
It has become possible to have a
b. False cache on the same chip as the
processor.
The unit of transfer must equal a
word or an addressable unit. a. True
a. True b. False
b. False All of the Pentium processors
include two on-chip L1 caches,
Both sequential access and direct
one for data and one for
access involve a shared read-write
instructions.
mechanism.
a. True
a. True
b. False
b. False
Cache design for HPC is the same
In a volatile memory, information
as that for other hardware
decays naturally or is lost when
platforms and applications.
electrical power is switched off.
a. True
a. True
b. False
b. False
__________ refers to whether
To achieve greatest performance
memory is internal or external to
the memory must be able to keep
the computer.
up with the processor.
a. Location
a. True
b. Access
b. False
c. Hierarchy
d. Tag For random-access memory,
________ is the time from the
Internal memory capacity is
instant that an address is
typically expressed in terms of
presented to the memory to the
_________.
instant that data have been stored
a. hertz or made available for use.
b. nanos a. memory cycle time
c. bytes b. direct access
d. LOR c. transfer rate
For internal memory, the d. access time
__________ is equal to the number
The ________ consists of the access
of electrical lines into and out of
time plus any additional time
the memory module.
required before a second access
a. access time can commence.
b. unit of transfer a. latency
c. capacity b. memory cycle time
d. memory ratio c. direct access
DRAM is much costlier than SRAM. d. transfer rate
a. True A portion of main memory used as
a buffer to hold data temporarily
b. False
that is to be read out to disk is
referred to as a _________.

"Memory is organized into records a. disk cache

and access must be made in a
b. latency
specific linear sequence" is a
description of __________. c. virtual address
a. sequential access d. miss
b. direct access
c. random access A line includes a _________ that
identifies which particular block is
d. associative
currently being stored.
individual blocks or records have a
a. cache
unique address based on physical
location with ______. b. hit
a. associative c. tag
b. physical access d. locality
c. direct access __________ is the simplest mapping
technique and maps each block of
d. sequential access
main memory into only one
possible cache line.
a. Direct mapping b. hit
b. Associative mapping c. line
c. Set associative mapping d. tag
d. None of the above A logical cache stores data using
______.
When using the __________
technique all write operations a. physical addresses
made to main memory are made
b. virtual addresses
to the cache as well.
c. random addresses
a. write back
d. none of the above
b. LRU
The basic element of a
c. write through
semiconductor memory is the
d. unified cache memory cell.
The key advantage of the a. True
__________ design is that it
b. False
eliminates contention for the
cache between the instruction A characteristic of ROM is that it is
fetch/decode unit and the volatile.
execution unit.
a. True
a. logical cache
b. False
b. split cache
RAM must be provided with a
c. unified cache constant power supply.
d. physical cache a. True
The Pentium 4 _________ b. False
component executes micro-
The two traditional forms of RAM
operations, fetching the required
used in computers are DRAM and
data from the L1 data cache and
SRAM.
temporarily storing results in
registers. a. True
a. fetch/decode unit b. False
b. out-of-order execution logic A static RAM will hold its data as
long as power is supplied to it.
c. execution unit
a. True
d. memory subsystem
b. False
Nonvolatile means that power
In reference to access time to a
must be continuously supplied to
two-level memory, a _________
the memory to preserve the bit
occurs if an accessed word is not
values.
found in the faster memory.
a. True
a. miss
b. False The SRAM on the CDRAM cannot
be used as a buffer to support the
The advantage of RAM is that the
serial access of a block of data.
data or program is permanently in
main memory and need never be a. True
loaded from a secondary storage
b. False
device.
a. True
Which properties do all
b. False
semiconductor memory cells
Semiconductor memory comes in share?
packaged chips.
a. they exhibit two stable states
a. True which can be used to represent
binary 1 and 0
b. False
b. they are capable of being
All DRAMs require a refresh
written into to set the state
operation.
c. they are capable of being read
a. True
to sense the state
b. False
d. all of the above
A number of chips can be grouped
One distinguishing characteristic
together to form a memory bank.
of memory that is designated as
a. True _________ is that it is possible to
both to read data from the
b. False
memory and to write new data
An error-correcting code enhances into the memory easily and
the reliability of the memory at rapidly.
the cost of added complexity.
a. RAM
a. True
b. ROM
b. False
c. EPROM
RDRAM is limited by the fact that
d. EEPROM
it can only send data to the
processor once per bus clock Which of the following memory
cycle. types are nonvolatile?
a. True a. erasable PROM
b. False b. programmable ROM
The prefetch buffer is a memory c. flash memory
cache located on the RAM chip.
d. all of the above
a. True
In a _________, binary values are
b. False stored using traditional flip-flop
logic-gate configurations.
a. ROM
b. SRAM at the full speed of the
processor/memory bus without
c. DRAM
imposing wait states.
d. RAM
a. DDR-DRAM
A __________ contains a permanent
b. SDRAM
pattern of data that cannot be
changed, is nonvolatile, and c. CDRAM
cannot have new data written into
d. none of the above
it.
________ can send data to the
a. RAM
processor twice per clock cycle.
b. SRAM
a. CDRAM
c. ROM
b. SDRAM
d. flash memory
c. DDR-DRAM
With _________ the microchip is
d. RDRAM
organized so that a section of
memory cells are erased in a
single action.
a. flash memory
__________ increases the data
b. SDRAM transfer rate by increasing the
c. DRAM operational frequency of the RAM
chip and by increasing the
d. EEPROM prefetch buffer from 2 bits to 4
bits per chip.
__________ can be caused by harsh
environmental abuse, a. DDR2
manufacturing defects, and wear.
b. RDRAM
a. SEC errors
c. CDRAM
b. Hard errors
d. DDR3
c. Syndrome errors
_______ increases the prefetch
d. Soft errors buffer size to 8 bits.
_________ can be caused by power a. CDRAM
supply problems or alpha
particles. b. RDRAM

a. Soft errors c. DDR3

b. AGT errors d. all of the above

c. Hard errors Theoretically, a DDR module can

transfer data at a clock rate in the
d. SEC errors range of __________ MHz.
The _________ exchanges data with a. 200 to 600
the processor synchronized to an
external clock signal and running b. 400 to 1066
c. 600 to 1400 b. False
d. 800 to 1600 A bit near the center of a rotating
disk travels past a fixed point
A DDR3 module transfers data at
slower than a bit on the outside.
a clock rate of __________ MHz.
a. True
a. 600 to 1200
b. False
b. 800 to 1600
The disadvantage of using CAV is
c. 1000 to 2000
that individual blocks of data can
d. 1500 to 3000 only be directly addressed by
track and sector.
The ________ enables the RAM chip
to preposition bits to be placed on a. True
the data bus as rapidly as
b. False
possible.
A removable disk can be removed
a. flash memory
and replaced with another disk.
b. Hamming code
a. True
c. RamBus
b. False
d. buffer
The head must generate or sense
an electromagnetic field of
sufficient magnitude to write and
read properly.
Magnetic disks are the foundation a. True
of external memory on virtually all
computer systems. b. False

a. True
b. False The transfer time to or from the
disk does not depend on the
During a read or write operation, rotation speed of the disk.
the head rotates while the platter
beneath it stays stationary. a. True

a. True b. False

b. False RAID is a set of physical disk

drives viewed by the operating
The width of a track is double that system as a single logical drive.
of the head.
a. True
a. True
b. False
b. False
RAID level 0 is not a true member
There are typically hundreds of of the RAID family because it does
sectors per track and they may be not include redundancy to
either fixed or variable lengths. improve performance.
a. True a. True
b. False d. a solid state drive
Because data are striped in very Data are transferred to and from
small strips, RAID 3 cannot the disk in __________.
achieve very high data transfer
a. tracks
rates.
b. gaps
a. True
c. sectors
b. False
d. pits
The SSDs now on the market use
a type of semiconductor memory In most contemporary systems
referred to as flash memory. fixed-length sectors are used, with
_________ bytes being the nearly
a. True
universal sector size.
b. False
a. 64
SSD performance has a tendency
b. 128
to speed up as the device is used.
c. 256
a. True
d. 512
b. False
Scanning information at the same
Flash memory becomes unusable
rate by rotating the disk at a fixed
after a certain number of writes.
speed is known as the _________.
a. True
a. constant angular velocity
b. False
b. magnetoresistive
Adjacent tracks are separated by
c. rotational delay
______.
d. constant linear velocity
a. sectors
The disadvantage of _________ is
b. gaps
that the amount of data that can
c. pits be stored on the long outer tracks
is only the same as what can be
d. heads
stored on the short inner tracks.
Greater ability to withstand shock
a. SSD
and damage, improvement in the
uniformity of the magnet film b. CAV
surface to increase disk reliability,
c. ROM
and a significant reduction in
overall surface defects to help d. CLV
reduce read-write errors, are all
A __________ disk is permanently
benefits of ___________.
mounted in the disk drive, such as
a. magnetic read and write the hard disk in a personal
mechanisms computer.
b. platters a. nonremovable
c. the glass substrate b. movable-head
c. double sided
d. removable RAID level ________ has the
highest disk overhead of all RAID
When the magnetizable coating is
types.
applied to both sides of the platter
the disk is then referred to as a. 0
_________.
b. 1
a. multiple sided
c. 3
b. substrate
d. 5
c. double sided
A _________ is a high-definition
d. all of the above video disk that can store 25
Gbytes on a single layer on a
The set of all the tracks in the
single side.
same relative position on the
platter is referred to as a a. DVD
_________.
b. DVD-R
a. floppy disk
c. DVD-RW
b. single-sided disk
d. Blu-ray DVD
c. sector
________ is when the disk rotates
d. cylinder more slowly for accesses near the
outer edge than for those near the
The sum of the seek time and the
center.
rotational delay equals the
_________, which is the time it a. Constant angular velocity (CAV)
takes to get into position to read
b. Magnetoresistive
or write.
c. Constant linear velocity (CLV)
a. access time
d. Seek time
b. gap time
The areas between pits are called
c. transfer time
_________.
d. constant angular velocity
a. lands
__________ is the standardized
b. sectors
scheme for multiple-disk database
design. c. cylinders
a. RAID d. strips
b. CAV A set of I/O modules is a key
element of a computer system.
c. CLV
a. True
d. SSD
b. False
I/O channels are commonly seen
on microcomputers, whereas I/O
controllers are used on The rotating interrupt mode allows
mainframes. the processor to inhibit interrupts
from certain devices.
a. True
a. True
b. False
b. False
Because the 82C55A is
It is the responsibility of the
programmable via the control
processor to periodically check
register, it can be used to control
the status of the I/O module until
a variety of simple peripheral
it finds that the operation is
devices.
complete.
a. True
a. True
b. False
b. False
With isolated I/O there is a single
address space for memory When large volumes of data are to
locations and I/O devices. be moved, a more efficient
technique is direct memory access
a. True
(DMA).
b. False
a. True
A disadvantage of memory-
b. False
mapped I/O is that valuable
memory address space is used up. An I/O channel has the ability to
execute I/O instructions, which
a. True
gives it complete control over I/O
b. False operations.
The disadvantage of the software a. True
poll is that it is time consuming.
b. False
a. True
A multipoint external interface
b. False provides a dedicated line between
the I/O module and the external
With a daisy chain the processor
device.
just picks the interrupt line with
the highest priority. a. True
a. True b. False
b. False A Thunderbolt compatible
peripheral interface is no more
Bus arbitration makes use of
complex than that of a simple USB
vectored interrupts.
device.
a. True
a. True
b. False
b. False
The _________ contains logic for
performing a communication
function between the peripheral An I/O module that is quite
and the bus. primitive and requires detailed
control is usually referred to as an
a. I/O channel
_________.
b. I/O module
a. I/O command
c. I/O processor
b. I/O controller
d. I/O command
c. I/O channel
The most common means of
d. I/O processor
computer/user interaction is a
__________. The _________ command causes
the I/O module to take an item of
a. keyboard/monitor
data from the data bus and
b. mouse/printer subsequently transmit that data
item to the peripheral.
c. modem/printer
a. control
d. monitor/printer
b. test
The end user is concerned mainly
with the computer's architecture. c. read
a. True d. write
b. False The ________ command is used to
activate a peripheral and tell it
what to do.
The I/O function includes a
a. control
_________ requirement to
coordinate the flow of traffic b. test
between internal resources and
c. read
external devices.
d. write
a. cycle
b. status reporting
________ is when the DMA module
c. control and timing
must force the processor to
d. data suspend operation temporarily.
An I/O module that takes on most a. Interrupt
of the detailed processing burden,
b. Thunderbolt
presenting a high-level interface
to the processor, is usually c. Cycle stealing
referred to as an _________.
d. Lock down
a. I/O channel
The 8237 DMA is known as a
b. I/O command _________ DMA controller.
c. I/O controller a. command
d. device controller b. cycle stealing
c. interrupt A ________ is used to connect
storage systems, routers, and
d. fly-by
other peripheral devices to an
________ is a digital display InfiniBand switch.
interface standard now widely
a. target channel adapter
adopted for computer monitors,
laptop displays, and other b. InfiniBand switch
graphics and video interfaces.
c. host channel adapter
a. DisplayPort
d. subnet
b. PCI Express
A ________ connects InfiniBand
c. Thunderbolt subnets, or connects an InfiniBand
switch to a network such as a
d. InfiniBand
local area network, wide area
The _____ layer is the key to the network, or storage area network.
operation of Thunderbolt and what
a. memory controller
makes it attractive as a high-
speed peripheral I/O technology. b. TCA
a. cable c. HCA
b. application d. router
c. common transport Scheduling and memory
management are the two OS
d. physical
functions that are most relevant
The Thunderbolt protocol to the study of computer
_________ layer is responsible for organization and architecture.
link maintenance including hot-
a. True
plug detection and data encoding
to provide highly efficient data b. False
transfer.
The most important system
a. cable program is the OS.
b. application a. True
c. common transport b. False
d. physical The ABI is the boundary between
hardware and software.
a. True
The ________ contains I/O protocols
that are mapped on to the b. False
transport layer.
The decimal system has a radix of
a. cable 100.
b. application a. True
c. common transport b. False
d. physical
The OS must determine how much a. True
processor time is to be devoted to
b. False
the execution of a particular user
program. The Pentium II includes hardware
for both segmentation and paging.
a. True
a. True
b. False
b. False
With a batch operating system the
user does not have direct access ARM provides a versatile virtual
to the processor. memory system architecture that
can be tailored to the needs of the
a. True
embedded system designer.
b. False
a. True
Privileged instructions are certain
b. False
instructions that are designated
special and can be executed only Managers are users of domains
by the monitor. that must observe the access
permissions of the individual
a. True
sections and/or pages that make
b. False up that domain.
Uniprogramming is the central a. True
theme of modern operating
b. False
systems.
The __________ is a program that
a. True
controls the execution of
b. False application programs and acts as
an interface between applications
Both batch multiprogramming and
and the computer hardware.
time sharing use
multiprogramming. a. job control language
a. True b. operating system
b. False c. batch system
An interrupt is a hardware- d. nucleus
generated signal to the processor.
Facilities and services provided by
a. True the OS that assist the programmer
in creating programs are in the
b. False
form of _________ programs that
Swapping is an I/O operation. are not actually part of the OS but
are accessible through the OS.
a. True
a. utility
b. False
b. multitasking
With demand paging it is
necessary to load an entire c. JCL
process into main memory.
d. logical address
The _________ defines the d. privileged instruction
repertoire of machine language
A _________ is a special type of
instructions that a computer can
programming language used to
follow.
provide instructions to the
a. ABI monitor.
b. API a. job control language
c. HLL b. multiprogram
d. ISA c. kernel
There are 50 tens in the number d. utility
509.
The _________ scheduler
a. True determines which programs are
admitted to the system for
b. False
processing.
The _________ defines the system
a. long-term
call interface to the operating
system and the hardware b. medium-term
resources and services available
c. short-term
in a system through the user
instruction set architecture. d. I/O
a. HLL The ________ scheduler is also
known as the dispatcher.
b. API
a. long-term
c. ABI
b. medium-term
d. ISA
c. short-term
The ________ gives a program
access to the hardware resources d. I/O
and services available in a system
A _________ is an actual location in
through the user instruction set
main memory.
architecture supplemented with
high-level language library calls. a. logical address
a. JCL b. partition address
b. ISA c. base address
c. ABI d. physical address
d. API ________ is when the processor
spends most of its time swapping
A _________ system works only one
pages rather than executing
program at a time.
instructions.
a. batch
a. Swapping
b. uniprogramming
b. Thrashing
c. kernel
c. Paging
d. Multitasking Our primary counting system is
based on binary digits to
Virtual memory schemes make
represent numbers.
use of a special cache called a
________ for page table entries. a. True
a. TLB b. False
b. HLL Negative powers of 10 are used to
represent the positions of the
c. VMC
numbers for decimal fractions.
d. SPB
a. True
With _________ the virtual address
b. False
is the same as the physical
address. A number with both an integer
and fractional part has digits
a. unsegmented unpaged memory
raised to both positive and
b. unsegmented paged memory negative powers of 10.
c. segmented unpaged memory a. True
d. segmented paged memory b. False
The decimal system is a special In any number, the rightmost digit
case of a positional number is referred to as the most
system with radix 10 and with significant digit.
digits in the range 0 through 9.
a. True
a. True
b. False
b. False
A number cannot be converted
A _________ is a collection of from binary notation to decimal
memory regions. notation.
a. APX a. True
b. nucleus b. False
c. domain
d. page table Although convenient for
computers, the binary system is
The OS maintains a __________ for
exceedingly cumbersome for
each process that shows the
human beings.
frame location for each page of
the process. a. True
a. kernel b. False
b. page table A nibble is a grouping of four
decimal digits.
c. TLB
a. True
d. logical address
b. False
Hexadecimal notation is only used d. 2
for representing integers.
Which of the following is correct?
a. True
a. 25 = (2 x 102) + (5 x 101)
b. False
b. 289 = (2 x 103) + (8 x 101) +
It is extremely easy to convert (9 x 100)
between binary and hexadecimal
c. 7523 = (7 x 103) + (5 x 102) +
notation.
(2 x 101) + (3 x 100)
a. True
d. 0.628 = (6 x 10-3) + (2 x 10-2)
b. False + (8 x 10-1)
Hexadecimal notation is more In the number 3109, the 3 is
compact than binary notation. referred to as the _________.
a. True a. most significant digit
b. False b. least significant digit
A sequence of hexadecimal digits c. radix
can be thought of as representing
d. base
an integer in base 10.
In the number 3109, the 9 is
a. True
referred to as the _________.
b. False
a. most significant digit
Because of the inherent binary
b. least significant digit
nature of digital computer
components, all forms of data c. radix
within computers are represented
d. base
by various binary codes.
Numbers in the binary system are
a. True
represented to the _________.
b. False
a. base 0
The decimal system has a base of
b. base 1
______.
c. base 2
a. 0
d. base 10
b. 10
ARM processors support data
c. 100
types of 8 (byte), 16 (halfword),
d. 1000 and 32 (word) bits in length.
Which digit represents "hundreds" a. True
in the number 8732?
b. False
a. 8
Hexadecimal has a base of
b. 7 _________.
c. 3 a. 2
b. 8 b. False
c. 10 Another term for "base" is
__________.
d. 16
a. radix
The binary string 110111100001
is equivalent to __________. b. integer
a. DE116 c. position
b. C7816 d. digit
c. FF6416 In the number 472.156 the 2 is
the _________.
d. B8F16
a. most significant digit
The _________ system uses only
the numbers 0 and 1. b. radix point
a. positional c. least significant digit
b. binary d. none of the above
c. hexadecimal Binary 0101 is hexadecimal
_________.
d. decimal
a. 0
Decimal "10" is __________ in
binary. b. 5
a. 1000 c. A
b. 0010 d. 10
c. 1010 The operation of the digital
computer is based on the storage
d. 0001
and processing of binary data.
Decimal "10" is _________ in
a. True
hexadecimal.
b. False
a. 1
Claude Shannon, a research
b. A
assistant in the Electrical
c. 0 Engineering Department at M.I.T.,
proposed the basic principles of
d. FF
Boolean algebra.
Four bits is called a _________.
a. True
a. radix point
b. False
b. byte
In the absence of parentheses, the
c. nibble AND operation takes precedence
over the OR operation.
d. binary digit
a. True
Addresses are a form of data.
b. False
a. True
Logical functions are implemented b. False
by the interconnection of
In general, a decoder has n inputs
decoders.
and 2n outputs.
a. True
a. True
b. False
b. False
The delay by the propagation time
Combinational circuits are often
of signals through the gate is
referred to as "memoryless"
known as the gate delay.
circuits because their output
a. True depends only on their current
input and no history of prior inputs
b. False
is retained.
A combinational circuit consists of
a. True
n binary inputs and m binary
outputs. b. False
a. True Binary addition is exactly the
same as Boolean algebra.
b. False
a. True
Any Boolean function can be
implemented in electronic form as b. False
a network of gates.
Events in the digital computer are
a. True synchronized to a clock pulse so
that changes occur only when a
b. False
clock pulse occurs.
A Boolean function can be realized
a. True
in the sum of products (SOP) form
but not in the product of sums b. False
(POS) form.
A register is a digital circuit used
a. True within the CPU to store one or
more bits of data.
b. False
a. True
"Don't care" conditions are when
certain combinations of values of b. False
variables never occur, and
The operand ________ yields true if
therefore the corresponding
and only if both of its operands
output never occurs.
are true.
a. True
a. XOR
b. False
b. OR
The value to be loaded into the
c. AND
program counter can come from a
binary counter, the instruction d. NOT
register, or the output of the ALU.
The operation _________ yields true
a. True if either or both of its operands
are true.
a. NOT a. DeMorgan
b. AND b. Quine-McCluskey
c. NAND c. Karnaugh map
d. OR d. Boole-Shannon
The unary operation _________ ________ are used in digital circuits
inverts the value of its operand. to control signal and data routing.
a. OR a. Multiplexers
b. NOT b. Program counters
c. NAND c. Flip-flops
d. XOR d. Gates
Counters can be designated as ______ is implemented with
_________. combinational circuits.
a. asynchronous a. Nano memory
b. synchronous b. Random access memory
c. both asynchronous and c. Read only memory
synchronous
d. No memory
d. neither asynchronous or
A high-level language expresses
synchronous
operations in a basic form
Which of the following is a involving the movement of data to
functionally complete set? or from registers.
a. AND, NOT a. True
b. NOR b. False
c. AND, OR, NOT The ________ exists in one of two
states and, in the absence of
d. all of the above
input, remains in that state.
A _______ is an electronic circuit
a. assert
that produces an output signal
that is a simple Boolean operation b. complex PLD
on its input signals.
c. decoder
a. gate
d. flip-flop
b. decoder
The ________ flip-flop has two
c. counter inputs and all possible
combinations of input values are
d. flip-flop
valid.
For more than four variables an
a. J-K
alternative approach is a tabular
technique referred to as the b. D
_________ method.
c. S-R
d. clocked S-R One boundary where the
computer designer and the
A _________ accepts and/or
computer programmer can view
transfers information serially.
the same machine is the machine
a. S-R latch instruction set.
b. shift register a. True
c. FPGA b. False
d. parallel register The operation to be performed is
specified by a binary code known
CPUs make use of _________
as the operation code.
counters, in which all of the flip-
flops of the counter change at the a. True
same time.
b. False
a. synchronous
The address of the next
b. asynchronous instruction to be fetched must be
a real address, not a virtual
c. clocked S-R
address.
d. timed ripple
a. True
The _________ table provides the
b. False
value of the next output when the
inputs and the present output are It has become common practice to
known, which is exactly the use a symbolic representation of
information needed to design the machine instructions.
counter or any sequential circuit.
a. True
a. excitation
b. False
b. Kenough
One of the traditional ways of
c. J-K flip-flop describing processor architecture
is in terms of the number of
d. FPGA
addresses contained in each
instruction.

A _________ is a PLD featuring a a. True

general structure that allows very
b. False
high logic capacity and offers
more narrow logic resources and a Memory references are faster than
higher ration of flip-flops to logic register references.
resources than do CPLDs.
a. True
a. SPLD
b. False
b. FPGA
The instruction set is the
c. PAL programmer's means of
controlling the processor.
d. PLA
a. True
b. False There must be ________
instructions for moving data
Not all machine languages include
between memory and the
numeric data types.
registers.
a. True
a. branch
b. False
b. logic
Most machines provide the basic
c. memory
arithmetic operations of add,
subtract, multiply, and divide. d. I/O
a. True ________ instructions operate on
the bits of a word as bits rather
b. False
than as numbers, providing
A branch can be either forward or capabilities for processing any
backward. other type of data the user may
wish to employ.
a. True
a. Logic
b. False
b. Arithmetic
Procedures do not allow
programming tasks to be c. Memory
subdivided into smaller units.
d. Test
a. True
______ instructions provide
b. False computational capabilities for
processing number data.
The focus of MMX technology is
multimedia programming. a. Boolean
a. True b. Logic
b. False c. Memory
The ________ specifies the d. Arithmetic
operation to be performed.
_______ instructions are needed to
a. source operand reference transfer programs and data into
memory and the results of
b. opcode
computations back out to the
c. next instruction reference user.
d. processor register a. I/O
A(n) _________ expresses b. Transfer
operations in a concise algebraic
c. Control
form using variables.
d. Branch
a. opcode
The x86 data type that is a signed
b. high-level language
binary value contained in a byte,
c. machine language word, or doubleword, using twos
d. register
complement representation is d. push
_________.
Which ARM operation category
a. general includes logical instructions (AND,
OR, XOR), add and subtract
b. ordinal
instructions, and test and
c. integer compare instructions?
d. packed BCD a. data-processing instructions
b. branch instructions
The most fundamental type of c. load and store instructions
machine instruction is the
d. extend instructions
_________ instruction.
a. conversion
In the ARM architecture only
b. data transfer
_________ instructions access
c. arithmetic memory locations.
d. logical a. data processing
The _________ instruction includes b. status register access
an implied address.
c. load and store
a. skip
d. branch
b. rotate
Which data type is defined in
c. stack MMX?
d. push a. packed byte
Which of the following is a true b. packed word
statement?
c. packed doubleword
a. a procedure can be called from
d. all of the above
more than one location
A branch instruction in which the
b. a procedure call can appear in a
branch is always taken is
procedure
_________.
c. each procedure call is matched
a. conditional branch
by a return in the called program
b. unconditional branch
d. all of the above
c. jump
The entire set of parameters,
including return address, which is d. bi-endian
stored for a procedure invocation
The value of the mode field
is referred to as a _________.
determines which addressing
a. branch mode is to be used.
b. stack frame a. True
c. pop b. False
In a system without virtual a. True
memory, the effective address is a
b. False
virtual address or a register.
Typically an instruction set will
a. True
include both preindexing and
b. False postindexing.
The disadvantage of immediate a. True
addressing is that the size of the
b. False
number is restricted to the size of
the address field. The x86 is equipped with a variety
of addressing modes intended to
a. True
allow the efficient execution of
b. False high-level languages.
With direct addressing, the length a. True
of the address field is usually less
b. False
than the word length, thus limiting
the address range. The base with index and
displacement mode sums the
a. True
contents of the base register, the
b. False index register, and a displacement
to form the effective address.
a. True
Register addressing is similar to
direct addressing with the only b. False
difference being that the address
field refers to a register rather
than a main memory address.
a. True For addresses that reference
b. False memory the range of addresses
that can be referenced is not
Register indirect addressing uses related to the number of address
the same number of memory bits.
references as indirect addressing.
a. True
a. True
b. False
b. False
The principal price to pay for
Three of the most common uses variable-length instructions is an
of stack addressing are relative increase in the complexity of the
addressing, base-register processor.
addressing, and indexing.
a. True
a. True
b. False
b. False
One advantage of linking the
The method of calculating the EA addressing mode to the operand
is the same for both base-register rather than the opcode is that any
addressing and indexing.
addressing mode can be used with d. displacement
any opcode.
________ has the advantage of
a. True flexibility, but the disadvantage of
complexity.
b. False
a. Stack addressing
The advantage of __________ is
that no memory reference other b. Displacement addressing
than the instruction fetch is
c. Direct addressing
required to obtain the operand.
d. Register addressing
a. direct addressing
For _________, the address field
b. immediate addressing
references a main memory
c. register addressing address and the referenced
register contains a positive
d. stack addressing
displacement from that address.
The principal advantage
a. indexing
of__addressing is that it is a very
simple form of addressing. b. base-register addressing
a. displacement c. relative addressing
b. register d. all of the above
c. stack Indexing performed after the
indirection is __________.
d. direct
a. relative addressing
______ has the advantage of large
address space, however it has the b. autoindexing
disadvantage of multiple memory
c. postindexing
references.
d. preindexing
a. Indirect addressing
For the _________ mode, the
b. Direct addressing
operand is included in the
c. Immediate addressing instruction.
d. Stack addressing a. immediate
b. base
The advantages of _________ c. register
addressing are that only a small
d. displacement
address field is needed in the
instruction and no time-
consuming memory references
are required.
The only form of addressing for
a. direct
branch instructions is _________
b. indirect addressing.
c. register a. register
b. relative a. True
c. base b. False
d. immediate All instructions in the ARM
architecture are __________ bits
Which of the following interrelated
long and follow a regular format.
factors go into determining the
use of the addressing bits? a. 8
a. number of operands b. 16
b. number of register sets c. 32
c. address range d. 64
d. all of the above __________ is a design principle
employed in designing the PDP-10
_________ is a principle by which
instruction set.
two variables are independent of
each other. a. Orthogonality
a. Opcode b. Completeness
b. Orthogonality c. Direct addressing
c. Completeness d. All of the above
d. Autoindexing The processor needs to store
instructions and data temporarily
The _________ was designed to
while an instruction is being
provide a powerful and flexible
executed.
instruction set within the
constraints of a 16-bit a. True
minicomputer.
b. False
a. PDP-1
The control unit (CU) does the
b. PDP-8 actual computation or processing
of data.
c. PDP-11
a. True
d. PDP-10
b. False
The __________ byte consists of
three fields: the Scale field, the Within the processor there is a set
Index field and the Base field. of registers that function as a
level of memory above main
a. SIB
memory and cache in the
b. VAX hierarchy.
c. PDP-11 a. True
d. ModR/M b. False
The memory transfer rate has not Condition codes facilitate
kept up with increases in multiway branches.
processor speed.
a. True
b. False a. True
The allocation of control b. False
information between registers and
Interrupt processing allows an
memory are not considered to be
application program to be
a key design issue.
suspended in order that a variety
a. True of interrupt conditions can be
serviced and later resumed.
b. False
a. True
b. False
Instruction pipelining is a powerful
technique for enhancing An interrupt is generated from
performance but requires careful software and it is provoked by the
design to achieve optimum results execution of an instruction.
with reasonable complexity.
a. True
a. True
b. False
b. False
While the processor is in user
The cycle time of an instruction mode the program being executed
pipeline is the time needed to is unable to access protected
advance a set of instructions one system resources or to change
stage through the pipeline. mode, other than by causing an
exception to occur.
a. True
a. True
b. False
b. False
A control hazard occurs when two
or more instructions that are The exception modes have full
already in the pipeline need the access to system resources and
same resource. can change modes freely.
a. True a. True
b. False b. False
One of the major problems in __________ are a set of storage
designing an instruction pipeline is locations.
assuring a steady flow of
A. Processors
instructions to the initial stages of
the pipeline. B. PSWs
a. True C. Registers
b. False D. Control units
It is possible to improve pipeline The ___ controls the movement of
performance by automatically data and instructions into and out
rearranging instructions within a of the processor.
program so that branch
A. control unit
instructions occur later than
actually desired. B. ALU
C. shifter C. calculate operands
D. branch D. execute instruction
________ registers may be used _________ is a pipeline hazard.
only to hold data and cannot be
A. Control
employed in the calculation of an
operand address. B. Resource
A. General purpose C. Data
B. Data D. All of the above
C. Address The predict-never-taken approach
is the most popular of all the
D. Condition code
branch prediction methods.
__________ are bits set by the
a. True
processor hardware as the result
of operations. b. False
A. MIPS A ________ hazard occurs when
there is a conflict in the access of
B. Condition codes
an operand location.
C. Stacks
A. resource
D. PSWs
B. data
C. structural
The _________ contains the address
D. control
of an instruction to be fetched.
A _________ is a small, very-high-
A. instruction register
speed memory maintained by the
B. memory address register instruction fetch stage of the
pipeline and containing the n most
C. memory buffer register
recently fetched instructions in
D. program counter sequence.
The _________ contains a word of A. loop buffer
data to be written to memory or
B. delayed branch
the word most recently read.
C. multiple stream
A. MAR
D. branch prediction
B. PC
The _________ is a small cache
C. MBR
memory associated with the
D. IR instruction fetch stage of the
pipeline.
The ________ determines the
opcode and the operand A. dynamic branch
specifiers.
B. loop table
A. decode instruction
C. branch history table
B. fetch operands
D. flag essentially sequential nature of a
machine-instruction program.
The _________ stage includes ALU
operations, cache access, and a. True
register update.
b. False
A. decode
The major cost in the life cycle of
B. execute a system is hardware.
C. fetch a. True
D. write back b. False
________ is used for debugging. It is common for programs, both
system and application, to
A. Direction flag
continue to exhibit new bugs after
B. Alignment check years of operation.
C. Trap flag a. True
D. Identification flag b. False
The ARM architecture supports Procedure calls and returns are
_______ execution modes. not important aspects of HLL
programs.
A. 2
a. True
B. 8
b. False
C. 11
The register file is on the same
D. 7
chip as the ALU and control unit.
a. True
b. False
The register file employs much
The OS usually runs in ________. shorter addresses than addresses
for cache and memory.
A. supervisor mode
a. True
B. abort mode
b. False
C. undefined mode
To handle any possible pattern of
D. fast interrupt mode calls and returns the number of
Microprogramming eases the task register windows would have to be
of designing and implementing unbounded.
the control unit and provides a. True
support for the family concept.
b. False
a. True
Cache memory is a much faster
b. False memory than the register file.
Pipelining is a means of a. True
introducing parallelism into the
b. False d. Operands used
The cache is capable of handling The Patterson study examined the
global as well as local variables. dynamic behavior of _________
programs, independent of the
a. True
underlying architecture.
b. False
a. HLL
When using graph coloring, nodes
b. RISC
that share the same color cannot
be assigned to the same register. c. CISC
a. True d. all of the above
b. False _________ is the fastest available
storage device.
With simple, one cycle
instructions, there is little or no a. Main memory
need for microcode.
b. Cache
a. True
c. Register storage
b. False
d. HLL
Almost all RISC instructions use
The first commercial RISC product
simple register addressing.
was _________.
a. True
a. SPARC
b. False
b. CISC
RISC processors are more
c. VAX
responsive to interrupts because
interrupts are checked between d. the Pyramid
rather elementary operations.
_________ instructions are used to
a. True position quantities in registers
temporarily for computational
b. False
operations.
Unrolling can improve
a. Load-and-store
performance by increasing
instruction parallelism by b. Window
improving pipeline performance.
c. Complex
a. True
d. Branch
b. False

_________ determines the control

and pipeline organization.
a. Calculation
b. Execution sequencing Which stage is required for load
and store operations?
c. Operations performed
a. I
b. E All MIPS R series processor
instructions are encoded in a
c. D
single ________ word format.
d. all of the above
a. 4-bit
A ________ instruction can be used
b. 8-bit
to account for data and branch
delays. c. 16-bit
a. SUB d. 32-bit
b. NOOP A _________ architecture is one
that makes use of more, and more
c. JUMP
fine-grained pipeline stages.
d. all of the above
a. parallel
delay slot
b. superpipelined
The instruction location
c. superscalar
immediately following the delayed
branch is referred to as the d. hybrid
________.
The R4000 can have as many as
a. delay load _______ instructions in the pipeline
at the same time.
b. delay file
a. 8
c. delay slot
b. 10
d. delay register
c. 5
A tactic similar to the delayed
branch is the _________, which can d. 3
be used on LOAD instructions.
a. delayed load
b. delayed program
c. delayed slot
d. delayed register
The MIPS R4000 uses ________ bits
for all internal and external data
paths and for addresses, registers,
and the ALU.
a. 16
b. 32
c. 64
d. 128
refers to an architecture defined
by _____.
a. Microsoft
b. Apple
c. Sun Microsystems
d. IBM
The R4000 pipeline stage where
the instruction result is written
back to the register file is the
__________ stage.
a. write back
b. tag check
c. data cache
d. instruction execute