Ministry of Higher Education and

Scientific Research - Iraq

University of Baghdad
College of Engineering
Department of Computer Engineering

MODULE DESCRIPTOR FORM

‫نموذج وصف المادة الدراسية‬
Module Information
‫معلومات المادة الدراسية‬
Module Title BOOLEAN ALGEBRA Module Delivery

Module Type SUPORT

Module Code COE105
Class Lecture + Lab
ECTS Credits 5
SWL (hr/sem) 125
Module Level 1 Semester of Delivery 1
Administering
Computer Engineering College Engineering
Department
[email protected]
Module Leader Zainab Hassan Fakhri e-mail

Module Leader’s
Module Leader’s Acad. Title
Qualification
[email protected]
Module Tutor Zainab Hassan Fakhri e-mail

Peer Reviewer Name e-mail

Review Committee Approval Version Number

Relation With Other Modules

‫العالقة مع المواد الدراسية األخرى‬
Prerequisite module Semester

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Co-requisites module Semester
Module Aims, Learning Outcomes and Indicative Contents
‫أهداف المادة الدراسية ونتائج التعلم والمحتويات اإلرشادية‬
● Understanding of Boolean variables, operators (AND, OR, NOT), and their
properties.
● Learn how to express and simplify Boolean functions.
● Apply laws and theorems (e.g., De Morgan’s Theorems) to simplify Boolean
Module Aims expressions.
‫أهداف المادة الدراسية‬ ● Use Karnaugh maps for simplifying Boolean expressions and designing
combinational logic circuits.
● Design and analyze combinational logic circuits based on Boolean expressions.
● Use Boolean algebra and Karnaugh maps to minimize the number of gates
and inputs required for a given logic function.

● Clearly define and explain Boolean variables, operators, and fundamental

concepts of Boolean algebra.
● Demonstrate knowledge of key Boolean laws and theorems, such as De
Morgan’s Theorems.
● Apply Boolean algebra techniques to simplify complex Boolean expressions
and functions.
Module Learning ● Utilize Karnaugh maps to visually simplify Boolean expressions and to design
Outcomes efficient combinational logic circuits.
● Design and implement digital circuits using basic logic gates (AND, OR, NOT,
‫مخرجات التعلم للمادة الدراسية‬ NAND, NOR, XOR, XNOR) based on Boolean expressions.
● Analyze and design combinational logic circuits to perform specified tasks or
functions.
● Apply Boolean algebra techniques and Karnaugh maps to minimize the
number of logic gates and inputs in digital circuit designs.
● Develop optimized circuit designs that improve performance and reduce cost.

Indicative Contents
‫المحتويات اإلرشادية‬

Learning and Teaching Strategies

‫استراتيجيات التعلم والتعليم‬
- Lectures.
Strategies
- Homework and Assignments.

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 - Tests and Exams.
- In-class questions and Discussions.
- Extracurricular Activities.
- Individual / Group Projects
- In- and Out-Class conversations.

Student Workload (SWL)

‫الحمل الدراسي للطالب‬
Structured SWL (h/sem) Structured SWL (h/w)
79 5
‫الحمل الدراسي المنتظم للطالب خالل الفصل‬ ‫الحمل الدراسي المنتظم للطالب أسبوعيا‬
Unstructured SWL (h/sem) Unstructured SWL (h/w)
46 3
‫الحمل الدراسي غير المنتظم للطالب خالل الفصل‬ ‫الحمل الدراسي غير المنتظم للطالب أسبوعيا‬
Total SWL (h/sem)
125
‫الحمل الدراسي الكلي للطالب خالل الفصل‬

Module Evaluation
‫تقييم المادة الدراسية‬
Time/ Relevant Learning
Weight (Marks) Week Due
As
Number Outcome
Quizzes 12% (12)
Attendance and
Formative 8% (8)
Participation
assessment
Home works 5% (5)
Lab. 15% (15)
Summative Mid Exam 1 10% (10)
assessment Final Exam 3 hrs. 50% (50)
Total assessment 100% (100 Marks)

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 Delivery Plan (Weekly Syllabus)
‫المنهاج االسبوعي النظري‬
Week Material Covered
Week 1
Number system
Week 2
Arithmetic Operations
Week 3
Digital Codes, Code Conversion
Week 4
Logic Gates
Week 5
Boolean algebra
Week 6
The Karnaugh Map
Week 7
Implementation of Logic Circuit
Week 8
Midterm Exam
Week 9
Basic Adders
Week 10
Arithmetic circuits
Week 11
Comparators
Week 12, 13
Decoders and encoders, case studies: Seven Segment decoder
Week 14, 15
Multiplexers and De-multiplexers

Delivery Plan (Weekly Lab. Syllabus)

‫المنهاج االسبوعي للمختبر‬
Week Material Covered
Week 1 Verification of Logic Gates.
Week 2 Implementation of Universal Gates (NAND & NOR).
Week 3 Design of Half Adder.
Week 4 Design of Full Adder.
Week 5 Design of Half Subtractor.
Week 6, 7 Design of Full Subtractor.
Week 8, 9 Design and Implementation of Multiplexer (MUX).
Week 10, 11 Design and Implementation of Demultiplexer (DEMUX).
Week 12, 13 XOR Gate as a Parity Checker.
Week 14, 15 Design of 4-bit Binary Adder.

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 Learning and Teaching Resources
‫مصادر التعلم والتدريس‬
Available in the
Text
Library?
Required Texts
Recommended
Texts

Websites

APPENDIX:

GRADING SCHEME
‫مخطط الدرجات‬
Group Grade ‫التقدير‬ Marks (%) Definition
A – Excellent ‫امتياز‬ 90 - 100 Outstanding Performance
B - Very Good ‫جيد جدا‬ 80 - 89 Above average with some errors
Success Group
(50 - 100)
C – Good ‫جيد‬ 70 - 79 Sound work with notable errors
D – Satisfactory ‫متوسط‬ 60 - 69 Fair but with major shortcomings
E – Sufficient ‫مقبول‬ 50 - 59 Work meets minimum criteria
Fail Group FX – Fail ‫مقبول بقرار‬ (45-49) More work is required but credit awarded
(0 – 49) F – Fail ‫راسب‬ (0-44) Considerable amount of work required

Note:
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NB Decimal places above or below 0.5 will be rounded to the higher or lower full mark (for example a mark of 54.5
will be rounded to 55, whereas a mark of 54.4 will be rounded to 54. The University has a policy NOT to condone
"near-pass fails" so the only adjustment to marks awarded by the original marker(s) will be the automatic rounding
outlined above.

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