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DHD Lab

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Viswatej Abbireddy
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10 views

DHD Lab

Uploaded by

Viswatej Abbireddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Visvesvaraya National Institute

of Technology (VNIT), Nagpur

DIGITAL HARDWARE DESIGN


(ECP 313)
Project Report

Submitted by :
Jayram.A (BT21ECE052)
Thahesh.P(BT21ECE018)
Vinit.R( BT21ECE009)
Viswatej.A (BT21ECE017)
Semester 6

Submitted to :
Anamika singh
(Course Instructor)
Department of Electronics and Communication Engineering,
VNIT Nagpur
1.0

Digital Timer
Aim: To Design a Digital Timer which has the following functionalities
1. Up timer
2. Down timer
3. Alarm
4. Reset

Components and Software used:


• Quartus
• FPGA Board

Code: :

1
2 module seg7(
3 input [3:0] data in,
4 output reg [7:0] display out
5 );
6

7 always @(*) begin


8 case (data in)
9 4'd0:
10 display out = 8'b11000000; //a,b,c,d,e,f,g,dot (zero)
11 4'd1:
12 display out = 8'b11001111; //one
13 4'd2:
14 display out = 8'b10100100; //two
15 4'd3:
16 display out = 8'b10000110; //three
17 4'd4:
18 display out = 8'b10001011; //four
19 4'd5:
20 display out = 8'b10010010; //five
21 4'd6:
22 display out = 8'b10010000; //six
23 4'd7:
24 display out = 8'b11000111; //seven
25 4'd8:
26 display out = 8'b10000000; //eight
27 4'd9:
28 display out = 8'b10000010; //nine
1.0

29 default:
30 display out = 8'b11000000; //default case
31 endcase
32 end
33
34 endmodule
35
36 module digital clock(
37 input clk 50mhz, // 50 MHz system clock input
38 input reset,
39 input up, // up input
40 input stop,
41 output [31:0] display out, // 7−segment display output
42 output reg alarm led // Alarm LED output
43 );
44
45 reg clk 1hz; // 1 Hz clock signal
46 reg [27:0] counter;
47 reg [5:0] seconds;
48 reg [5:0] minutes;
49 reg [5:0] timer mode; // 0 = Up timer, 1 = Down timer
50
51 // Set the alarm time (1:00)
52 parameter ALARM MINUTE = 6'd0;
53 parameter ALARM SECOND = 6'd05;
54

55 always @(posedge clk 50mhz or posedge reset) begin


56 if (reset) begin
57 counter ≤ 28'd0;
58 clk 1hz ≤ 1'b0;
59 end
60 else begin
61 if (counter == 28'd30000000) begin
62 counter ≤ 28'd0;
63 clk 1hz ≤ ¬clk 1hz;
64 end
65 else begin
66 counter ≤ counter + 28'd1;
67 end
68 end
69 end
70
71 always @(posedge clk 1hz or posedge reset) begin
72 if (reset) begin
73 seconds ≤ 6'd0;
74 minutes ≤ 6'd0;
75 timer mode ≤ 6'd0;
76 end
77 else begin
1.0

78 if (timer mode == 6'd0) begin // Up timer


79 if (seconds == 6'd59) begin
80 seconds ≤ 6'd0;
81 if (minutes == 6'd59)
82 minutes ≤ 6'd0;
83 else
84 minutes ≤ minutes + 6'd1;
85 end
86 else
87 seconds ≤ seconds + 6'd1;
88 end
89 else if (timer mode == 6'd1)
90 begin // Down timer
91 if (seconds == 6'd0) begin
92 seconds ≤ 6'd59;
93 if (minutes == 6'd0)
94 minutes ≤ 6'd59;
95 else
96 minutes ≤ minutes − 6'd1;
97 end
98 else
99 seconds ≤ seconds − 6'd1;
100 end
101 //else begin−−> need to implement for stopwatch
102
103 if (up == 1'b1) begin
104 timer mode ≤ 6'd0; // Up timer mode
105 end
106 else if (up == 1'b0) begin
107 timer mode ≤ 6'd1; // Down timer mode
108 end
109 else if (stop == 1'b1) begin
110 timer mode ≤ 6'd2;//stop timer mode
111 end
112 end
113 end
114
115

116 // Check if the current time matches the alarm time


117 always @* begin
118 if (minutes == ALARM MINUTE && seconds == ALARM SECOND)
119 alarm led = 1'b1; // Activate LED when alarm time is reached
120 else
121 alarm led = 1'b0;
122 end
123
124 wire [3:0] seconds ones, seconds tens, minutes ones, minutes tens;
125
126 assign seconds ones = seconds % 6'd10;
1.0

127 assign seconds tens = seconds / 6'd10;


128 assign minutes ones = minutes % 6'd10;
129 assign minutes tens = minutes / 6'd10;
130
131 // Instantiate the 7−segment display module
132 seg7 seconds ones seg7 (
133 .data in(seconds ones),
134 .display out(display out[30:24])
135 );
136
137 seg7 seconds tens seg7 (
138 .data in(seconds tens),
139 .display out(display out[22:16])
140 );
141
142 seg7 minutes ones seg7 (
143 .data in(minutes ones),
144 .display out(display out[14:8])
145 );
146

147 seg7 minutes tens seg7 (


148 .data in(minutes tens),
149 .display out(display out[6:0])
150 );
151
152 endmodule

RTL Viewer: :
1.0

Flow Chart: :

Conclusion : Therefore Digital Timer has been designed on the FPGA board
through the Quartus software.

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