Computer Organisation & Architecture

How to Use Self-Learning Material?

The pedagogy used to design this course is to enable the student to assimilate the concepts
with ease. The course is divided into modules. Each module is categorically divided into units or
chapters. Each unit has the following elements:

Table of Contents: Each unit has a well-defined table of contents. For example: “1.1.1.
(a)” should be read as “Module 1. Unit 1. Topic 1. (Sub-topic a)” and 1.2.3. (iii) should
be read as “Module 1. Unit 2. Topic 3. (Sub-topic iii).

Aim: It refers to the overall goal that can be achieved by going through the unit.

Instructional Objectives: These are behavioural objectives that describe intended

learning and define what the unit intends to deliver.

Learning Outcomes: These are demonstrations of the learner’s skills and experience
sequences in learning, and refer to what you will be able to accomplish after going
through the unit.

Self-Assessment Questions: These include a set of multiple-choice questions to be

answered at the end of each topic.

Did You Know?: You will learn some interesting facts about a topic that will help you
improve your knowledge. A unit can also contain Quiz, Case Study, Critical Learning
Exercises, etc., as metacognitive scaffold for learning.

Summary: This includes brief statements or restatements of the main points of unit and
summing up of the knowledge chunks in the unit.

Activity: It actively involves you through various assignments related to direct application
of the knowledge gained from the unit. Activities can be both online and offline.

Bibliography: This is a list of books and articles written by a particular author on a

particular subject referring to the unit’s content.

e-References: This is a list of online resources, including academic e-Books and journal
articles that provide reliable and accurate information on any topic.

Video Links: It has links to online videos that help you understand concepts from a
variety of online resources.

Computer Organisation & Architecture

 LEADERSHIP KLEF

President Vice Chancellor

Er. Koneru Satyanarayana Dr. G. Pardha Saradhi Varma

Pro-Vice Chancellor Incharge Registrar

Dr. N. Venkatram Dr. K. Subbarao

Computer Organisation & Architecture

 CREDITS

Author
Dr. Fazal Noorbasha

Director CDOE
C. Shanath Kumar

Instructional Designer
Nabina Das

Content Editor
Kalyani Kunchala

Project Manager
K. D. N. Lakshmi

Graphic Designer
K. Dinesh

Computer Organisation & Architecture

 First Edition, 2023.

KL Deemed to be University-CDOE has full copyright over this educational material. No

part of this document may be produced, stored in a retrieval system, or transmitted, in any
form or by any means.

Computer Organisation & Architecture

 Author Profile

Dr. Fazal Noorbasha

Dr. Fazal Noorbasha holds multiple degrees, including B.Sc. in Electronics, M.Sc. in Electronics,
B.Tech. in ECE, and M.Tech. in AI (Artificial Intelligence). He obtained his Ph.D. in VLSI under the
esteemed guidance of Dr. Ashish Verma, Director In-charge at the Institute of Engineering and
Technology and Dr. Harishingh Gour, Central University, Sagar, M.P., India.

With extensive experience in guiding students, Dr. Fazal has supervised 30 B.Tech. (ECE)
and 35 M.Tech. (VLSI) projects. He has successfully mentored three Ph.D. scholars who have
completed their research work, and currently supervises three scholars who are pursuing their
Ph.D. under his guidance.

Dr. Fazal has an impressive publication record, with 57 papers indexed in Scopus/SCI/WoS, as
well as 30 journal and conference publications listed in UGC CARE. He has also undertaken
funded projects sponsored by DST and NGOs.In 2011,

Dr. Fazal joined K L University as an Assistant Professor in the Department of ECE. He initiated
the VLSI Research Group at the university, where he serves as the Research group head. Over
the years, he has organised numerous workshops, FDPs, and conferences as a convener and
co-convener. Presently, Dr. Fazal holds the position of Associate Professor in the Department of
ECE and serves as the Associate Dean (Academics) at K L University.

His research interests span across various domains, including Digital Systems, Cryptography,
VLSI, AI and IoT.

Computer Organisation & Architecture

Computer Organisation & Architecture

Course Description

The Computer Organisation and Architecture (COA) is one of the most important and comprehensive
subjects that includes many foundational concepts and knowledge used in the design of a computer
system. The system architecture defines various functional units of the computer system and how
these units are interconnected. It defines the system performance specifications and what system
should achieve in terms of performance.

In simple words, the computer architecture is all about computer system design details expressed in
terms of functional units and interconnection between these units. The computer architecture helps
us define the functional capabilities and the requirements for the computer system. The system
architecture is a high-level design specification that does not specify any specific details of the
hardware components. The computer architecture gives an abstracted view of the structure of various
functional units and its behaviour.

In Computer Organisation and Architecture (COA), the computer system can be classified into number
of functional units. This classification is based on the specific function performed in the computer
system.

Digital electronics, digital circuits, and digital technology are electronics that are operated on digital
signals. Digital techniques are much easier for getting the electronic device. These devices are used
to switch into one of the known states apart from reproducing a continuous range of values. Digital
circuits are made from an enormous collection of logic gates and a simple electronic representation
of the Boolean logic function. Modern digital computers are built from digital logic circuits whose basic
building blocks are logic gates, each of which is designed to implement a specific logical function.
Information is held in data “words”, representing data or instructions, made up from strings of individual
“bits” with binary values of 1 or 0. These values are analogous to Boolean logic propositions and
the statements or conclusions derived from them which were defined as “true” or “false”. Boolean
algebra is the tool used to design combinations of gates to implement more complex functions such
as mathematical operations, control functions and data storage.

Boolean functions are the building blocks of symmetric cryptographic systems. Symmetrical
cryptographic algorithms are fundamental tools in the design of all types of digital security systems
(i.e., communications, financial and e-commerce). Cryptographic Boolean Functions and Applications
is a concise reference that shows how Boolean functions are used in cryptography. Boolean functions
are among the fundamental objects of discrete mathematics, especially in those of its subdisciplines
which fall under mathematical logic and mathematical cybernetics.

With such wide applications, the presence of the digital electronics is felt in all the arenas of life and
carried further with new inventions. This course is designed for the aspirants who wish to know the
core concepts of Computer Organisation and Architecture using digital electronics concepts. It covers
the basic and academic concepts that include various computer blocks, number system, conversion
types, Logic Gates, SOP and POS Boolean equations and optimisation methods using Boolean laws
and K-MAPs, combinational logic circuits and sequential logic circuits design and many more.

This course is divided into four modules.

Computer Organisation & Architecture

1
MODULE 1
BASICS OF COMPUTERS AND NUMBER SYSTEM
Central Processing Unit - Block Diagram Of CPU - Input Unit , Output Unit , Arithmetic And Logic
Unit , Control Unit , Memory - Classification Of Memory – ROM And RAM , Types Of RAM SRAM
AND DRAM ROM:PROM, EPROM, EEPROM, Number System-Definition of Number System and
Types of Number System, Decimal Number System , Binary Number System ,Octal Number System
,Hexadecimal Number System , Conversion of Number System - Decimal into Binary , Binary into
Decimal , Decimal into Octal , Binary into Octal , Decimal into Hexadecimal, Binary into Hexadecimal.

MODULE 2
BOOLEAN ALGEBRA AND LOGIC GATES
Boolean Algebra - Boolean Algebra, Application of Boolean Algebra, Boolean Functions, Rules
of Boolean Algebra, Properties of Boolean Algebra and , Operations of Boolean Algebra- Boolean
Addition, Boolean Subtraction. Logic Gates, Truth Table and Logic Design – AND Gate, NAND Gate,
OR Gate, NOR Gate, EX-OR Gate, EX-NOR Gates.

MODULE 3
KARNAUGH MAP (K-MAP) AND SIMPLIFICATION OF BOOLEAN FUNCTIONS
Karnaugh Map-K-Map, Conversion Steps for Solving K-Map, steps used to solve the expressions,
Method of K-Map- 2 Variable KMaps, 3 Variable K Maps, 4 Variable K Maps, 5 Variable K Maps.
Minimization Techniques- Minterms and Maxterms, Sum of Product (SOP), Product of Sum (POS) and
Conversion of SOP to POS and Conversion of POS to SOP.

MODULE 4
COMBINATIONAL CIRCUITS & SEQUENTIAL CIRCUITS
Combinational Circuits-Half Adder, Full Adder, Half Subtractor, Full Subtractor, Multiplexer and
Demultiplexer. Conversion
Sequential Circuits– Flip Flops, Types of Flip Flop– SR Flip Flop, JK Flip Flop, D flip flop, T Flip flop,
Master - Slave JK Flip Flop, Conversion.

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2
Table of Contents

MODULE 1
BASICS OF COMPUTERS AND NUMBER SYSTEM

Unit 1.1 Basics of Computers

Unit 1.2 Memory
Unit 1.3 Number System

MODULE 2
BOOLEAN ALGEBRA AND LOGIC GATES

Unit 2.1 Boolean Algebra

Unit 2.2 Operations of Boolean Algebra
Unit 2.3 Logic Gates, Truth Table and Logic Design

MODULE 3
KARNAUGH MAP (K-MAP) AND SIMPLIFICATION OF BOOLEAN FUNCTIONS

Unit 3.1 Karnaugh(K-Map)

Unit 3.2 Minimisation Techniques

MODULE 4
COMBINATIONAL CIRCUITS & SEQUENTIAL CIRCUITS

Unit 4.1 Combinational Circuits - Adders

Unit 4.2 Combinational Circuits - Subtractors
Unit 4.3 Combinational Circuits – Multiplexers and De-multiplexers
Unit 4.4 Sequential Circuits
Unit 4.5 Conversion of Flip-Flops

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3
 Computer Organisation and Architecture

Module - 1

Basics of Computers
and Number System

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4
Module Description

Now a days, computers have become an essential element in all aspects of life. Their importance lies
in all areas of the global needs that demand knowledge of computers as the basic need in making
an individual more updated to the global events. Therefore, knowledge of the basics of computers is
imperative for swift and expeditious work in all organisations.
Be it the latest developments, like Artificial Intelligence, Internet of Things, and Cloud Computing, etc.,
all the developments are the furtherance of the basic knowledge of the computers, and we cannot
deny the fact that the future runs on the miracles of the new innovations brought by the computers
and the future generations work environment is almost revolved around the computers and their
inventions. So, it is important for all of us to focus on the foundational knowledge of the computers and
their applications in different genres.
Globalisation has increased the scope of connectivity among all the nations with large amount of
data storing and sharing. With such enormous amounts of data connectivity, Big Data analytics
acquires importance on the parameters of memory allocation and division. The basic understanding
of the memory and the types acts as a basis to improvise the data processing and the storage of the
instructions from all the ends.
However, the functioning of the computer requires the knowledge of the number system for the efficient
flow of data. The encryption and decryption of data is important in the cyber arena which works on the
principle of number system to avoid any kind of data breach. Therefore, the basic understanding of the
number system gives ample scope to excel in data protection.
The basic knowledge of the computer includes the understanding of the components of the computer
input unit, CPU (Central Processing Unit), output unit, Memory, and Number System. Hence, this
module attempts to provide the basic knowledge on the above-mentioned topics.

Unit 1.1 Basics of Computers

Unit 1.2 Memory
Unit 1.3 Number System

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5
 Computer Organisation and Architecture

Module - 1
Unit - 1

Basics of Computers

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6
Table of Contents
Unit 1.1 Basics of Computers

Aim --------------------------------------------------------------------------------------------------------- 08
Instructional Objectives ------------------------------------------------------------------------------- 08
Learning Outcomes ------------------------------------------------------------------------------------ 08
1.1.1 Central Processing Unit (CPU) -------------------------------------------------------------- 10
Self-Assessment Questions ------------------------------------------------------------------ 11
1.1.2 Control Unit --------------------------------------------------------------------------------------- 12
Self-Assessment Questions ------------------------------------------------------------------ 13
1.1.3Arithmetic Logic Unit ---------------------------------------------------------------------------- 14
Self-Assessment Questions ------------------------------------------------------------------ 15
1.1.4 Input Unit ------------------------------------------------------------------------------------------ 16
Self-Assessment Questions ------------------------------------------------------------------ 17
1.1.5 Output Unit ---------------------------------------------------------------------------------------- 18
Self-Assessment Questions ------------------------------------------------------------------ 19
1.1.6Memory or Storage Unit ------------------------------------------------------------------------ 20
Self-Assessment Questions ------------------------------------------------------------------ 21
Summary -------------------------------------------------------------------------------------------------   22
Terminal Questions ----------------------------------------------------------------------------------- 22
Answer Keys -------------------------------------------------------------------------------------------- 23
Activity ---------------------------------------------------------------------------------------------------- 23
Glossary ------------------------------------------------------------------------------------------------ 24
Bibliography -------------------------------------------------------------------------------------------- 24
e-References ------------------------------------------------------------------------------------------ 24
Video links ---------------------------------------------------------------------------------------------- 25
Image credits ------------------------------------------------------------------------------------------ 25
Keywords ------------------------------------------------------------------------------------------------ 25

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7
 Aim
To introduce fundamental concepts, such as the architecture and functional components of
digital computers.

Instructional Objectives
This unit intends to:

● Explain the basics of computer organisation and architecture

● Describe the Central Processing Unit (CPU) structure
● Classify the distinct types of CPU modules.
● Describe the input, output, control, ALU and memory unit

Learning Outcomes
Upon completion of this unit, you will be able to:

● Summarise the basics of computer system and organisation

● Identify the different units of computer system architecture
● Illustrate the working of CPU and its modules

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8
Introduction to Computer Architecture
A computer is an electronic machine that performs arithmetic and logical functions in a sequential
and automatic manner, based on user input and producing desired output. It consists of two main
components: hardware and software. Hardware refers to the physical components of the computer,
such as the monitor, keyboard, and mouse. Software, on the other hand, is a collection of programs
that utilise the hardware to perform various tasks, such as the Windows operating system, Linux, MS
Office, etc.
Computer Architecture - Computer Architecture refers to the structure and organisation of a
computer system, including its hardware components and the way they interact. It encompasses the
design principles and techniques used to create efficient and reliable computer systems. By studying
Computer Architecture, students gain insight into how computers are built, how data is processed,
and how instructions are executed, providing a foundation for understanding advanced computing
concepts.
Computer Organisation - Computer organisation involves the working of hardware components and
how they are integrated into a computer system. It deals with the internal view of the computer and the
roles played by internal components during program execution. In other words, computer organisation
is responsible for connecting various computer components, such as the processor, memory, and
peripherals, and the tasks they perform during program execution.
To gain a comprehensive understanding of the inner workings of a computer, it is important to
acknowledge that it comprises multiple interconnected components or units. This diagram illustrates
the connectivity of these components, collectively known as the Von Neumann architecture, which
forms the foundation of a computer system.

Central Processing Unit

Control Unit
Input Arithmetic/Logic Unit Output
Device Device

Memory Unit

Fig. 1: Von Neumann Architecture of a Computer

Now, let’s delve into a detailed exploration of these functional components that comprise a computer
system.
The Von Neumann computer architecture, proposed by John von Neumann in the 1940s, is the foundation
for modern computer design. It features a sequential execution model with four key components: a
central processing unit (CPU), a memory unit, an input/output (I/O) system, and a control unit. The
CPU fetches and executes instructions stored in memory, while the control unit coordinates the flow
of data and instructions. This architecture enables the storage and manipulation of both program
instructions and data in a unified memory space, revolutionising the field of computing.
Computer Organisation & Architecture
9
1.1.1 Central Processing Unit (CPU)
A Central Processing Unit is also called a processor, central processor, or microprocessor. It carries
out all the essential functions of a computer. It receives instructions from both the hardware and active
software and produces output accordingly. It stores all important programs like operating systems and
application software. CPU also helps Input and output devices to communicate with each other. Owing
to these features of CPU, it is often referred to as the brain of the computer.
The CPU is physically installed or inserted into a CPU socket on the motherboard. To ensure optimal
performance, it is equipped with a heat sink that absorbs and dissipates heat, keeping the CPU cool.
The Central Processing Unit (CPU) encompasses the following features:

● The CPU is considered the “brain” of the computer.

● The CPU performs all types of data processing operations.
● It stores data, intermediate results, and program instructions.
● The CPU controls the operation of all computer components.

The CPU itself consists of the following components:

● Control Unit: The control unit is responsible for fetching and decoding instructions, as well as
coordinating the activities of other CPU components.
● Arithmetic Logic Unit (ALU): The ALU performs arithmetic and logical operations, including
addition, subtraction, comparison, and Boolean operations.
● Memory or Storage Unit: The memory unit stores data, intermediate results, and program
instructions.

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Self-Assessment Questions

1) CPU stands for:

A) Control Processing Unit

B) Central Programming Unit
C) Central Processing Unit
D) Control Programming Unit

2) ______ is the brain of the computer.

A) CPU
B) Monitor
C) Mouse
D) Printer

3) CPU helps input and output devices to communicate with each other.

(True/False)

4) Causing the CPU to step through a series of micro-operations is called ______.

A) Execution
B) Runtime
C) Pipelining
D) Sequencing

5) Inside the CPU cabinet, the SATA and PATA cables are connected from motherboard to
______.

A) Hard disk
B) Floppy disk
C) ROM
D) RAM

6) Which of the following are correct features of CPU:

A) CPU is considered as the brain of the computer

B) CPU performs all types of data processing operations
C) It stores data, intermediate results, and instructions
D) All the above
Computer Organisation & Architecture
11
1.1.2 Control unit

The control unit is a crucial circuitry component within the computer system. It utilises electrical signals
to instruct the computer system in executing previously stored instructions. Its main responsibility is
to maintain and regulate the flow of information across the processor. Although the control unit does
not participate in processing and storing data, it plays a vital role in controlling and coordinating the
functioning of all computer parts.

During program execution, the control unit fetches one instruction at a time from the main memory,
decodes it, and then proceeds to execute it. If the instruction involves arithmetic or logical operations,
such as AND, OR, or Ex-OR, the control unit relies on the Arithmetic Logic Unit (ALU) to perform these
operations. After executing the current instruction, the CPU fetches the next instruction for further
execution. This process continues until the program is completed, and the result is output using an
output device. In many computer systems, the control unit and ALU are integrated into a single block
known as the Central Processing Unit (CPU).
The control unit carries out the following functions:

● It controls the transfer of data and instructions among the various units of the computer.
● It manages and coordinates all the units within the computer.
● It obtains instructions from the memory, interprets them, and directs the operation of the
computer accordingly.
● It facilitates communication with input/output devices to transfer data or store results.
● However, it does not process or store data itself.

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12
Self-Assessment Questions

7) ______ looks after and controls the working of the components and the computer system.

A) Control Unit
B) Monitor
C) RAM
D) All the above

8) Which one of the following helps the computer system in the process of carrying out the
stored program instructions:

A) ALU
B) Control Unit
C) Both
D) None

9) Control Unit interacts with both the main memory and ALU.

(True/False)

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1.1.3 Arithmetic Logic Unit
The Arithmetic Logic Unit (ALU) is a critical component responsible for performing arithmetic and
logical functions. Its arithmetic operations encompass addition, subtraction, multiplication, division,
and comparisons. Logical functions involve data selection, comparison, and merging. A CPU may
contain multiple ALUs to enhance computational capabilities. Additionally, ALUs can be utilised for
maintaining timers that aid in running the computer efficiently.
The ALU consists of two subsections:

● Arithmetic Section: This section handles arithmetic operations such as addition, subtraction,
multiplication, and division. Although multiplication and division can be performed, they are
considered more resource-intensive operations. Multiplication can be achieved through
repetitive additions, while subtraction can be accomplished through repeated subtractions.
● Logic Section: This section focuses on logical operations, including AND, OR, NOT, XOR,
NOR, NAND, and other similar operations.

By categorising ALU operations, we can distinguish them as follows:

● Logical Operations: These involve logical operations such as AND, OR, NOT, XOR, NOR,
NAND, and others.
● Bit-Shifting Operations: This refers to shifting the positions of bits by a specific number of
places either to the right or left, resembling multiplication or division operations.
● Arithmetic Operations: These encompass bit-level addition and subtraction, with multiplication
and division being less frequently used due to their increased complexity. Multiplication can
be achieved through repeated additions, and subtraction can be performed through repeated
subtractions.

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Self-Assessment Questions

10) ALU unit consists of ______ subsections namely.

A) 2
B) 3
C) 4
D) 5

11) Which section is to perform logic operations such as comparing, selecting, matching, and
merging of data?

A) Arithmetic Section
B) Logic Section
C) Both A and B
D) None of the above

12) The ‘heart’ of the processor which performs many different operations:

A) Arithmetic and Logic Unit

B) Motherboard
C) Control Unit
D) Memory

13) ALU is the place where the actual executions of instructions take place during the pro-
cessing operation.

(True/False)

14) The ALU gives the output of the operations, and the output is stored in the _______.

A) Memory Devices
B) Registers
C) Flags
D) Output Unit

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1.1.4 Input Unit
The input unit is responsible for the process of entering raw data, instructions, and information into the
computer system. This input is facilitated through various input devices. These devices enable users
to send data, information, or control signals to the computer. Once received, the Central Processing
Unit (CPU) processes the input to generate the desired output.

There are several popular input devices commonly used:

1. Keyboard
2. Mouse
3. Scanner
4. Joystick
5. Light Pen
6. Digitiser
7. Microphone
8. Magnetic Ink Character Recognition (MICR)
9. Optical Character Reader (OCR)
10. Digital Camera
11. Paddle
12. Steering Wheel
13. Gesture recognition devices
14. Light Gun
15. Touch Pad
16. Remote
17. Touch screen
18. Virtual Reality (VR)
19. Webcam
20. Biometric devices
These input devices serve different purposes and cater to various user needs, ensuring a diverse
range of input options for interacting with the computer system.

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Self-Assessment Questions

15) Which one of the following is an input device:

A) Remote
B) Microphone
C) Paddle
D) All the above

16) In computing, which one of the following is used to provide data and control signals to an
information processing system.

A) Control unit
B) Input unit
C) Output unit
D) None

17) The input device Keyboard has ________ keys on the topmost row.

A) Numeric keys
B) Function Keys
C) Control Keys
D) Special Keys

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1.1.5 Output Unit
The output unit refers to the process of presenting processed data through output devices, such as
monitors, printers, and speakers. These devices display or produce the results of the data processing
performed by the computer system. Different output devices are used to present the output in various
formats, including text, images, hard copies, and audio or video.
Some of the popular output devices are:

1. Monitor

● CRT Monitor
● LCD Monitor
● LED Monitor
● Plasma Monitor

2. Printer

● Impact Printers
A. Character Printers
● Dot Matrix printers
● Daisy Wheel printers
B. Line printers
● Drum printers
● Chain printers
● Non-impact printers

A. Laser printers

B. Inkjet printers

3. Projector
Monitors provide visual output, while printers produce hard copies of documents or images. Projectors
are used to display output on a larger screen or surface.
These output devices serve various purposes and offer different features to meet the diverse needs
of users. They play a crucial role in presenting the processed information to users in a readable,
printable, or viewable format.

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Self-Assessment Questions

18) Which one of the following converts the computer data to human understandable format?

A) Cathode Ray Tube

B) Printer
C) Plotter
D) All the above

19) The output displayed can be in diverse ways such as text, images and hardcopies.

(True/False)

20) Which one of the following allows users to project their output onto a large area, such as
a screen or a wall?

A) Projector
B) Speaker
C) Printer
D) None

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19
1.1.6 Memory or Storage Unit
The memory or storage unit, also known as Random Access Memory (RAM), plays a vital role in a
computer system. It serves as a temporary storage area that holds data, programs, and intermediate
results during processing, enabling the computer to function effectively.
This unit is responsible for storing instructions, data, and intermediate results, supplying information to
other components of the computer as needed. It is commonly referred to as the internal storage unit,
main memory, or primary storage. The size of the memory unit directly impacts the speed, power, and
capability of the computer.
In computer systems, there are two types of memories: primary memory and secondary memory. The
primary memory refers to the main memory unit, such as RAM, while secondary memory encompasses
external storage devices like hard drives and solid-state drives.
The memory unit performs several essential functions, including:

● Storing all the data and instructions required for processing.

● Holding intermediate results during processing.
● Retaining the processed results before they are sent to an output device.
● Serving as the medium through which inputs and outputs are transmitted.

The efficient functioning and capacity of the memory unit significantly influence the overall performance
of a computer system.

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20
Self-Assessment Questions

21) The process of division on memory spaces is called ______.

A) Paging
B) Segmentation
C) Bifurcation
D) Dynamic Division

22) Which one of the following is made up of registers?

A) Memory
B) Storage
C) Both
D) None

23) Which one of the following is a high-speed memory?

A) Primary Memory
B) Cache Memory
C) Both
D) None

24) Which unit can store instructions, data, and intermediate results?

A) Arithmetic Logic Unit

B) Control Unit
C) Storage Unit
D) All the above

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21
 Summary
● Basic computers speak about the main components of the computer that perform core
functions and include Input, CPU (ALU, Memory unit, Control unit), and output unit.
● The input unit takes the user inputs and sends them to the CPU to perform some function.
● The computer’s central processing unit (CPU) is the portion of a computer that retrieves
and executes instructions.
● The CPU is the brain of a CAD system. It consists of an arithmetic and logic unit (ALU), a
control unit, and various registers.
● The CPU is often simply referred to as the processor.
● The instructions passed from the input unit are stored in the memory unit of the CPU.
● The control unit passes the control signals to instruct the system to perform the already
stored instructions in the memory.
● Depending upon the instructions, the ALU performs either arithmetic or logical functions
and the processed data is stored in the memory.
● Finally, the output is fetched from the memory unit and printed on the output device by the
output unit.

Terminal Questions

1. Identify and illustrate the block diagram of the CPU

2. Describe and analyse the functions of its units.
2. Evaluate the roles and responsibilities of the ALU in computer processing.
3. Describe the operations of the Control Unit in a computer system.

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Answer Keys

Self-Assessment Questions
Question No. Answer
1 A
2 A
3 True
4 D
5 A
6 D
7 A
8 B
9 True
10 A
11 C
12 A
13 True
14 B
15 D
16 B
17 B
18 D
19 True
20 A
21 B
22 A
23 B
24 A

Activity

Activity Type: Offline Duration: 30-45 min

1. Draw a CPU block diagram, and then explain the function and interaction of each module
within the diagram.

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 Glossary
● ALU: The part of a computer that does math and makes logical decisions.
● CPU: The brain of a computer that carries out instructions and performs calculations.
● Memory: A temporary storage area for information like apps and files. To keep data
safe, it needs to be stored on a permanent device like a hard drive or CD-ROM.
● I/O port (Input/Output port): A connection point between the computer and external
devices like keyboards, screens, or card readers. It may be an input port or an output
port, or it may be bi-directional.
● Software: Programs and data that give instructions to the computer. It includes
applications, operating systems, and utilities.
● Hardware: The physical components of a computer system, such as the processor,
memory, storage devices, and input/output devices.

Bibliography
● Mano, M. (1992). Computer System Architecture. PHI.
● Stallings, W. (2015). Computer System Architecture. PHI.
● Brown, S., & Vranesic, Z. (2008). Fundamentals of Digital Logic with Verilog Design (2nd
ed.). McGraw-Hill.
● Mano, M. (2017). Digital Logic and Computer Design. Pearson.
● Jain, R. P. (2009). Modern Digital Electronics (4th ed.). Tata McGraw Hill.

e-References
● https://www.tutorialspoint.com/computer_fundamentals/computer_cpu.htm
● https://www.tutorialspoint.com/computer_fundamentals/computer_input_devices.htm
● https://www.tutorialspoint.com/computer_fundamentals/computer_output_devices.htm
● https://study.com/academy/lesson/arithmetic-logic-unit-alu-definition-design-function.
html

Computer Organisation & Architecture

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Video Links

● https://youtu.be/gHMQftD-HJY

Image Credits

● Fig.1: Wikipedia

Keywords
● Processor
● Input devices
● Output devices
● Arithmetic Operations
● Logical Operations
● Cache Memory
● HDD
● SSD
● DDR SDRAM

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 Computer Organisation and Architecture

Module - 1
Unit - 2

Memory

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Table of Contents
Unit 1.2 Memory

Aim ----------------------------------------------------------------------------------------------------- 28
Instructional Objectives -------------------------------------------------------------------------- 28
Learning Outcomes -------------------------------------------------------------------------------- 28
1.2.1 Introduction to Memory -------------------------------------------------------------------- 29
1.2.1.1 Overview of Memory Unit ------------------------------------------------------ 29
1.2.2 Types of Memory ---------------------------------------------------------------------------- 31
1.2.2.1 Random Access Memory ------------------------------------------------------- 31
1.2.2.2 Read-Only Memory --------------------------------------------------------------- 32
Self-Assessment Questions -------------------------------------------------------------- 35
Summary --------------------------------------------------------------------------------------------- 39
Terminal Questions ------------------------------------------------------------------------------- 39
Answer Keys ---------------------------------------------------------------------------------------- 40
Activity  ----------------------------------------------------------------------------------------------- 40
Glossary --------------------------------------------------------------------------------------------- 41
Bibliography ----------------------------------------------------------------------------------------- 41
e-References --------------------------------------------------------------------------------------- 42
Video Links ------------------------------------------------------------------------------------------ 42
Image Credits ---------------------------------------------------------------------------------------- 42
Keywords --------------------------------------------------------------------------------------------- 42

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 Aim
To provide a comprehensive understanding of the various types of memory in a computer
system and their significance in real-world computing scenarios.

Instructional Objectives
This unit intends to:

● Describe the different types of memory

● Explain memory management techniques
● Explore the factors affecting memory access and performance

Learning Outcomes
Upon completion of this unit, you will be able to:

● Identify and differentiate between various types of memory

● Analyse the role of memory in improving system performance
● Evaluate factors influencing memory access and performance in computing scenarios

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1.2.1 Introduction to Memory
In the world of computer architecture, memory plays a critical role in storing and retrieving data for
processing. A memory unit, also known as primary storage or main memory, is an essential component
of a computer system.

1. Definition and Purpose:

A memory unit refers to the internal storage component of a computer system that stores data and
instructions required for current and future processing. It acts as a temporary workspace, facilitating
quick access to data by the central processing unit (CPU). The primary purpose of a memory unit is to
provide fast, efficient, and reliable storage for both program instructions and data during the execution
of computer operations.

2. Functionality:
Memory units are responsible for performing three key functions:

● Data Storage: Memory units store data in binary form, consisting of 0s and 1s, which represent
the fundamental building blocks of information within a computer system. This data can include
program instructions, input data, intermediate results, and output data generated during
computational processes.
● Data Retrieval: The CPU interacts with the memory unit to retrieve stored data and instructions
required for processing. The memory unit ensures quick access and retrieval of information,
enabling the CPU to execute instructions efficiently.
● Data Manipulation: The memory unit facilitates data manipulation by the CPU. It allows the
CPU to read, write, and modify data stored within its memory cells, providing the necessary
workspace for computations and operations.

1.2.1.1 Overview of Memory Unit

Memory units can be defined as the building blocks of storage in a computer system. They are used to
measure and represent the quantity of data that can be stored and accessed by the system. Memory
units are crucial for various computing processes and involve the use of binary digits (0s and 1s) to
represent and manipulate data.
Memory in a computer system consists of two main types: RAM (Random Access Memory) and ROM
(Read-Only Memory). RAM is used to store program instructions and data that can be read from
and written to by the processor during the operation of the computer. ROM, on the other hand, holds
permanent instructions and data that cannot be modified by normal operations.
The primary purpose of memory is to store binary-coded instructions and data. Instructions define
the sequences of operations that the computer should carry out, while data refers to the input and
output information processed by the computer. Memory capacity is typically measured in bytes, and it
is commonly expressed in larger units such as kilobytes (KB), megabytes (MB), gigabytes (GB), and
terabytes (TB).
In computer terminology, a kilobyte (KB) is defined as 1024 bytes due to the binary nature of data stor-
age. Therefore, a KB represents 1024 bytes, not 1000 as in the decimal system.
Overall, memory units play a vital role in storing and accessing instructions and data within a computer
system, enabling efficient computation and data processing.

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 How we perceive it: The reality

address of address of
memory cell RAM ( memory ) memory cell RAM ( memory )

13
00000000 00001101

3
00000001 00000011

0
00000010 00000000

45
00000011 00101101

A memory address Each byte

is 32 bits long !!! has 8 bits

Fig. 1: Overview of Memory Unit

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1.2.2 Types of Memory
Memory is an essential element of a computing system as it enables the computer to perform tasks.
There are two types of memory: RAM and ROM, each serving a different purpose. RAM is used
to store data that the computer is currently using, while ROM stores data required for booting and
operation. RAM allows data to be accessed and modified in any order, making it faster than ROM
which can only be read.
Types of Computer Memory:

1. Random Access Memory (RAM)

2. Read-Only Memory (ROM)

Types of memory

RAM ROM

SRAM DRAM PROM EPROM EEPROM

Fig. 2: Classification of Memory

1.2.2.1 Random Access Memory

Random Access Memory, commonly known as RAM, is a type of volatile memory that allows data to be
read from and written to by the computer’s processor. It provides fast access to data and instructions
during program execution.

● Also known as read-write memory, main memory, or primary memory.

● It stores programs and data required by the CPU during program execution.
● RAM is a volatile memory, meaning data is lost when power is turned off.

RAM is further categorised into two subtypes:

1. Static RAM (SRAM): Static RAM is a type of RAM that uses flip-flop circuits to store data. It is
faster and more expensive than other types of RAM. SRAM is commonly used in cache memory, which
provides quick access to frequently used data.

2. Dynamic RAM (DRAM): Dynamic RAM stores data using capacitors, which need to be refreshed
periodically to retain the data. DRAM is more cost-effective but slower compared to SRAM. It is widely
used as the main memory in computers due to its higher storage capacity.

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Advantages of Random Access Memory (RAM):

● Speed: RAM allows quick access to data compared to other storage types.
● Flexibility: Data stored in RAM can be easily modified or deleted.
● Capacity: RAM capacity can be upgraded to store more data, improving performance.
● Power Management: RAM consumes less power, making it suitable for portable devices.

Disadvantages of Random Access Memory (RAM):

● Volatility: Data stored in RAM is lost when power is turned off, posing a risk to unsaved work.
● Capacity: RAM has limitations and may not be sufficient for memory-intensive tasks.
● Cost: Upgrading RAM can be relatively expensive compared to other memory types.

1.2.2.2 Read-Only Memory

Read-Only Memory, or ROM, is a non-volatile memory that stores data and instructions that cannot be
modified or erased by normal computer operations. It contains firmware and system-specific software
required for booting the computer.
● Stores crucial information essential to operate the system, such as the program required to boot
the computer.
● It is non-volatile, meaning it retains its data even when power is turned off.
● Used in embedded systems or applications where the programming does not need to be
changed.
● Commonly found in calculators and peripheral devices.

ROM is categorised into four subtypes:

1. PROM (Programmable Read-Only Memory): Can be programmed by the user, but the data and
instructions in it cannot be changed once programmed.
2. EPROM (Erasable Programmable Read Only Memory): Can be reprogrammed by erasing data
through exposure to ultraviolet light. All previous data must be erased before reprogramming.

EPROM operates based on a MOS (Metal-Oxide-Semiconductor) transistor. The transistor has a

“floating” gate surrounded by an insulator. Here’s how the programming process works:

● Negative charges form a channel between the source and drain, storing logic 1.
● Applying a large positive voltage at the gate causes negative charges to move out of the channel
and get trapped in the floating gate, storing logic 0.
● To erase the EPROM, UV rays are shone on the surface of the floating gate, causing the
negative charges to return to the channel from the floating gate, restoring logic 1.
● EPROM packages have a quartz window through which UV light can pass, enabling the erasure
process.

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EPROM offers better writability but has reduced storage performance compared to other memory types.
It is commonly used during design development stages where frequent changes to the programmed
data are expected. EPROM uses ultraviolet rays that can penetrate the crystal glass on the package,
allowing for the simultaneous erasure of the entire data stored within.

3. EEPROM (Electrically Erasable Programmable Read Only Memory): The data can be erased
by applying an electric field, allowing selective erasure of portions of the chip. Unlike EPROM, which
requires the entire chip to be erased, EEPROM allows for selective erasure of portions of the chip.
EEPROM is programmed and erased electronically, typically by utilising higher than normal voltage
levels. Some key features of EEPROM include:

● It offers improved writeability, allowing data to be written or modified more easily compared to
other types of memory.
● It can be in-system programmable with built-in circuit to provide the necessary higher voltage
levels.
● It has built-in memory controller, which is commonly used to hide complex details from the
memory user, simplifying the interaction with the memory.
● Due to the erasing and programming processes involved, EEPROM tends to have slower write
speeds compared to other memory types.
● It can endure tens of thousands of erase and program cycles, allowing for data modification
without degradation.
● Shares a similar storage permanence characteristic with EPROM, with data retention typically
lasting around 10 years.
● More convenient to use than EPROM due to the absence of ultraviolet light for erasure. However,
it is generally more expensive.
● EEPROM erases data in 8-bit units, utilising high electrical voltage.

4. MROM (Mask ROM): A type of ROM that is permanently programmed during the manufacturing
process and cannot be modified by the user.

Advantages of Read Only Memory (ROM):

● Non-volatility: ROM retains data even when power is turned off, making it suitable for storing
critical data like BIOS or firmware.
● Reliability: The data in ROM is less prone to corruption or errors compared to other types of
memory.
● Power Management: ROM consumes less power, making it suitable for portable devices.

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Disadvantages of Read Only Memory (ROM):

● Limited Flexibility: ROM is read-only and cannot be modified, which can be problematic for
applications or firmware that require updates.
● Limited Capacity: ROM typically has limited capacity and upgrading it can be difficult or expen-
sive.
● Cost: ROM can be more expensive than other types of memory, impacting the cost of upgrading
computer systems or devices.

Differences between RAM and ROM:

S.No. RAM ROM

Permanent storage
1 Temporary storage

2 Stores data in MBs Stores Data in GBs

3 Volatile Non-volatile

4 Uses in normal operations Uses for startup process of computer

Writing data is faster

5 Writing data is slower

Table 1: Difference between RAM and ROM

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Self-Assessment Questions

1) The chip by which both the operation of read and write is performed __________.

A) RAM
B) ROM
C) PROM
D) EPROM

2) RAM is also known as __________.

A) RWM
B) MBR
C) MAR
D) ROM

3) Which of the following control signals are selected for read and write operations in a RAM?

A) Data buffer
B) Chip select
C) Read and write
D) Memory

4) Computers invariably use RAM for __________.

A) High complexity
B) High resolution
C) High speed main memory
D) High flexibility

5) Which of the following has the capability to store the information permanently?

A) RAM
B) ROM
C) Storage cells
D) Both RAM and ROM

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 6) ROM is made up of ___________.

A) NAND and OR gates

B) NOR and decoder
C) Decoder and OR gates
D) NAND and decoder

7) Why are ROMs (Read Only Memory) called non-volatile memory?

A) They lose memory when power is removed

B) They do not lose memory when power is removed
C) They lose memory when power is supplied
D) They do not lose memory when power is supplied

8) Why is SRAM more preferably in non-volatile memory?

A) low-cost
B) high-cost
C) low power consumption
D) transistor as a storage element

9) Which type of storage element of SRAM is extremely fast in accessing data but con-
sumes lots of power?

A) TTL
B) CMOS
C) NAND
D) NOR

10) What is approximate data access time of SRAM?

A) 4ns
B) 10ns
C) 2ns
D) 60ns

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11) How many MOSFETs are required for SRAM?

A) 2
B) 4
C) 6
D) 8

12) Which memory storage is widely used in PCs and Embedded Systems?

A) SRAM
B) DRAM
C) Flash memory
D) EEPROM

13) Which is the storage element in DRAM?

A) Inductor
B) Capacitor
C) Resistor
D) Mosfet

14) What is the size of a trench capacitor in DRAM?

A) 1 Mb
B) 4-256 Mb
C) 8-128 Mb
D) 64-128 Mb

15) Why was PROM introduced?

A) To increase the storage capacity

B) To increase the address locations
C) To provide flexibility
D) To reduce the size

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 16) Which of the following is programmed electrically by the user?

A) ROM
B) EPROM
C) PROM
D) EEPROM

17) EPROM uses an array of ____________.

A) p-channel enhancement type MOSFET

B) n-channel enhancement type MOSFET
C) p-channel depletion type MOSFET
D) n-channel depletion type MOSFET

18) Address decoding for dynamic memory chip control may also be used for ____________.

A) Chip selection and address location

B) Read and write control
C) Controlling refresh circuits
D) Memory mapping

19) Which one of the following is used for the fabrication of MOS EPROM?

A) TMS 2513
B) TMS 2515
C) TMS 2516
D) TMS 2518

20) How many addresses a MOS EPROM have.

A) 1024
B) 512
C) 2516
D) 256

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Summary
● Memory is a vital system for storing and retrieving information for future use, with functions
of encoding, storing, and retrieval.
● In processor data control, we have RAM (volatile) and ROM (non-volatile) memories.
● RAM serves as temporary storage for actively processed data, erasing when power is off.
● ROM acts as permanent storage for essential input/output operations, such as booting.
● RAM is classified as SRAM (static RAM) widely used in microprocessors, and DRAM (dy-
namic RAM) made of capacitors.
● ROM types include PROM, EPROM, EEPROM, and MROM. PROM is non-erasable, while
EPROM and EEPROM are erasable.
● EPROM utilises ultraviolet light for erasing, while EEPROM relies on electrical means.
● MROM is a read-only memory (ROM) where contents are programmed by the integrated
circuit manufacturer.

Terminal Questions

1. Categorise the various types of Memories based on their characteristics.

2. Analyse and contrast the features of DRAM and SDRAM.
3. Summarise the key aspects of EPROM and EEPROM in a brief note.

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 Answer Keys

Self-Assessment Questions
Question No. Answer
1 A
2 A
3 C
4 C
5 B
6 C
7 B
8 C
9 A
10 A
11 C
12 B
13 B
14 B
15 C
16 C
17 B
18 A
19 C
20 C

Activity

Activity Type: Offline Duration: 30-45 min

1. Summarise and evaluate various memory designs in a report.

2. Research and explore emerging trends in memory technology, such as MRAM or
NVRAM.

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Glossary
● Memory: The electronic data storage crucial for a computer’s operation, including RAM
(random-access memory). It stores programs and data.
● ROM: Read Only Memory. Contains essential instructions for computer startup. User can-
not replace it.
● EPROM: Electrically Erasable Programmable Read-Only Memory chip. Retains memory
even without power. Can be erased and reprogrammed.
● EEPROM: Electrically Erasable Programmable Read-Only Memory chip. Retains memory
even without power. Can be erased and reprogrammed.
● RAM: Random Access Memory. Volatile data storage used for current operations. Access
speed is unaffected by data location.
● SDRAM: Synchronous Dynamic Random-Access Memory. Transfers data in sync with the
memory bus.
● DRAM: Dynamic Random Access Memory. Common memory type that requires constant
refreshing to retain data. Uses capacitors and transistors for temporary data storage.

Bibliography
● Mano, M. (1992). Computer System Architecture. PHI.

● Stallings, W. (2015). Computer System Architecture. PHI.

● Brown, S., & Vranesic, Z. (2008). Fundamentals of Digital Logic with Verilog Design (2nd
ed.). McGraw-Hill.

● Mano, M. (2017). Digital Logic and Computer Design. Pearson.

● Jain, R. P. (2009). Modern Digital Electronics (4th ed.). Tata McGraw Hill.

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 e-References
● https://www.tutorialspoint.com/computer_fundamentals/computer_memory.htm
● https://www.tutorialspoint.com/computer_fundamentals/computer_ram.htm
● https://www.tutorialspoint.com/computer_fundamentals/computer_rom.htm

Video links
● https://youtu.be/nSEfOe88Y0w
● https://youtu.be/sWAsRA-9DgQ
● https://youtu.be/CPOcSGgSxiQ

Image credits
● Fig.1: https://passlab.github.io/ITSC3181/notes/lecture04_MemoryBinarySystem.pdf

● Fig.2: https://media.geeksforgeeks.org/wp-content/uploads/memory.png

Keywords
● RAM
● ROM
● SRAM
● DRAM
● PROM
● EEPROM
● MOSFET

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Computer Organisation and Architecture

Module - 1
Unit - 3

Number System

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43
 Table of Contents
Unit 1.3 Number System

Aim --------------------------------------------------------------------------------------------- 45
Instructional Objectives ------------------------------------------------------------------ 45
Learning Outcomes ------------------------------------------------------------------------ 45
1.3.1 Overview of Number System ---------------------------------------------------- 46
1.3.2 Types of Number Systems ------------------------------------------------------- 47
Self-Assessment Questions ----------------------------------------------------- 50
1.3.3 Conversion of Number Systems ------------------------------------------------ 51
1.3.4 Conversion of Decimal Number System -------------------------------------- 51
Self-Assessment Questions ----------------------------------------------------- 58
1.3.5 Conversion of Binary Number System ---------------------------------------- 59
Self-Assessment Questions ----------------------------------------------------- 64
1.3.6 Conversion of Octal Number System ------------------------------------------ 65
Self-Assessment Questions ----------------------------------------------------- 69
1.3.7 Conversion of Hexadecimal Number System ------------------------------- 70
Self-Assessment Questions ----------------------------------------------------- 74
Summary  ------------------------------------------------------------------------------------ 75
Terminal Questions ----------------------------------------------------------------------- 75
Answer Keys -------------------------------------------------------------------------------- 76
Activity   -------------------------------------------------------------------------------------- 76
Glossary ------------------------------------------------------------------------------------ 77
Bibliography -------------------------------------------------------------------------------- 77
e-References ------------------------------------------------------------------------------ 78
Video Links --------------------------------------------------------------------------------- 78
Image Credits ----------------------------------------------------------------------------- 78
Keywords ------------------------------------------------------------------------------------ 78

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Aim
To provide students with a comprehensive understanding of number systems, including an
introduction to different types and the process of converting between them.

Instructional Objectives
This unit intends to:

● Define and differentiate types of number systems

● Explain the significance of number systems in digital computers
● Demonstrate the process of converting between different number systems

Learning Outcomes
Upon completion of this unit, you will be able to:

● Define and comprehend the concept of number systems

● Enumerate and recognise different types of number systems
● Apply the conversion process from one number system to another
● Evaluate the significance of number systems in digital computers

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1.3.1 Overview of Number System
A number system is a mathematical system that uses a set of symbols or digits to represent numbers
and performs arithmetic operations. It consists of two main parts: the integer portion and the fraction
portion, separated by a radix point.
In a number system with a radix or base of ‘b’, the range of numbers present in that system is from 0
to (b-1). The radix indicates the number of unique symbols or digits used in the number system.

(N)b =dn-1 dn-1 dn-3,...d1 d0 d-1 d-2-d-3... d-m

Integer Portion Fractional Portion

Radix Point

Fig. 1: Number representation format

Let’s break down the variables used in this context:

● N: Represents a specific number within the number system.

● b: Refers to the radix or base of the number system.
● n: Represents the number of digits in the integer portion of the number.
● m: Represents the number of digits in the fractional portion of the number.
● dn-1: Represents the Most Significant Digit (MSD) in the integer portion.
● d-m: Represents the Least Significant Digit (LSD) in the fractional portion.

The commonly used number systems include:

● Binary Number System: Uses a radix of 2 and consists of only two digits, 0 and 1.
● Octal Number System: Uses a radix of 8 and consists of digits from 0 to 7.
● Decimal Number System: Uses a radix of 10 and consists of digits from 0 to 9.
● Hexadecimal Number System: Uses a radix of 16 and consists of digits from 0 to 9, along with
additional symbols A to F to represent values 10 to 15.

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1.3.2 Types of Number Systems
Number systems are different methods of representing and expressing numerical quantities. The
commonly used number systems are:
1. Binary Number System:
The binary number system has a base of 2. Since b=2, it consists of two digits ranging from 0 to 2-1 =
1 (as discussed earlier, the range is from 0 to b-1). Therefore, the binary number system only includes
the digits 0 and 1.
Examples: (1101)2, (110101)2, (0101)2, (101.01)2, etc.

22 21 20 21 22 Positional Values or Weights

101 . 01

Binary Point

Fig. 2: Binary number representation format

In the Binary Number System, the portion to the left of the binary point (integer part) has weights of
20, 21, 22, and so on from right to left. The portion on the right-hand side of the binary point (fractional
part) has weights of 2-1, 2-2, and so on from left to right.
The given binary number (101.01)2 can be represented as:
(101.01)2 = (1 * 22) + (0 * 21) + (1 * 20) + (0 * 2-1) + (1 * 2-2)
By simplifying the terms on the right-hand side of the equation, we obtain the decimal equivalent of the
binary number on the left-hand side, which is (5.25)10.

2. Octal Number System:

The octal number system has a base of 8, indicated by the value of b. As a result, it consists of eight
digits ranging from 0 to 7, as discussed previously. The digits used in the octal number system are 0,
1, 2, 3, 4, 5, 6, and 7.
Examples: (73)8, (420)8, (125.13)8, and so on.

82 81 80 8-1 8-2 Positional Values or Weights

125 . 01

Octal Point

Fig. 3: Octal number representation format

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In the Octal Number System, the positional values or weights to the left of the octal point in the integer
part are assigned as 80, 81, 82, and so on, from right to left. For the fractional part on the right-hand side,
the weights are assigned as 8-1, 8-2, and so on, from left to right.
Let’s take the example of the octal number (125.13)8:
(125.13)8 = (1 * 82) + (2 * 81) + (5 * 80) + (1 * 8-1) + (3 * 8-2)
After simplifying the terms on the right-hand side of the equation, we arrive at the decimal equivalent
of the octal number on the left-hand side, which is (85.140625)10.

3. Decimal Number System:

The Decimal Number System has a base of 10, indicated by the value of b. As a result, it consists of
10 digits ranging from 0 to 9, as discussed previously.
Examples: (101)10, (12)10, (999)10, (540.25)10, and so on.

102 101 100 10-1 10-2 Positional Values or Weights

540 . 25

Decimal Point
Fig. 4: Decimal number representation format

In the Decimal Number System, the positional values or weights to the left of the decimal point in the
integer part are assigned as 100, 101, 102, and so on, from right to left. For the fractional part on the
right-hand side, the weights are assigned as 10-1, 10-2, and so on, from left to right.

Let’s take the example of the decimal number (540.25)10:

(540.25)10 = (5 * 102) + (4 * 101) + (0 * 100) + (2 * 10-1) + (5 * 10-2)
After simplifying the terms on the right-hand side (RHS) of the equation, we obtain the decimal equiv-
alent of the decimal number on the left-hand side (LHS).

4. Hexadecimal Number System:

The Hexadecimal Number System has a base of 16, denoted by the value of b. As a result, it consists
of 16 digits ranging from 0 to 15, as discussed previously.

It consists of both digits and alphabets where digits range from 0 to 9 i.e., 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and
alphabets range from A to F where (A=10), (B=11), (C=12), (D=13), (E=14) and (F=15).

Examples: (123)16, (459)16, (12A3F.12)16, and so on.

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 162 161 160 16-1 16-2 Positional Values or Weights

12A . 13

Hexadecimal Point

Fig. 5: Hexadecimal number representation format

In the Hexadecimal Number System, the positional values or weights to the left of the decimal point
in the integer part are assigned as 160, 161, 162, and so on, from right to left. For the fractional part on
the right-hand side, the weights are assigned as 16-1, 16-2, and so on, from left to right.

Let’s take the example of the hexadecimal number (12A.13)16:

(12A.13)16 = (1 * 162) + (2 * 161) + (10 * 160) + (1 * 16-1) + (3 * 16-2)
After simplifying the terms on the right-hand side of the equation, we obtain the decimal number equiv-
alent to the hexadecimal number on the left-hand side, which is (298.06640625)10.

Table 1: Number systems

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 Self-Assessment Questions

1) 3 x 101 + 4 x 100 is ______.

A) 0.34
B) 3.4
C) 34
D) 340

2) The 1’s complement of 11110000 is ______.

A) 11111111
B) 11111110
C) 00001111
D) 10000001

3) The 2’s complement of 11001100 is ______.

A) 00110011
B) 00110100
C) 00110101
D) 00110110

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1.3.3 Conversion of Number Systems
Conversion of number systems refers to the process of converting a value from one numeral system
to another. It involves transforming a number expressed in a particular base or radix into its equivalent
representation in a different base.

Number Base Conversion

Binary to Decimal to Octal to Hexadeximal to

other Number other Number other Number other Number
System System System System

Binary to Decimal Decimal to Octal to Binary Hexa-decimal to

Binary
Binary to Octal Octal to Decimal Binary
Decimal to Octal
Binary to Hexa- Octal to Hexa-decimal to
decimal Decimal to Hexa-decimal Decimal
Hexadecimal
Hexa-decimal to
Octal

Fig. 6: Classification of Number Conversions

1.3.4 Conversion of Decimal Number System

Converting decimal numbers to other number systems, such as binary, octal, or hexadecimal, involves
dividing the decimal number and extracting remainders or fractions. For binary conversion, successive
divisions by 2 are performed, and the remainders give the binary equivalent. Octal and hexadecimal
conversions use division by 8 and 16, respectively.
(a). Conversion of Decimal Number to Binary Number
In the conversion of a decimal number to a binary number, the decimal integer part is divided by 2
successively until the quotient becomes 0. The remainders obtained from each division, read from
bottom to top, form the binary integer representation.
For the decimal fractional part, it is multiplied by 2 successively until the fractional part becomes 0. The
integers obtained from each multiplication, read from top to bottom, constitute the binary fractional
representation.
To convert a mixed number (containing both integer and fractional parts) to binary, the integral part
and the fractional part are converted separately to binary, and then combined to obtain the final binary
representation.
Let’s consider some examples to illustrate the concept more effectively.

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Example 1: Convert (13.25)10 to (? )2

Solution:

To convert (13.25)10 to binary, we can follow the steps below:

Integral Part:

Divide the decimal integer part (13) by 2 successively until the quotient becomes 0:

13 ÷ 2 = 6 remainder 1

6 ÷ 2 = 3 remainder 0

3 ÷ 2 = 1 remainder 1

1 ÷ 2 = 0 remainder 1

Reading the remainders from bottom to top, we have: (13)10 = (1101)2

Fractional Part:

Multiply the decimal fractional part (0.25) by 2 successively until the fractional part becomes 0:

0.25 × 2 = 0.5

0.5 × 2 = 1.0 (Note: Since the fractional part becomes 0, we stop here.)

Reading the integers obtained from top to bottom, we have: (0.25)10 = (0.01)2

Combining the integral and fractional parts, we get:

(13.25)10 = (1101.01)2

Therefore, (13.25)10 is equivalent to (1101.01)2 in binary.

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Example 2: Convert (15.6)10 to (? )2

Solution:

Converting Integral and Fractional part separately.

Integral Part:
Divide the decimal integer part (15) by 2 successively until the quotient becomes 0:

15 ÷ 2 = 7 remainder 1
7 ÷ 2 = 3 remainder 1
3 ÷ 2 = 1 remainder 1
1 ÷ 2 = 0 remainder 1

Reading the remainders from bottom to top, we have: (15)10 = (1111)2

Fractional Part:
Multiply the decimal fractional part (0.6) by 2 successively until the fractional part becomes 0:

0.6 × 2 = 1.2 (Note: Take only the integer part, which is 1)

0.2 × 2 = 0.4 (Take the integer part, which is 0)
0.4 × 2 = 0.8 (Take the integer part, which is 0)
0.8 × 2 = 1.6 (Take the integer part, which is 1)
0.6 × 2 = 1.2 (Take the integer part, which is 1)

(Note: Since the fractional part repeats the sequence 1100, we can stop here.)
Reading the integers obtained, we have: (0.6)10 = (0.1 1001 1001...)2 (repeating)
Combining the integral and fractional parts, we get:
(15.6)10 = (1111.1100 1100...)2 (repeating)
(or)

(15.6)10 = (1111.1100)2
Therefore, (15.6)10 is equivalent to (1111.1100 1100...)2 (repeating) in binary.

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Note: If the numbers are non-terminating and non-repeating then, in that case, the process of
multiplication is to be stopped after 4 or 5 decimal places.

(b). Conversion of Decimal Number to Octal Number

To convert a decimal number to octal, we follow a similar process as converting decimal to binary.
However, there is a difference in the base used. In the integral part, we successively divide the num-
ber by 8 until the quotient becomes 0. The remainders obtained from each division, read from bottom
to top, represent the equivalent octal digits, with the last remainder being the Most Significant Digit
(MSB).
For the fractional part, we multiply it by 8 until the fractional part of the product becomes 0. The integer
part of each product term, read from top to bottom, gives the equivalent octal digits, starting from the
Most Significant Digit (MSB).
When converting mixed decimal numbers to octal, we separate the integral and fractional parts. Each
part is converted to octal individually, ensuring the correct placement of the digits with respect to their
significance. Finally, we combine the octal integral and fractional parts to obtain the desired octal rep-
resentation.
Let’s consider some examples to illustrate the concept more effectively.

Example 1: Convert (73.625)10 to (? )8

Solution:
To convert the decimal number (73.625)10 to octal, we can follow the pro-
cess of separating the integral and fractional parts and converting them individually.

Integral Part:
We divide the integral part, 73, by 8 successively until the quotient becomes 0:

73 ÷ 8 = 9 remainder 1
9 ÷ 8 = 1 remainder 1
1 ÷ 8 = 0 remainder 1

Reading the remainders from bottom to top, we have the octal equivalent of the integral part: (111)8.
Fractional Part:
For the fractional part, 0.625, we multiply it by 8 successively until the fractional part of the product
becomes 0:
0.625 × 8 = 5

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The integer parts of the product terms, read from top to bottom, represent the octal equivalent of the
fractional part: (5)8.
Combining the integral and fractional parts, we get the final octal representation: (73.625)10 = (111.5)8.

Example 2: Convert (965.198)10 to (? )8

Solution:

To convert the decimal number (965.198)10 to octal, we can follow the process of separating the inte-
gral and fractional parts and converting them individually.

Integral Part:

We divide the integral part, 965, by 8 successively until the quotient becomes 0:

965 ÷ 8 = 120 remainder 5

120 ÷ 8 = 15 remainder 0
15 ÷ 8 = 1 remainder 7
1 ÷ 8 = 0 remainder 1
Reading the remainders from bottom to top, we have the octal equivalent of the integral part: (1705)8.

Fractional Part:
For the fractional part, 0.198, we multiply it by 8 successively until the fractional part of the product
becomes 0:
0.198 × 8 = 1.584
0.584 × 8 = 4.672
0.672 × 8 = 5.376
0.376 × 8 = 3.008
0.008 × 8 = 0.064
The integer parts of the product terms, read from top to bottom, represent the octal equivalent of the
fractional part: (14535)8.
Combining the integral and fractional parts, we get the final octal representation: (965.198)10 =
(1755.14535)8.

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(c). Conversion of Decimal Number to Hexadecimal Number
To convert a decimal number into a hexadecimal number system, we divide the integral part by 16 suc-
cessively until the quotient becomes 0. The remainders obtained from the divisions, read from bottom
to top, represent the equivalent hexadecimal digits, where the bottom digit is the Most Significant Bit
(MSB), and the topmost digit is the Least Significant Bit (LSB).
For the fractional part, we multiply it by 16 successively until the fractional part of the product becomes
0. The integer parts of the product terms, recorded from top to bottom, form the respective hexadeci-
mal digits, where the topmost digit is the MSB.
To convert a mixed decimal number into hexadecimal, we first convert the integral and fractional parts
separately into hexadecimal, and then combine them to get the desired result.
It’s important to note that in the hexadecimal number system, the digits range from 0 to 9, and then
from 10 to 15 are represented as A=10, B=11, C=12, D=13, E=14, and F=15, respectively.
Let’s consider some examples to better understand the conversion of decimal numbers to hexadeci-
mal numbers.

Example 1: Convert (1954.785)10 to (? )16

Solution:
Given decimal number (1954.785)10 is of mixed type and contains both integral (1954)10 and decimal
part (0.785)10. To convert the given number into hexadecimal, we have to convert integral and frac-
tional part individually into hexadecimal and then combine them together to get the required result.

Integral Part:
We successively divide the integral part by 16 until the quotient is 0 and record the remainders from
bottom to top.
1954 ÷ 16 = 122 remainder 2
122 ÷ 16 = 7 remainder 10 (A in hexadecimal)
The remainders are 10 and 2, which correspond to A and 2 in hexadecimal, respectively. So, the inte-
gral part in hexadecimal is A2.

Fractional Part:
For the fractional part, we multiply it by 16 until the fractional part of the product becomes 0. We record
the integer parts of the product terms from top to bottom.
0.785 × 16 = 12.56 (integer part: 12)
0.56 × 16 = 8.96 (integer part: 8)
0.96 × 16 = 15.36 (integer part: 15)
The integer parts are 12, 8, and 15, which correspond to C, 8, and F in hexadecimal, respectively. So,
the fractional part in hexadecimal is (C8F)16.

After converting both integral part and fractional part individually into hexadecimal, now we combine
both to get our desired result i.e., (1954.785)10 = (A2.C8F)16.

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Example 2: Convert (3283.715)10 to (? )16

Solution:
To convert the given number into hexadecimal, we have to convert integral and fractional part indi-
vidually into hexadecimal and then combine them together to get the required result.
Integral Part:

We successively divide the integral part by 16 until the quotient is 0 and record the remainders from
bottom to top.

3283 ÷ 16 = 205 remainder 3

205 ÷ 16 = 12 remainder 13 (D in hexadecimal)

The remainders are 13 and 3, which correspond to D and 3 in hexadecimal, respectively. So, the
integral part in hexadecimal is D3.

Fractional Part:

For the fractional part, we multiply it by 16 until the fractional part of the product becomes 0. We
record the integer parts of the product terms from top to bottom.

0.715 × 16 = 11.44 (integer part: 11)

0.44 × 16 = 7.04 (integer part: 7)
0.04 × 16 = 0.64 (integer part: 0)

The integer parts are 11, 7, and 0, which correspond to B, 7, and 0 in hexadecimal, respectively. So,
the fractional part in hexadecimal is B70.

Combining the integral and fractional parts, we get the hexadecimal representation of (3283.715)10
as (D3.B70)16.

Therefore, (3283.715)10 = (D3.B70)16.

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 Self-Assessment Questions

4) The decimal number 21 is equivalent to the binary number ______.

A) 10101
B) 10001
C) 10000
D) 11111

5) The decimal number + 122 is expressed in the 2’s complement form as ______.

A) 01111010
B) 11111010
C) 01000101
D) 10000101

6) (170)10 is equivalent to ______.

A) (FD)16
B) (DF)16
C) (AA)16
D) (AF)16

7) Convert (0.345)10 into an octal number.

A) (0.16050)8
B) (0.26050)8
C) (0.19450)8
D) (0.24040)8

8) The octal equivalent of the decimal number (417)10 is ______.

A) (641)8
B) (619)8
C) (640)8
D) (598)8

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1.3.5 Conversion of Binary Number System
To convert binary to decimal, each binary digit is multiplied by the corresponding power of 2 (starting
from right to left) and the results are summed. Binary numbers can also be converted to other number
systems like octal and hexadecimal by grouping the binary digits (starting from the left) into sets of
three or four, respectively, and replacing each set with its equivalent in the target number system.
(a). Conversion of Binary Number to Decimal Number
To convert a binary number to its decimal equivalent, we use positional weights by multiplying each bit
with its corresponding power of 2 and summing them.

● In an integral part of the binary number, the positional weights follow the pattern of 20, 21, 22,
23, 24, 25, and so on from right to left.
● In the fractional part of the binary number, the positional weights follow the pattern of 2-1, 2-2,
2-3, 2-4, 2-5, and so on from left to right.
To convert a mixed binary number, we convert its integral and fractional parts individually and then
combine them to obtain the decimal number.
Let’s consider some examples to illustrate the concept more effectively.

Example 1: Convert (101.11)2 to (?)10

Solution:
To convert the binary number (101.11)2 to its decimal equivalent, we use the positional weights and
perform the necessary calculations.
In the integral part, we have:
(101) 2 = (1 * 2²) + (0 * 2¹) + (1 * 2⁰) = 4 + 0 + 1 = 5.
In the fractional part, we have:
(0.11) 2 = (1 * 2-1) + (1 * 2-2) = 0.5 + 0.25 = 0.75.

Combining the integral and fractional parts, we get:

(101.11) 2 = 5 + 0.75 = 5.75.
Therefore, (101.11) 2 is equivalent to (5.75)10 in decimal.

Example 2: Convert (11011.101)2 to (?)10

Solution:
In the integral part, we have:
(11011) 2 = (1 * 2⁴) + (1 * 2³) + (0 * 2²) + (1 * 2¹) + (1 * 2⁰) = 16 + 8 + 0 + 2 + 1 = 27.
In the fractional part, we have:
(0.101) 2 = (1 * 2-1) + (0 * 2-2) + (1 * 2-3) = 0.5 + 0 + 0.125 = 0.625.

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Combining the integral and fractional parts, we get:
(11011.101) 2 = 27 + 0.625 = 27.625.
Therefore, (11011.101) 2 is equivalent to (27.625)10 in decimal.

(b). Conversion of Binary Number to Octal Number

To convert binary numbers into octal numbers, we utilise the relationship between binary and octal
systems. In the octal number system, there are eight digits ranging from 0 to 7. Each octal digit can be
represented using three bits in binary, as there are 2³ = 8 possible combinations.
When converting, we start from the least significant bit (rightmost) of the binary number and group
three successive bits together. This grouping process is done from right to left for the integral part and
from left to right for the fractional part. Each group is then converted to its equivalent octal symbol
based on the table of binary to octal conversions.
It’s important to note that when grouping, one or two additional bits may be added to the left of the
most significant bit (MSB) in the integral part, and/or to the right of the least significant bit (LSB) in the
fractional part, depending on the number of bits in the original binary representation. This ensures that
the groups are properly formed and aligned with the octal system.

Table 2: Octal-Binary numbers

Let’s consider some examples to illustrate the concept more effectively.

Example 1: Convert (110011.011)2 to (? )8

Solution:
To convert the binary number (110011.011) 2 to octal, we will separate the integral and fractional parts
and convert them individually.

Integral Part:
Starting from the rightmost side, we group the bits in sets of three: 110 011. Since we have three
groups, we can directly convert them to their octal equivalents: (6 3)8.

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Fractional Part:
For the fractional part, we start from the left and group the bits in sets of three: 011. We can then con-
vert it to its octal equivalent: (3)8.

Combining the integral and fractional parts, we have (110011.011)2 = (63.3)8.

Example 2: Convert (110011011110.1011)2 to (? )8

Solution:
To convert the binary number (110011011110.1011)2 to octal, we will separate the integral and fraction-
al parts and convert them individually.

Integral Part:
Starting from the rightmost side, we group the bits in sets of three: 110 011 011 110. We can then
convert each group to its octal equivalent: (6 3 3 6) 8.

Fractional Part:
For the fractional part, we start from the left and group the bits in sets of three: 101 100. We can then
convert it to its octal equivalent: (5 4)8.
Combining the integral and fractional parts, we have (110011011110.1011)2 = (6336.54)8.

Note: In the Example 2, to make a group of three bits, we have added two additional bits to the right
of LSB in the fractional part.

(c). Conversion of Binary Number to Hexadecimal Number

Converting binary numbers into hexadecimal numbers follows a similar process as converting binary
to octal, but with some modifications. The relationship between binary numbers and hexadecimal
numbers is given as:

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 Table 3: Decimal–Hexadecimal–Binary numbers

In hexadecimal number system, we have sixteen digits ranging from 0 to 15 which can be represented
using four-bit binary numbers in 24 = 16 ways, so starting from the least significant bit of the binary
number, we group four successive bits of the binary number to get its equivalent hexadecimal number
as seen from the table above.
In the integral part, we group four bits from right to left, and in the fractional part, we group four bits
from left to right, and then convert them to their respective hexadecimal symbols. In the process of
grouping four bits, one/two/three bits can be added to the left of the MSB in an integral part and/or to
the right of the LSB bit of the fractional part of the binary number.
Note: Whenever we need any additional bits, we only add ‘0’ as the additional bit.
Let’s consider some examples to illustrate the concept more effectively.

Example 1: Convert (01111111.1010)2 to (? )16

Solution:
To convert the binary number to hexadecimal, we will separate the integral and fractional parts and
convert them individually.

Integral Part:
Group the binary digits in sets of four from left to right: “0111” and “1111”.
Convert each group to its decimal equivalent: “0111” = 7, “1111” = 15.
In hexadecimal, the decimal values 7 and 15 are represented as “7” and “F” respectively.
Fractional Part:
Consider the fractional part “1010”.

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Convert it to a decimal fraction: 1/21 + 0/22 + 1/23 + 0/24 = 0.5 + 0 + 0.125 + 0 = 0.625.
Convert the decimal fraction 0.625 to hexadecimal: “A”.
Combine Integral and Fractional Parts:
The integral part “0111 1111” becomes “7F” in hexadecimal.
The fractional part “1010” remains as “A” in hexadecimal.

The hexadecimal equivalent of the binary number (01111111.1010)2 is therefore (7F.A)16.

Example 2: Convert (1110011100.110001)2 to (? )16

Solution:
To convert the given binary number to hexadecimal, we need to group the binary digits into sets of
four from left to right, both in the integral and fractional parts. However, in this case, the given binary
number consists of only 10 bits in the integral part and 6 bits in the fractional part, which cannot be
evenly grouped into sets of four.
To accommodate the grouping, we add two zero bits to the left of the most significant bit (MSB) in the
integral part, resulting in a 12-bit integral part. Similarly, we add two zero bits to the right of the least
significant bit (LSB) in the fractional part, resulting in an 8-bit fractional part.
The modified binary number is now: (001110011100.11000100)2
Now, we can group the binary digits into sets of four:
Integral part: 0011 1001 1100
Fractional part: 1100 0100
Converting each set of four binary digits to their hexadecimal equivalents, we get:
Integral part: 3 9 C
Fractional part: C 4

Combining the hexadecimal parts, we obtain the final result:

(1110011100.110001)2 = (39C.C4)16

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 Self-Assessment Questions

9) The decimal equivalent of 1000 is ______.

A) 2
B) 4
C) 6
D) 8

10) The binary number 11011101 is equal to the decimal number______.

A) 121
B) 221
C) 441
D) 256

11) Convert the binary number (01011.1011)2 into decimal:

A) (11.6875)10
B) (11.5874)10
C) (10.9876)10
D) (10.7893)10

12) Convert binary to octal: (110110001010)2 = ?

A) (5512)8
B) (6612)8
C) (4532)8
D) (6745)8

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1.3.6 Conversion of Octal Number System
The conversion of numbers between the octal number system and other number systems is an
essential process in computing and digital systems. The octal number system uses a base of 8 and
consists of digits ranging from 0 to 7. To convert a number from octal to another system, such as
decimal or binary, we use the place values and perform calculations based on the positional weights.

(a). Conversion of Octal Number to Binary Number

To convert octal numbers to binary numbers, we can use a straightforward process. Each digit in the
octal number is replaced by its equivalent binary representation. The conversion table for octal to
binary is as follows:

Table 4: Octal – Binary numbers

By replacing each digit with its binary equivalent, we can obtain the binary representation of the octal
number.
Let’s consider some examples to illustrate the concept more effectively.

Example 1: Convert (73.2)8 into (? )2

Solution:
To convert the octal number (73.2)8 to binary, we need to convert each digit of the octal number to its
binary equivalent.

Starting with the integral part, we have:

Digit 7: 7 in binary is 111.
Digit 3: 3 in binary is 011.

Combining them, we get the integral part in binary as 111011.

Moving to the fractional part, we have:
Digit 2: 2 in binary is 010.

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Combining it with the integral part, we get the fractional part in binary as 010.
Putting them together, the binary representation of (73.2)8 is (111011.010)2.

Example 2: Convert (475.62)8 into (? )2

Solution:
To convert the octal number (475.62)8 to binary, we need to convert each digit of the octal number to
its binary equivalent.
Starting with the integral part, we have:
Digit 4: 4 in binary is 100.
Digit 7: 7 in binary is 111.
Digit 5: 5 in binary is 101.
Combining them, we get the integral part in binary as 100111101.

Moving to the fractional part, we have:

Digit 6: 6 in binary is 110.
Digit 2: 2 in binary is 010.
Combining them, we get the fractional part in binary as 110.010.

Putting them together, the binary representation of (475.62)8 is (100111101.110010)2.

(b). Conversion of Octal Number to Decimal Number

To convert an octal number to a decimal number, we use positional weights and multiply each digit by
the corresponding weight. Then, we sum up the products to obtain the decimal equivalent.
• In the integral part of the octal number, the positional weights follow the pattern of powers of 8:
80, 81, 82, 83, 84, 85, and so on, from right to left.
• In the fractional part of the octal number, the positional weights follow the pattern of reciprocal
powers of 8: 8-1, 8-2, 8-3, 8-4, 8-5, and so on, from left to right.
By multiplying each digit by its corresponding positional weight and summing up the results, we can
determine the decimal equivalent of the octal number accurately.
Let’s consider some examples to illustrate the concept more effectively.

Example 1: Convert (75.3)8 = (? )10

Solution:
To convert the octal number (75.3)8 to its decimal equivalent, we use the positional weights and multi-
ply each digit by the corresponding weight.
In the integral part, the positional weights follow the pattern of powers of 8: 80, 81, 82, and so on, from
right to left. In this case, we have the digits 7 and 5 in the integral part.
(7 * 81) + (5 * 80) = 56 + 5 = 61

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In the fractional part, the positional weights follow the pattern of reciprocal powers of 8: 8-1, 8-2, and so
on, from left to right. In this case, we have the digit 3 in the fractional part.
(3 * 8-1) = 3 * (1/8) = 3/8 = 0.375
Combining the integral and fractional parts, we get the decimal equivalent:
61 + 0.375 = 61.375
Therefore, (75.3)8 is equal to (61.375)10 in decimal.

Shortcut:

(75.3)8 = [7*81 + 5*80] + [3*8-1]

= 56+5+0.375

= (61.375)10

Example 2: Convert (624.712)8 = (? )10

Solution:

(624.712)8 = [6*82 + 2*81 + 4*80] + [7*8-1 + 1*8-2 + 2*8-3]

= 384+ 16 + 4 + 0.875 + 0.015624 + 0.00390625

= (404.894)10

Example 3: Convert (482.31)8 = (? )10

Solution:

The given number (482.31)8 is not a valid octal number because octal numbers only consist of digits
ranging from 0 to 7. As the given number includes the digit 8, it cannot be converted to a decimal
number using octal-to-decimal conversion.

(c). Conversion of Octal Number to Hexadecimal Number

Conversion of an octal number to hexadecimal follows a definite path. We first convert the octal number
to its equivalent binary representation, and then we convert the binary number to hexadecimal.
The conversion process is as follows: Octal Number → Binary Number → Hexadecimal Number.

Example 1: Convert (35.7)8 into (? )16

Solution:

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Step 1: Convert octal number to binary number.

Therefore, (35.7)8 = (011101.111)2

Step 2: Convert binary number to a hexadecimal number.

Therefore, (011101.111)2 = (1D.E)16

Therefore, (35.7)8 = (1D.E)16

Note: To know more about converting binary number to a hexadecimal number, refer to the topic “Con-
version of Binary number to Hexadecimal number.”

Example 2: Convert (73.2)8 into (? )16

Solution:

Step 1: Convert octal number to binary number.

Therefore, (73.2)8 = (111011.010)2

Step 2: Convert binary number to a hexadecimal number.

Therefore, (111011.010)2 = (3B.4)16

Therefore, (73.2)8 = (3B.4)16

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Self-Assessment Questions

13) Octal to binary conversion: (24)8 =

A) (111101)2
B) (010100)2
C) (111100)2
D) (101010)2

14)) Convert octal number (125)8 to decimal number.

A) (85)10
B) (95)10
C) (75)10
D) (65)10

15) Conversion of the octal number (352653)8 to binary number.

A) (011101010110101011)2
B) (00111101010101001)2
C) (001101101010111001)2
D) (001110011011110001)2

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1.3.7 Conversion of Hexadecimal Number System
Conversion of Hexadecimal Number System involves converting numbers from the hexadecimal (base
16) numeral system to other numeral systems such as decimal (base 10), binary (base 2), and octal
(base 8). In the hexadecimal system, there are sixteen digits, ranging from 0 to 9 and A to F, where A
represents 10, B represents 11, and so on. To convert a hexadecimal number to decimal, each digit
is multiplied by the corresponding power of 16 and summed. Converting hexadecimal to binary and
octal involves replacing each digit with its equivalent binary or octal representation. These conversions
are essential in various computer applications, including programming, data storage, and digital
communication.

(a) Conversion of Hexadecimal Number to Binary Number

Conversion of hexadecimal numbers to binary numbers involves representing each hexadecimal digit
with its equivalent binary representation. Each hexadecimal digit corresponds to four bits in binary. For
example, the hexadecimal digit “0” is represented as “0000” in binary, “1” as “0001,” and so on up to
“F” represented as “1111.”
To convert a hexadecimal number to binary, we break down the hexadecimal number into its individual
digits and replace each digit with its corresponding binary representation. The resulting binary digits
are then combined to form the binary equivalent of the hexadecimal number.
For example, to convert the hexadecimal number “A3F” to binary:
“A” is equivalent to “1010” in binary,
“3” is equivalent to “0011” in binary,
“F” is equivalent to “1111” in binary.
Therefore, “A3F” in hexadecimal is “1010001111” in binary.
By following this process, we can convert any hexadecimal number to its binary equivalent.

Table 5: Decimal – Hexadecimal – Binary numbers

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Example 1: Convert (7A.2C)16 into (? )2

Solution:

To convert the hexadecimal number to binary, we replace each hexadecimal digit with its equivalent
binary representation.

Using the table provided above, we can replace hexadecimal numbers with their equivalent binary
digits.

Therefore, (7A.2C)16 = (0111 1010.0010 1100)2

Example 2: Convert (D2A.2B7)16 into (? )2

Solution:

Using the table provided above, we can replace hexadecimal numbers with their equivalent binary
digits.

Therefore, (D2A.2B7)16 = (1101 0010 1010.0010 1011 0111)2

Example 3: Convert (FF18.5E5)16 into (? )2

Solution:

Using the table provided above, we can replace hexadecimal numbers with their equivalent binary
digits.

Therefore, (FF18.5E5)16 = (1111 1111 0001 1000. 0101 1110 0101)2

(b) Conversion of Hexadecimal Number to Octal Number

Conversion of the hexadecimal numbers to octal numbers follows a specific process. We first convert
the hexadecimal number to a binary number, and then convert the binary number to an octal number.

The conversion path is as follows: Hexadecimal Number → Binary Number → Octal Number

Example 1: Convert (1D.E)16 into (? )8

Solution:

Step 1: Convert the first hexadecimal number to a binary number.

Thus, (1D.E)16 = (0001 1101.1110)2

Step 2: Convert the binary number to an octal number, resulting in

(00011101.1110)2 = (35.7)8

Therefore, (1D. E)16 = (35.7)8

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Note: To know how to convert binary number to an octal number, refer to the topic “Conversion of
Binary Number to Octal Number.”

Example 2: Convert (3B.4)16 into (? )8

Solution:

Step 1: Convert the first hexadecimal number to a binary number.

Thus, (3B.4)16 = (0011 1011.0100)2

Step 2: Convert the binary number to an octal number, resulting in

(0011 1011.0100)2 = (73.20)8

Therefore, (3B.4)16 = (73.20)8

(c) Conversion of Hexadecimal Number to Decimal Number

To convert a hexadecimal number into a decimal number, we use the positional weights by multiplying
each digit with the corresponding weight and summing them up.
● In the integral part of the hexadecimal number, the weights follow the pattern as 160, 161, 162,
163, 164, 165, and so on from right to left.
● In the fractional part of the hexadecimal number, the weights follow the pattern as 16-1, 16-2,
16-3, 16-4, 16-5, and so on from left to right.
It’s important to note that in hexadecimal representation, A = 10, B = 11, C = 12, D = 13, E = 14, and
F = 15.
By calculating the products and summing them up, we can obtain the decimal equivalent of the hexa-
decimal number.

Example 1: Convert (75.3)16 into (? )10

Solution:
Step 1: Convert the integral part of the hexadecimal number to decimal.
(75)16 = (7 * 161) + (5 * 160) = (117)10
Step 2: Convert the fractional part of the hexadecimal number to decimal.
(0.3)16 = (3 * 16-1) = (0.1875)10

Combine the integral and fractional parts to obtain the decimal equivalent.
(75.3)16 = (117)10 + (0.1875)10 = (117.1875)10

Therefore, (75.3)16 is equal to (117.1875)10.

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Example 2: Convert (CD3.B70A)16 into (? )10

Solution:
Step 1: Convert the integral part of the hexadecimal number to decimal.
(CD3)16 = (12 * 162) + (13 * 161) + (3 * 160) = (3283)10
Step 2: Convert the fractional part of the hexadecimal number to decimal.
(B70A)16 = (11 * 16-1) + (7 * 16-2) + (0 * 16-3) + (10 * 16-4) = (0.718994)10

Combine the integral and fractional parts to obtain the decimal equivalent.
(CD3.B70A)16 = (3283)10 + (0.718994)10 = (3283.718994)10

Therefore, (CD3.B70A)16 is equal to (3283.718994)10.

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 Self-Assessment Questions

16) The given hexadecimal number (1E.53)16 is equivalent to ______.

A) (35.684)8
B) (36.246)8
C) (34.340)8
D) (35.599)8

17) Convert the hexadecimal number (1E2)16 to decimal:

A) 480
B) 483
C) 482
D) 484

18) Convert the hexadecimal number (7CF)16 to decimal:

A) (711)10
B) (6781)10
C) (19999)10
D) (1019)10

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Summary
● Number systems are mathematical notations used to express numbers in a consistent
manner.
● They provide unique representations for numbers and reflect their arithmetic and alge-
braic structure.
● Decimal, binary, octal, and hexadecimal are types of number systems.
● Decimal to binary conversion involves recursively dividing the decimal number by 2 and
noting down the remainders.
● Decimal to octal conversion divides the integral part by 8 and multiplies the fractional
part by 8 until the quotient or product is 0.
● Decimal to hexadecimal conversion involves dividing the integral part by 16 and multi-
plying the fractional part by 16 until 0 is reached.
● Binary to decimal conversion requires adding up place values multiplied by the corre-
sponding bits.
● Binary to octal conversion involves grouping three bits from right to left in the integral
part and left to right in the fractional part to obtain the octal symbol.
● Binary to hexadecimal conversion involves grouping four digits from right to left in the
integral part and left to right in the fractional part to obtain the hexadecimal symbol.
● Octal to binary conversion replaces octal numbers with their equivalent binary digits.
● Octal to decimal conversion adds up positional weights multiplied by the corresponding
bits.
● Octal to hexadecimal conversion involves first converting to binary and then to hexadec-
imal.
● Hexadecimal to binary conversion is done using the relationship between hexadecimal
and binary numbers.
● Hexadecimal to octal conversion follows the path of conversion to binary first and then
to octal.

Terminal Questions
1. Convert the Binary number (101010.1011)2 into Decimal, Hexadecimal and Octal.

2. Convert the Octal number (235.51)8 into Binary and Hexadecimal.

3. Convert the Hexadecimal number (A3C.2B)16 in to Decimal and Binary.

4. Convert the Decimal number (235.92)10 into Octal, Hexadecimal, and Binary.

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 Answer Keys

Self-Assessment Questions
Question No. Answer
1 C
2 C
3 B
4 A
5 A
6 C
7 B
8 A
9 D
10 B
11 A
12 B
13 B
14 A
15 A
16 B
17 C
18 C

Activity
Activity Type: Offline Duration: (30-40 min)

Four types of number system using the following data: (23.54)8, (93.54)10, (2A.54)16,
(101101.1011)2

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Glossary
● Bit: The smallest unit of information in computing, representing a binary digit (0 or 1).
● Byte: A unit of digital information composed of eight bits.
● Binary Number: A number system that uses only two digits, 0 and 1, to represent values.
● Decimal Number: A number system with a base of ten, using digits 0-9 to represent val-
ues.
● Hexadecimal Number: A number system with a base of sixteen, using digits 0-9 and
letters A-F to represent values.
● Octal Number: A number system with a base of eight, using digits 0-7 to represent val-
ues.
● Radix: The base or the number of unique digits used in a particular number system.
● Place Value: The value assigned to a digit based on its position within a number, which
contributes to the overall value of the number.
● Conversion: The process of transforming a number from one number system to another.
● Arithmetic Operations: Mathematical operations such as addition, subtraction, multipli-
cation, and division performed on numbers in various number systems.
● Overflow: A condition that occurs when the result of an arithmetic operation exceeds the
maximum representable value in a given number system.

Bibliography
● Mano, M. (1992). Computer System Architecture. PHI.
● Stallings, W. (2015). Computer System Architecture. PHI.
● Brown, S., & Vranesic, Z. (2008). Fundamentals of Digital Logic with Verilog Design (2nd
ed.). McGraw-Hill.
● Mano, M. (2017). Digital Logic and Computer Design. Pearson.
● Jain, R. P. (2009). Modern Digital Electronics (4th ed.). Tata McGraw Hill.

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 e-References
● https://www.tutorialspoint.com/computer_fundamentals/computer_number_system.htm
● https://www.tutorialspoint.com/computer_fundamentals/computer_number_conversion.
htm

Video links
● https://youtu.be/crSGS1uBSNQ
● https://youtu.be/4ae9sJBBkvw

Image Credits

● Fig. 1: Number representation format - https://www.includehelp.com/basics/Images/num-

ber-systems-1.jpg
● Fig. 2: Binary number representation format - https://www.includehelp.com/basics/Imag-
es/number-systems-1.jpg
● Fig. 3: Octal number representation format - https://www.includehelp.com/basics/Imag-
es/number-systems-1.jpg
● https://www.includehelp.com/basics/Images/number-systems-1.jpg
● Fig. 5: Hexadecimal number representation format - https://www.includehelp.com/basics/
Images/number-systems-1.jpg
● Fig. 6: Classification of Number Conversions - https://www.javatpoint.com/conver-
sion-of-number-system-in-digital-electronics

Keywords
● Base
● Numeral
● Radix Point
● Positional Notation
● Complement
● Arithmetic Operations
● Floating-Point Representation
● Overflow and Underflow
● Sign Bit
● Binary Coded Decimal (BCD)

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 Computer Organisation and Architecture

Module - 2
Unit - 1

Boolean Algebra and

Logic Gates

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Module Description
The “Boolean Algebra and Logic Gates” module is a foundational guide to grasp the principles and
applications of digital systems. It introduces you to the concepts of Boolean algebra, operations within
Boolean algebra, and the use of logic gates in digital circuit design.
You will begin by exploring Boolean algebra, which is a mathematical system developed by George
Boole. You will gain a deep understanding of Boolean operators, including AND, OR, and NOT, and
learn how these operators can be used to manipulate and simplify logical expressions. Through
practical examples and exercises, you will develop proficiency in applying Boolean algebra to analyse
and solve problems in digital systems.
The module then progresses to the study of operations within Boolean algebra. You will explore Boolean
functions, truth tables, and logic gates. You will discover how logic gates, such as AND, OR, XOR,
and NAND gates, can be combined to perform complex logical operations. By analysing truth tables
and understanding the behaviour of logic gates, you will develop the skills to design and optimise
digital circuits. By comprehending the principles behind Boolean algebra and logic gates, you will be
equipped with the necessary knowledge to contribute to the advancement of modern technology.
By the end of this module, you will have a solid foundation in Boolean algebra and logic gates. You will
be able to analyse, design, and optimise digital circuits using Boolean expressions, truth tables, and
logic gates. This knowledge will prepare you for more advanced topics in digital systems and open
doors to further exploration in the field of computer science.

Unit 2.1 Boolean Algebra

Unit 2.2 Operations of Boolean Algebra
Unit 2.3 Logic Gates, Truth Table and Logic Design

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Table of Contents
Unit 2.1 Boolean Algebra

Aim ------------------------------------------------------------------------------------------------------- 82
Instructional Objectives ----------------------------------------------------------------------------- 82
Learning Outcomes --------------------------------------------------------------------------------- 82
2.1.1 Boolean Algebra, Rules, and Properties of Boolean Algebra --------------------- 83
         Self-Assessment Questions --------------------------------------------------------------- 86
2.1.2 Boolean Functions --------------------------------------------------------------------------- 87
         Self-Assessment Questions --------------------------------------------------------------- 89
2.1.3 De Morgan’s Theorem ----------------------------------------------------------------------   90
         Self-Assessment Questions --------------------------------------------------------------- 94
Summary -----------------------------------------------------------------------------------------------    95
Terminal Questions ----------------------------------------------------------------------------------    95
Answer Keys ----------------------------------------------------------------------------------------- 96
Activity -------------------------------------------------------------------------------------------------     96
Glossary -----------------------------------------------------------------------------------------------   97
Bibliography  ----------------------------------------------------------------------------------------- 97
e-References  ---------------------------------------------------------------------------------------- 97
Video Links ------------------------------------------------------------------------------------------- 97
Image Credits  --------------------------------------------------------------------------------------- 97
Keywords  --------------------------------------------------------------------------------------------- 98

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 Aim
To develop a comprehensive understanding of Boolean algebra, including its rules, properties,
functions, and the application of De Morgan’s Theorem.

Instructional Objectives
This unit intends to:

● Describe the significance of Boolean algebra in computer applications

● Demonstrate the rules, properties, and application of Boolean algebra
● Explain the De Morgan’s theorem for optimising logical expressions

Learning Outcomes
Upon completion of this unit, you will be able to:

● Illustrate the role of Boolean functions in digital circuit design

● Apply Boolean functions to design and analyse digital circuits
● Analyse and evaluate logical expressions using De Morgan’s theorem

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2.1.1 Boolean Algebra
The logical symbols 0 and 1 are used for representing the digital input or output. The symbols “1” and
“0” can also be used for a permanently open and closed digital circuit. The digital circuit can be made
up of several logic gates. To perform the logical operation with minimum logic gates, a set of rules
were invented, known as the Laws of Boolean Algebra. These rules are used to reduce the number
of logic gates for performing logic operations.

DID The Boolean algebra is used for simplifying and analysing the complex
YOU Boolean expression. It is also known as Binary algebra because we only
KNOW use binary numbers in this. George Boole developed the binary algebra
in 1854.

Rules in Boolean algebra

1. Only two values (1 for high and 0 for low) are possible for the variable used in Boolean algebra.

2. The overbar (-) is used for representing the complement variable. So, the complement of vari-
able C is represented as.

3. The plus (+) operator is used to represent the ORing of the variables.

4. The dot(.) operator is used to represent the ANDing of the variables.

Properties of Boolean algebra

These are the following properties of Boolean algebra:

1) Annulment Law
When the variable is AND with 0, it will give the result 0, and when the variable is OR with 1, it will
give the result 1, i.e.,

B.0 = 0

B+1 = 1

2) Identity Law
When the variable is AND with 1 and OR with 0, the variable remains the same, i.e.,

B.1 = B

B+0 = B

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3) Idempotent Law
When the variable is AND and OR with itself, the variable remains same or unchanged, i.e.,

B.B = B

B+B = B

4) Complement Law
When the variable is AND and OR with its complement, it will give the result 0 and 1 respectively.

B.B’ = 0

B+B’ = 1

5) Double Negation Law

This law states that, when the variable comes with two negations, the symbol gets removed and the
original variable is obtained.

((A)’)’ = A

6) Commutative Law
This law states that no matter in which order we use the variables. It means that the order of variables
does not matter in this law.

A.B = B.A

A+B = B+A

7) Associative Law
This law states that the operation can be performed in any order when the variables priority is of same
as ‘*’ and ‘/’.

(A.B).C = A. (B.C)

(A+B) +C = A+(B+C)

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8) Distributive Law
This law allows us to open of brackets. Simply, we can open the brackets in the Boolean expressions.

A+ (B.C) = (A+B). (A+C

A.(B+C) = (A.B) + (A.C)

9) Absorption Law
This law allows us for absorbing the similar variables.

B+ (B.A) = B

B.(B+A) = B

10) De Morgan’s Law

The operation of an OR and AND logic circuit will remain same if we invert all the inputs, change
operators from AND to OR and OR to AND, and invert the output.

(A.B)’ = A’+B’

(A+B)’ = A’. B’

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 Self-Assessment Questions

1) Algebra of logic is termed as ______________.

A) Numerical logic
B) Boolean algebra
C) Arithmetic logic
D) Boolean number

2) Boolean algebra can be used ____________.

A) For designing of the digital computers

B) In building logic symbols
C) Circuit theory
D) Building algebraic functions

3) Logic high in Boolean language is represented with _________.

A) Logic 0
B) Logic 1
C) Logic X
D) None of the above

4) Which of the following is the De Morgan’s formula for (X.Y)’:

A) X’ + Y’
B) X’ – Y’
C) X’ * Y’
D) X’/Y’

5) Which of the following are the theorems of Boolean algebra:

A) De Morgan’s theorem
B) Consensus theorem
C) Shannon’s theorem
D) All the above

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2.1.2 Boolean Functions
The binary variables and logic operations are used in Boolean algebra. The algebraic expression is
known as Boolean Expression, is used to describe the Boolean Function. The Boolean expression
consists of the constant value 1 and 0, logical operation symbols, and binary variables.

Example 1: F=xy’ z+p

We defined the Boolean function F=xy’ z+p in terms of four binary variables x, y, z, and p. This func-
tion will be equal to 1 when x=1, y=0, z=1 or z=1.

Example 2:
F (A, B, C, D) = A + BC’ +ACD
Boolean Function = Boolean Expression

The output Y is represented on the left side of the equation. So,

Apart from the algebraic expression, the Boolean function can also be described in terms of the truth
table. We can represent a function using multiple algebraic expressions. They are their logical equiv-
alents. But for every function, we have only one unique truth table.

In truth table representation, we represent all the possible combinations of inputs and their result. We
can convert the switching equations into truth tables.

Example: F (A, B, C, D) =A+BC’+D

The output will be high when A=1 or BC’=1 or D=1 or all are set to 1. The truth table of the above
example is given below. The 2n is the number of rows in the truth table. The n defines the number of
input variables. So, the possible input combinations are 23=8.

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 Table 1: Truth Table of A+BC’+D

  

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Self-Assessment Questions

6) The canonical forms of Boolean Expressions are

A) OR and XOR
B) NOR and XNOR
C) MAX and MIN
D) SOM and POM

7) F (X, Y, Z, M) = X`Y`Z`M`. The degree of the function is _________.

A) 2
B) 5
C) 4
D) 1

8) The ___________ of all the variables in direct or complemented from is a maxterm.

A) addition
B) product
C) moduler
D) subtraction

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2.1.3 De Morgan’s Theorem
De Morgan’s First Theorem
According to the first theorem, the complement result of the AND operation is equal to the OR operation
of the complement of that variable. Thus, it is equivalent to the NAND function and is a negative-OR
function proving that (A.B)’ = A’+B’ and we can show this using the following table.

Table 2: De-Morgan’s First Theorem Truth Table

Fig. 1: De Morgan’s First Theorem Logic Circuit

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De Morgan’s Second Theorem
According to the second theorem, the complement result of the OR operation is equal to the AND
operation of the complement of that variable. Thus, it is the equivalent of the NOR function and is a
negative-AND function proving that (A+B)’ = A’. B’ and we can show this using the following truth table.

Table 3: De Morgan’s Second Theorem Truth Table

Fig. 2: De Morgan’s Second Theorem Logic Circuit

Let us take some examples in which we take some expressions and apply De Morgan’s theorems.

Example 1: (A.B.C)’

(A.B.C)’=A’+B’+C’

Example 2: (A+B+C)’

(A+B+C)’=A’. B’.C

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Example 3: ((A+BC’)’+D.(E+F’)’)’

For applying the De Morgan’s theorem on this expression, we must follow the following expressions:

1) In complete expression, first, we find those terms on which we can apply the De Morgan’s theorem
and treat each term as a single variable.

So,

2) Next, we apply De Morgan’s first theorem. So,

3) Next, we use rule number 9, i.e., (A=(A’)’) for canceling the double bars.

4) Next, we apply De Morgan’s second theorem. So,

5) Again, apply rule number 9 to cancel the double bar

Now, this expression has no term in which we can apply any rule or theorem. So, this is the final ex-
pression.

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Example 3: (AB’. (A + C))’+ A’B. (A + B + C’)’

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 Self-Assessment Questions

9) Which of the following scientist presented De Morgans theorem?

A) Augustus De Morgan
B) Charles De Morgan
C) Richard De Morgan
D) None of the above

10) De Morgans theorem solves _____ expressions.

A) Boolean algebra
B) Logic gates
C) Arithmetic
D) Both a and b

11) Which of the following is the reason behind De Morgan’s theorem?

A) Design digital circuit

B) Explains complement of sum of all input variables
C) Equals the product of the complement of every term
D) All the above

12) A NAND gate in De Morgans formula for (X.Y)’ is also called __________.

A) Bubbled OR
B) Bubbled NOR
C) Bubbled XOR
D) Bubbled NOT

13) Which of the following logic gates are required for representing De Morgans NAND gate:

A) AND
B) NOT
C) OR
D) Both a and b

14) A never true of unary operation is also called __________.

a) Unary falsum
b) Unary identity
c) Unary negation
d) Unary true

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Summary
● Boolean algebra is the category of algebra in which the variable’s values are the truth
values, true and false, ordinarily denoted 1 and 0, respectively.
● The set of rules called Laws of Boolean Algebra are invented to perform logical operations
with minimum logical gates.  
● The properties of Boolean Algebra includes Annulment, Identity, Idempotent, Competent,
Double Negation, Commutative, Associative, Distributive, Absorption and De Morgans Law.
● The Boolean function is expressed by Boolean Expression.
● A Boolean expression is composed of a combination of the Boolean constants (True or
False), Boolean variables and logical connectives.
● De Morgan’s Theorem uses two sets of rules or laws to solve various Boolean algebra
expressions by changing OR’s to AND’s, and AND’s to OR’s.
● De Morgan’s First theorem proves that when two (or more) input variables are AND’ed and
negated, they are equivalent to the OR of the complements of the individual variables.
● De Morgan’s Second theorem proves that when two (or more) input variables are OR’ed
and negated, they are equivalent to the AND of the complements of the individual variables.

Terminal Questions
1. Solve X•Y+X•Y’=X

2. Find the complement of (X+Y) (X’+Z)

3. Obtain the truth table for F =X+X’Y+X’Z

4. Prove the following expression is true or false using Boolean algebra. A + AB = A + B

5. Prove the following expressing is true or false using Boolean algebra. (A + B) (A + C) = A

+ BC

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 Answer Keys

Self-Assessment Questions
Question No. Answer
1 C
2 A
3 B
4 A
5 D
6 D
7 D
8 A
9 A
10 D
11 D
12 A
13 D
14 A

Activity

Activity Type: Offline Duration: 25-35 min

1. Use De Morgan’s Theorem, as well as any other applicable rules of Boolean algebra, to
simplify the following expression so there are no more complementation bars extending over
multiple variables:

__________

__       ___

AB +   AC

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Glossary
● Annulment Law: A term AND‘ed with a “0” equals 0 or OR‘ed with a “1” will equal 1
● Boolean Expression: Terms written in Boolean algebra that express the output of a
circuit in terms of the input.
● Boolean Function: A function having for ‘n’ number of variables, 2n number of
combinations with the input variables.  
● De Morgan’s Theorems: It states that the complement of a sum (OR operation) equals
the product (AND operation) of the complements, and that the complement of a product
(AND operation) equals the sum (OR operation) of the complements.
● Idempotent Law – An input that is AND‘ed or OR´ed with itself is equal to that input

Bibliography
● Mano, M. (1992). Computer System Architecture. PHI.
● William Stallings. (1987). Computer System Architecture. PHI.
● Brown, S., & Vranesic, Z. (2002). Fundamentals of Digital Logic with Verilog Design (2nd
ed). McGraw-Hill.
● Mano, M. (1979). Digital Logic and Computer Design. Pearson.
● Jain, R. P. (2009). Modern Digital Electronics (4th ed). Tata McGraw Hill.

e-References
● https://www.electronics-tutorials.ws/boolean/bool_6.html  
● https://www.electronics-tutorials.ws/boolean/bool_7.html
● https://www.electronics-tutorials.ws/boolean/bool_8.html
● https://www.electronics-tutorials.ws/boolean/demorgan.html

Video links
● https://youtu.be/AnQsznjccUw

Image credits
● Fig.1: De Morgan’s First Theorem Logic Circuit

https://www.javatpoint.com/de-morgans-theorem-of-boolean-algebra-in-digital-electronics

● Fig.2: De Morgan’s Second Theorem Logic Circuit

https://www.javatpoint.com/de-morgans-theorem-of-boolean-algebra-in-digital-electronics  

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 Keywords
● Boolean Laws
● De Morgan’s Theorems
● Annulment Law
● Identity Law

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98
  

Computer Organisation and Architecture

Module - 2
Unit - 2

Operations of Boolean
Algebra

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 Table of Contents
Unit 2.2 Operations of Boolean Algebra
Aim  --------------------------------------------------------------------------------------------------- 101
Instructional Objectives  ------------------------------------------------------------------------- 101
Learning Outcomes ------------------------------------------------------------------------------- 101
2.2.1 Laws and Rules of Boolean Algebra -------------------------------------------------- 102
         Self-Assessment Questions ------------------------------------------------------------- 111
Summary --------------------------------------------------------------------------------------------   112
Terminal Questions --------------------------------------------------------------------------------   112
Answer Keys ---------------------------------------------------------------------------------------- 113
Activity ------------------------------------------------------------------------------------------------    113
Glossary ---------------------------------------------------------------------------------------------   114
Bibliography -----------------------------------------------------------------------------------------   114
e-References ---------------------------------------------------------------------------------------   114
Video Links ----------------------------------------------------------------------------------------- 115
Image Credits  -------------------------------------------------------------------------------------- 115
Keywords  ------------------------------------------------------------------------------------------- 115

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Aim
To introduce the concepts of the Operations of Boolean Algebra, Laws and Rules of Boolean
Algebra.

Instructional Objectives
This unit intends to:

● Explain the operations of Boolean Algebra

● Describe the laws and rules of Boolean Algebra

Learning Outcomes
Upon completion of this unit, you will be able to:

● Analyse the operations of Boolean Algebra

● Explain the various laws and rules of Boolean algebra

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2.2.1 Laws and Rules of Boolean algebra
In simplification of the Boolean expression, the laws and rules of the Boolean algebra play a key role.
Before understanding these laws and rules of Boolean algebra, first let’s try to grasp the Boolean op-
erations addition and multiplication concept.

1) Boolean Addition
The addition operation of Boolean algebra is similar to the OR operation. In digital circuits, the OR op-
eration is used to calculate the sum term, without using AND operation. A + B, A + B’, A + B + C’, and
A’ + B + + D’ are some of the examples of ‘sum term’. The value of the sum term is true when one or
more than one literal is true and false when all the literals are false.

2) Boolean Multiplication
The multiplication operation of Boolean algebra is like the AND operation. In digital circuits, the AND
operation calculates the product, without using OR operation. AB, AB, ABC, and ABCD are some of the
examples of the product term. The value of the product term is true when all the literals are true and
false when any one of the literals is false.

Laws of Boolean algebra

These are the following laws of Boolean algebra:

1) Commutative Law
This law states that no matter in which order we use the variables. It means that the order of variables
does not matter. In Boolean algebra, the OR and the addition operations are similar. In the below dia-
gram, the OR gate display that the order of the input variables does not matter at all.

For two variables, the commutative law of addition is written as:

A+B = B+A

Fig. 1: Commutative Law (OR)

For two variables, the commutative law of multiplication is written as:

A.B = B.A

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 Fig. 2: Commutative Law (AND)

2) Associative Law
This law states that the operation can be performed in any order when the variables priority is same.
As ‘*’ and ‘/’ have same priority. In the below diagram, the associative law is applied to the 2-input OR
gate.

For three variables, the associative law of addition is written as:

A + (B + C) = (A + B) + C

Fig. 3: Associate Law (AND)

For three variables, the associative law of multiplication is written as:

A(BC) = (AB)C

According to this law, no matter in what order the variables are grouped when ANDing more than two
variables. In the below diagram, the associative law is applied to 2-input AND gate.

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 Fig. 4: Associate Law (OR)

3) Distributive Law:
According to this law, if we perform the OR operation of two or more variables and then perform the
AND operation of the result with a single variable, then the result will be similar to performing the AND
operation of that single variable with each two or more variable and then perform the OR operation of
that product. This law explains the process of factoring.

For three variables, the distributive law is written as:

A (B + C) = AB + AC

Fig. 5: Distributive Law

Rules of Boolean algebra

There are the following rules of Boolean algebra, which are mostly used in manipulating and simplify-
ing Boolean expressions. These rules play a significant role in simplifying Boolean expressions.

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 Table 1: Boolean algebra 12 Rules

1) Rule 1: A + 0 = A

Let us suppose; we have an input variable A whose value is either 0 or 1. When we perform OR
operation with 0, the result will be the same as the input variable. So, if the variable value is 1, then
the result will be 1, and if the variable value is 0, then the result will be 0. Diagrammatically, this rule
can be defined as:

Fig. 6: Rule-1 A + 0 = A Logic Circuit

2) Rule 2: (A + 1) = 1

Let us suppose; we have an input variable A whose value is either 0 or 1. When we perform OR
operation with 1, the result will always be 1. So, if the variable value is either 1 or 0, then the result will
always be 1. Diagrammatically, this rule can be defined as:

Fig. 7: Rule-2 (A + 1) = 1 Logic Circuit

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3) Rule 3: (A.0) = 0

Let us suppose; we have an input variable A whose value is either 0 or 1. When we perform the AND
operation with 0, the result will always be 0. This rule states that an input variable ANDed with 0 is
equal to 0 always. Diagrammatically, this rule can be defined as:

Fig. 8: Rule-3 (A.0) = 0 Logic Circuit

4) Rule 4: (A.1) = A

Let us suppose; we have an input variable A whose value is either 0 or 1. When we perform the AND
operation with 1, the result will always be equal to the input variable. This rule states that an input
variable ANDed with 1 is equal to the input variable always. Diagrammatically, this rule can be defined
as:

Fig. 9: Rule-4 (A.1) = A Logic Circuit

5) Rule 5: (A + A) = A

Let us suppose; we have an input variable A whose value is either 0 or 1. When we perform the OR
operation with the same variable, the result will always be equal to the input variable. This rule states
an input variable ORed with itself is equal to the input variable always. Diagrammatically, this rule can
be defined as:

Fig. 10: Rule-5 (A + A) = A Logic Circuit

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6) Rule 6: (A + A’) = 1

Let us suppose; we have an input variable A whose value is either 0 or 1. When we perform the OR
operation with the complement of that variable, the result will always be equal to 1. This rule states that
a variable ORed with its complement is equal to 1 always. Diagrammatically, this rule can be defined
as:

Fig. 11: Rule-6 (A + A’) = 1 Logic Circuit

7) Rule 7: (A.A) = A

Let us suppose; we have an input variable A whose value is either 0 or 1. When we perform the AND
operation with the same variable, the result will always be equal to that variable only. This rule states
that a variable ANDed with itself is equal to the input variable always. Diagrammatically, this rule can
be defined as:

Fig. 12: Rule-7 (A.A) = A Logic Circuit

8) Rule 8: (A.A’) = 0

Let us suppose; we have an input variable A whose value is either 0 or 1. When we perform the AND
operation with the complement of that variable, the result will always be equal to 0. This rule states
that a variable ANDed with its complement is equal to 0 always. Diagrammatically, this rule can be
defined as:

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 Fig. 13: Rule-8 (A.A’) = 0 Logic Circuit

9) Rule 9: A = (A’)’

This rule states that if we perform the double complement of the variable, the result will be the same
as the original variable. So, when we perform the complement of variable A, then the result will be A’.
Further if we again perform the complement of A’, we will get A, that is the original variable.

Fig. 14: Rule-9 A = (A’)’ Logic Circuit

10) Rule 10: (A + AB) = A

We can prove this rule by using the rule 2, rule 4, and the distributive law as:

A + AB = A (1 + B) Factoring (distributive law)

A + AB = A.1 Rule 2: (1 + B) = 1
A + AB = A               Rule 4: A .1 = A

Fig. 15: Rule-10 (A + AB) = A Logic Circuit

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11) Rule 11: A + AB = A + B

We can prove this rule by using the above rules as:

A + AB = (A + AB)+ AB Rule 10: A = A + AB

A+AB= (AA + AB)+ AB Rule 7: A = AA
A+AB=AA +AB +AA +AB Rule 8: adding AA = 0
A+AB= (A + A)(A + B) Factoring
A+AB= 1.(A + B) Rule 6: A + A = 1
A+AB=A + B Rule 4: drop the 1

Fig. 16: Rule-11 A + AB = A + B Logic Circuit

12) Rule 12: (A + B) (A + C) = A + BC

We can prove this rule by using the above rules as:

(A + B)(A + C)= AA + AC + AB + BC Distributive law

(A + B)(A + C)= A + AC + AB + BC Rule 7: AA = A
(A + B)(A + C)= A( 1 + C)+ AB + BC Rule 2: 1 + C = 1
(A + B)(A + C)= A.1 + AB + BC Factoring (distributive law)
(A + B)(A + C)= A(1 + B)+ BC Rule 2: 1 + B = 1
(A + B)(A + C)= A.1 + BC Rule 4: A .1 = A
(A + B)(A + C)= A + BC

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 Fig. 17: Rule-12 (A + B) (A + C) = A + BC Logic Circuit

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Self-Assessment Questions
1) Which of the following is a Simplification law?

A) M.(~M+N) = M.N
B) M+ (N.O) = (M+N) (M+O)
C) ~(M+N) = ~M.~N
D) M. (N.O) = (M.N). O

2) Which of the following is/are the universal logic gates?

A) OR and NOR
B) AND
C) NAND and NOR
D) NOT

3) Which of the following logic gates are required for representing De Morgans NAND
gate?

A) AND
B) NOT
C) OR
D) Both a and b

4) Which of the following is the output of (X+Y+Z)’ = (X’ Y’ Z’) when (X Y Z) = (0 0 0)?

A) 1
B) 0
C) X
D) None of the above

5) Which of the following is the example of distributive law of Boolean Algebra?

A) X + Y = Y + X
B) X.Y = Y.X
C) X +(Y+Z) = (X+Y) +Z
D) X.(Y+Z) = (X.Y) + (X.Z)

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 Summary
● Boolean operations, addition and multiplication concepts are used for simplification of the
Boolean expressions.

● Boolean addition operation is similar to the OR operation. In digital circuits, the OR opera-
tion is used to calculate the sum term, without using AND operation.

● Boolean multiplication operation is similar to the AND operation. In digital circuits, the AND
operation is used to calculate the product term, without using OR operation.

● The law of Boolean Algebra includes Associative law, Commutative and Distributive law.

● Commutative law states that the use of variables can be in any order.

● Associative law states that if the variables priority is same, the operation can be performed
in any order.

● Distributive law explains factoring.

● To simplify Boolean expressions, there are nine rules that are followed.

Terminal Questions
1. Use Boolean laws to find equivalent expression for XY+YZ+YZ’

2. Find the logic circuit for F =(X+Y) (X’Y+Z)

3. Draw the logic diagram for the given function F = XY+X’Z+X (Y’+Z’)

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Answer Keys

Self-Assessment Questions
Question No. Answer
1 A
2 C
3 D
4 A
5 D

Activity

Activity Type: Offline Duration: 30-45 min

1) Optimise and construct logic circuit for given Boolean equation:

F=ABC+ABC’+AB’C+A’BC+A’BC’  

Z= (A+B’+C) (A+B’+C’) (A’+B+C) (A’+B’+C) (A+B+C)

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 Glossary

● Associative law: This law states that the operation can be performed in any order when
the variables priority is same.

● Commutative law: If any logical operation of two Boolean variables gives the same result
irrespective of the order of those two variables, then that logical operation is said to be
Commutative.

● Distributive law: If any logical operation can be distributed to all the terms present in the
Boolean function, then that logical operation is said to be Distributive.

● Logic circuit: An integrated circuit which provides a fixed set of output signals according
to the signals present at the input.

Bibliography

● Mano, M. (1992). Computer System Architecture. PHI.

● Stallings, W. (2015). Computer System Architecture. PHI.
● Brown, S., & Vranesic, Z. (2008). Fundamentals of Digital Logic with Verilog Design (2nd
ed.). McGraw-Hill.
● Mano, M. (2017). Digital Logic and Computer Design. Pearson.
● Jain, R. P. (2009). Modern Digital Electronics (4th ed.). Tata McGraw Hill.

e-References
● https://www.electronics-tutorials.ws/boolean/bool_6.html  
● https://www.electronics-tutorials.ws/boolean/bool_7.html
● https://www.electronics-tutorials.ws/boolean/bool_8.html
● https://www.electronics-tutorials.ws/boolean/demorgan.html

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Video Links
● https://youtu.be/AnQsznjccUw

Image Credits
● Fig.1: Commutative Law (OR)
● Fig.2: Commutative Law (AND)
● Fig.3: Associate Law (AND)
● Fig.4: Associate Law (OR)
● Fig.5: Distributive Law
● Fig.6: Rule-1 A + 0 = A Logic Circuit
● Fig.7: Rule-2 (A + 1) = 1 Logic Circuit
● Fig.8: Rule-3 (A.0) = 0 Logic Circuit
● Fig.9: Rule-4 (A.1) = A Logic Circuit
● Fig.10: Rule-5 (A + A) = A Logic Circuit
● Fig.11: Rule-6 (A + A’) = 1 Logic Circuit
● Fig.12: Rule-7 (A.A) = A Logic Circuit
● Fig.13: Rule-8 (A.A’) = 0 Logic Circuit
● Fig.14: Rule-9 A = (A’)’ Logic Circuit
● Fig.15: Rule-10 (A + AB) = A Logic Circuit
● Fig.16: Rule-11 A + AB = A + B Logic Circuit
● Fig.17: Rule-12 (A + B) (A + C) = A + BC Logic Circuit
● (https://www.javatpoint.com/laws-and-rules-of-boolean-algebra-in-digital-electronics)

Keywords
● Boolean Laws
● De Morgan’s Theorems
● Commutative Law

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 Computer Organisation and Architecture

Module - 2
Unit - 3

Logic Gates, Truth Table,

and Logic Design

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Table of Contents
Unit 2.3 Logic Gates, Truth Table, and Logic Design

Aim ---------------------------------------------------------------------------------------------   118

Instructional Objectives  ------------------------------------------------------------------- 118
Learning Outcomes ------------------------------------------------------------------------   118
2.3.1 Logic Gates, Truth Table, and Logic Design. --------------------------------- 119
         Self-Assessment Questions ------------------------------------------------------ 126
Summary --------------------------------------------------------------------------------------     131
Terminal Questions -------------------------------------------------------------------------   131
Answer Keys --------------------------------------------------------------------------------- 132
Activity -----------------------------------------------------------------------------------------    132
Glossary ---------------------------------------------------------------------------------------   133
Bibliography ----------------------------------------------------------------------------------   133
e-References ---------------------------------------------------------------------------------   133
Video Links -----------------------------------------------------------------------------------   134
Image Credits --------------------------------------------------------------------------------   134
Keywords ------------------------------------------------------------------------------------- 134

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 Aim
To introduce students to the basic concepts of Logic gates to design Logic gates-based
Combinational Logic circuits for computer architecture modules.  

Instructional Objectives
This unit intends to:

● Describe the logic gates to design optimised combinational logic circuits

● Explain the Truth table and Logic Design for the several Logic Gates

Learning Outcomes
Upon completion of this unit, you will be able to:

● Summarise the logic gates operation for combinational logic circuits design
● Analyse the Truth table and Logic Design for the several Logic Gates

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2.3 .1 Logic Gates, Truth Table and Logic Design
Logic gates play an important role in circuit design and digital systems. It is a building block of a digital
system and an electronic circuit that always have only one output. These gates can have one input or
more than one input, but most of the gates have two inputs. On the basis of the relationship between
the input and the output, these gates are named as AND gate, OR gate, NOT gate, etc.

There are different types of gates which are as follows:

1) AND Gate
This gate works in the same way as the logical operator “and”. The AND gate is a circuit that performs
the AND operation of the inputs. This gate has a minimum of 2 input values and an output value.

A logic gate used to perform logical multiplication is known as AND gate. An AND gate is a logic circuit
having two or more inputs and one output. The output of an AND gate is HIGH only when all of its
inputs are in the HIGH state. In all other cases, the output is LOW. The logic symbol and truth table
of a two-input AND gate is shown in figure. The AND operation on two independent logic variables A
and B is written as Y = A.B and reads as Y equals A AND B. The operation of a two-input AND gate is
explained by the logic expression.

Y=A AND B AND C AND D……N

Y=A.B.C. D……N
Y=ABCD……N

Logic Design

Fig. 1: 2-input AND Gate

Truth Table

Table 1: AND Gate Truth Table

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2) OR Gate
This gate works in the same way as the logical operator “or”. The OR gate is a circuit which performs
the OR operation of the inputs. This gate also has a minimum of 2 input values and an output value.

A logic gate used to perform the operation of logical addition is called an OR gate. An OR gate
performs an ORing operation on two or more than two logic variables. The OR operation on two
independent logic variables A and B is written as Y = A+B and reads as Y equals A OR B. An OR
gate is a logic circuit with two or more inputs and one output. The output of an OR gate is LOW only
when all of its inputs are LOW. For all other possible input combinations, the output is HIGH. A truth
table lists all possible combinations of input binary variables and the corresponding outputs of a logic
system. Figure shows the circuit symbol and the truth table of a two-input OR gate. The operation of
a two-input OR gate is explained by the logic expression.  

Y=A OR B OR C OR D……N

Y=A+B+C+D……N

Logic Design

Fig. 2: 2-input OR Gate

Truth Table

Table 2: OR Gate Truth Table

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3) NOT Gate
The NOT gate is also called an inverter. This gate gives the inverse value of the input value as a result.
This gate has only one input and one output value.

A logic gate used to perform logical inversion is known as a NOT gate. A NOT gate is a one -input, one-
output logic circuit whose output is always the complement of the input. That is, a LOW input produces
a HIGH output, and vice versa. If X is the input to a NOT circuit, then its output Y is given by Y = Ā or A’
and reads as Y equals NOT A. The logic symbol and truth table of a NOT gate is shown in figure. The
operation of a NOT gate is explained by the logic expression                                                                

Y=NOT A

Y=A’

Logic Design

Fig. 3: NOT Gate

Truth Table

Table 3: NOT Gate Truth Table

4) NAND Gate
The NAND gate is the combination of AND gate and NOT gate. This gate gives the same result as a
NOT-AND operation. This gate can have two or more than two input values and only one output value.

NAND Gate is known as Universal gate as it can be used alone to implement any gate operation.
Hence it is said to be functionally complete.

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NAND stands for NOT AND. An AND gate followed by a NOT circuit makes it a NAND gate. The
output of a NAND gate is logic ‘0’ when all its inputs are logic ‘1’. For all other input combinations, the
output is logic ‘1’. The symbol and truth table of a NAND gate is as shown. NAND gate operation is
logically expressed as  

Y=A NOT AND B NOT AND C NOT AND D……N

Y=A NAND B NAND C NAND D……N

Y= (A. B. C. D ……. N)’  

Logic Design

Fig. 4: 2-input NAND Gate

Truth Table

Table 4: NAND Gate Truth Table

5) NOR Gate
The NOR gate is the combination of an OR gate and NOT gate. This gate gives the same result as the
NOT-OR operation. This gate can have two or more than two input values and only one output value.

NOR gate is also known as Universal gate as it is used alone to implement any gate operation and
hence it is also functionally complete.

NOR stands for NOT OR. An OR gate followed by a NOT circuit makes it a NOR gate. The output of
a NOR gate is logic ‘1’ when all its inputs are logic ‘0’. For all other input combinations, the output is
logic ‘0’. The symbol and truth table of a NOR gate is as shown. The output of a two-input NOR gate
is logically expressed as  

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Y=A NOT OR B NOT OR C NOT OR D……N

Y=A NOR B NOR C NOR D……N

Y= (A+ B+C+D+……. +N)’  

Logic Design

Fig. 5: 2-input NOR Gate

Truth Table

Table 5: NOR Gate Truth Table

6) XOR Gate
The XOR gate is also known as the Ex-OR gate. The XOR gate is used in half and full adder and
subtractor. The exclusive-OR gate is sometimes called as EX-OR and X-OR gate. This gate can have
two or more than two input values and only one output value.

The EXCLUSIVE-OR gate, commonly written as EX-OR gate, is a two-input, one-output gate. The
output of an EX-OR gate is logic ‘1’ when the inputs are unlike and logic ‘0’ when the inputs are
like. Although EX-OR gates are available in integrated circuit form only as two-input gates, unlike
other gates which are available in multiple inputs also, multiple-input EX-OR logic functions can be
implemented using more than one two-input gates. The output of a multiple-input EX-OR logic function
is logic ‘1’ when the number of 1s in the input sequence is odd and logic ‘0’ when the number of 1s in
the input sequence is even, including zero. The symbol and truth table of an EX-OR gate is shown in
figure. The output of a two-input EX-OR gate is logically expressed as

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Y=A XOR B XOR C XOR D……N

Y=ABCD……N
Y=AB’+A’B

Logic Design

Fig. 6: 2-input XOR Gate

Truth Table

Table 6: XOR Gate Truth Table

7) XNOR Gate
The XNOR gate is also known as the Ex-NOR gate. The XNOR gate is used in half and full adder and
subtractor. The exclusive-NOR gate is sometimes called as EX-NOR and X-NOR gate. This gate can
have two or more than two input values and only one output value.

The output of a two-input EX-NOR gate is logic ‘1’ when the inputs are like and logic ‘0’ when they are
unlike. In general, the output of a multiple-input EX-NOR logic function is logic ‘0’ when the number of
1s in the input sequence is odd and a logic ‘1’ when the number of 1s in the input sequence is even
including zero.

EXCLUSIVE-NOR (commonly written as EX-NOR) means NOT of EX-OR, i.e., the logic gate that we
get by complementing the output of an EX-OR gate. The truth table of an EX-NOR gate is obtained from
the truth table of an EX-OR gate by complementing the output entries as shown in figure. Logically,

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Y=A XNOR B XNOR C XNOR D……N
Y=ABCD……N
Y=A’B’+AB

Logic Design

Fig. 7: 2-input XNOR Gate

Truth Table

Table 7: XNOR Gate Truth Table

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 Self-Assessment Questions

1) The logical gates are categorised into ___________.

A) One group
B) Two groups
C) Three groups
D) Four groups

2) __________ are arithmetic gates.

A) NOT
B) NAND & NOR
C) X-OR & X-NOR
D) NOT, AND, & OR

3) _________ are the common forms of complex logic gates.

A) OR-AND-Invert (OAI)
B) AND-OR-Invert (AOI)
C) Both OAI and AOI
D) None of the above

4) What is the standard form of DCDVS logic?

A) Differential Cascade Voltage Switch

B) Differential Cascade Voltage Static
C) Differential Complex Voltage Switch
D) None of the above

5) What are the advantages of static complementary gates?

A) Reliable
B) Not easy to use
C) Not reliable
D) Reliable and easy to use

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6) The sum of products canonical forms also known as __________.

A) Minterm expansion
B) Disjunctive normal form
C) Both a and b
D) None of the above

7) ______ is an example of dominance law.

A) a+0=0+a=a
B) 1+a=a+1=1
C) ab=ba
D) a+(b+c)=(a+b)+c

8) Combinational logic is used to ___________.

A) Compute outputs
B) Compute new states
C) Both a and b
D) None of the above

9) The sequential logic contains ___________.

A) Memory elements
B) Memory is provided by feedback
C) Both a and b
D) None of the above

10) _________ are the methods used to represent negative integer numbers.

A) 1’s compliment
B) Sign magnitude
C) 2’s compliment
D) All of the above

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 11) The base is 16 for _______ number system.

A) Binary
B) Hexadecimal
C) Decimal
D) Octal

12) What is the standard form of ECDIC?

A) Extended Binary Coded Decimal Interchange Code

B) Extended Binary Coded Hexadecimal Interchange Code
C) Extended Binary Coded Decimal Information Code
D) None of the above

13) The ones complement of binary number 1010 is ___________.

A) 0101
B) 1010
C) 0110
D) 1110

14) The base is eight for _______ number system.

A) Binary
B) Hexadecimal
C) Decimal
D) Octal

15) How many gates does ultra large-scale integration contain.

A) 100 gates
B) 1000 gates
C) 10000 gates
D) More than 100,000 gates

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16) How many gates does very large-scale integration contain.

A) 100 gates
B) 10,000 to 100,000 gates
C) 10000 gates
D) None of the above

17) The base is ten for _______ number system.

A) Binary
B) Hexadecimal
C) Decimal
D) Octal

18) The propagation time delay of the silicon gate CMOS is _________.

A) 2ns
B) 7ns
C) 10ns
D) 8ns

19) Which IC is a triple three-input AND gate?

A) 74LS11
B) 74LS10
C) 74LS12
D) None of the above

20) Which IC is a triple three-input NAND gate?

A) 74LS11
B) 74LS10
C) 74LS27
D) None of the above

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 21) Which IC is a triple three-input NOR gate?

A) 74LS10
B) 74LS11
C) 74LS27
D) All of the above

22) Which IC is a dual four-input NAND gate?

A) 74LS20
B) 74LS21
C) 74LS27
D) None of the above

23) Which IC is a hex NOT gate?

A) 74LS04
B) 74LS19
C) 74LS23
D) None of the above

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Summary
● A logic gate is a device that acts as a building block for digital circuits. They perform basic
logical functions that are fundamental to digital circuits.  

● Most electronic devices we use today will have some form of logic gates in them.

● The different type of logic gates is AND, OR, NOT, NAND, NOR, XOR, XNOR.

● The logical multiplication operation of the input variables is performed by logical gate
AND.

● The logical addition operation of the input variables is performed by logical gate OR.

● The logical inversion operation is performed by the NOT GATE.

● NAND is a universal gate that performs all the gate operations.

● NOR gate is also a universal gate that can perform all the gate operations.

● XOR is two input and one output gate.

● XNOR is the logic gate of the complement of an EX-OR gate.

Terminal Questions

1. Explain the Universal logic gates function using truth table.

2. Draw and explain the EXOR and EXNOR Logic gates functions.

3. Construct and explain the OR and AND logic gate.

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 Answer Keys

Self-Assessment Questions
Question No. Answer
1   C
2   C
3   C
4   A
5   D
6 C
7 B
8 C
9 C
10 D
11 B
12 A
13 A
14 D
15 D
16 B
17 C
18 D
19 A
20 B
21 C
22 A
23 A

Activity
Activity Type: Offline Duration: 40-45 min

1. Construct logic circuit using logic gates for given Boolean equation:  

F= AB+C

2. Write truth table for given Boolean equation:

F=A+BC’

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Glossary

● AND gate: A basic logic operation in which a true (HIGH) output occurs only when al the
input conditions are true (HIGH).
● Exclusive-OR (XOR) gate: A basic logic operation in which a HIGH occurs when the two
inputs are at opposite levels.
● NAND gate: A logic circuit in which a LOW output occurs only if all the inputs are HIGH.
● OR gate: A logic gate that produces a HIGH output when one or more inputs are HIGH.
● NOR gate: A logic gate that produces a HIGH output when all the inputs are LOW.
● NOT gate: A logic gate that produces a HIGH output when the inputs is LOW.

Bibliography

● Mano, M. (1992). Computer System Architecture. PHI.

● Stallings, W. (2015). Computer System Architecture. PHI.
● Brown, S., & Vranesic, Z. (2008). Fundamentals of Digital Logic with Verilog Design (2nd
ed.). McGraw-Hill.
● Mano, M. (2017). Digital Logic and Computer Design. Pearson.
● Jain, R. P. (2009). Modern Digital Electronics (4th ed.). Tata McGraw Hill.

e-References

● https://epgp.inflibnet.ac.in/epgpdata/uploads/epgp_content/S000574EE/P001494/
M015065/ET/1459848930et05.pdf
● https://www.electronics-tutorials.ws/logic/logic_10.html

● http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html

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 Video Links

● https://youtu.be/0lwhoQ5aQe8
● https://youtu.be/hp0eoiP_v3c

Image Credits
Fig.1: 2-input AND Gate
● https://www.javatpoint.com/and-gate-in-digital-electronics
Fig.2: 2-input OR Gate
● https://www.javatpoint.com/logic-gates-in-digital-electronics
Fig.3: NOT Gate
● https://www.javatpoint.com/not-gate-in-digital-electronics
Fig.4: 2-input NAND Gate
● https://www.javatpoint.com/nand-gate-in-digital-electronics
Fig.5: 2-input NOR Gate
● https://www.javatpoint.com/nor-gate-in-digital-electronics
Fig.6: 2-input XOR Gate
● https://www.javatpoint.com/logic-gates-in-digital-electronics
Fig.7: 2-input XNOR Gate
● https://www.javatpoint.com/logic-gates-in-digital-electronics

Keywords
● Logic Gates
● Truth Tables
● Boolean Equations
● XNOR gate

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 Computer Organisation and Architecture

Module - 3
Unit - 1

Karnaugh Map (K-Map)

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Module Description
Simplifying the Boolean functions using Boolean postulates and theorems is a time-consuming process
and we must re-write the simplified expressions after each step.
To overcome this difficulty, Maurice Karnaugh introduced a method in 1953 for simplification of Boolean
functions in an effortless way.

The Karnaugh map (KM or K-map) is a method of simplifying Boolean algebra expressions. The
Karnaugh map reduces the need for extensive calculations by taking advantage of humans’ pattern-
recognition capability. It also permits the rapid identification and elimination of potential race conditions.
Race hazards are extremely easy to spot using a Karnaugh map, because a race condition may exist
when moving between any pair of adjacent, but disjoint, regions circumscribed on the map.

Karnaugh maps are used to simplify real-world logic requirements so that they can be implemented
using a minimum number of logic gates. With such wide applications, learning K-Maps gives a better
understanding of the simplification of Boolean functions.

The main criterion in the design of a digital circuit is that its cost should be as low as Possible. For that
the expression used to realise that circuit must be minimal. Since the cost is proportional to number
of gate inputs in the circuit, an expression is considered minimal only if it corresponds to the least
possible number of gate inputs.
Hence, the minimisation techniques are especially useful and helpful to make the circuit minimal in
design and the learner must be aware of all the techniques for developing high-end technology that
makes the emerging technologies like nanotechnology to develop with new inventions in all the fields.
Therefore, this module attempts to introduce the concepts K-Map and the Minimisation techniques that
all the learners must be aware of to gain expertise in this area.

This module has 2 units.

Unit 3.1 Karnaugh Map (K-Map)

Unit 3.2 Minimisation Techniques

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Table of Contents
Unit 3.1 Karnaugh Map (K-Map)
Aim  -------------------------------------------------------------------------------------------------- 138
Instructional Objectives  ------------------------------------------------------------------------ 138
Learning Outcomes  ----------------------------------------------------------------------------- 138
3.1.1 Karnaugh Map (K-Map) method ------------------------------------------------------ 139
         Self-Assessment Questions ------------------------------------------------------------ 142
3.1.2 Simplification of Boolean expressions using Karnaugh Map ------------------ 143
          Self-Assessment Questions ----------------------------------------------------------- 156
Summary -------------------------------------------------------------------------------------------    157
Terminal Questions  ------------------------------------------------------------------------------ 157
Answer Keys --------------------------------------------------------------------------------------- 158
Activity -----------------------------------------------------------------------------------------------     158
Glossary --------------------------------------------------------------------------------------------   159
Bibliography  --------------------------------------------------------------------------------------- 159
e-References   ------------------------------------------------------------------------------------ 159
Video Links   --------------------------------------------------------------------------------------- 159
Image Credits  ------------------------------------------------------------------------------------- 160
Keywords  ------------------------------------------------------------------------------------------ 160

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 Aim
To introduce students to the basic concepts of K-Map based Logic optimisation methods to
design Logic gates based Combinational Logic circuits for computer architecture modules.  

Instructional Objectives
This unit intends to:

● Demonstrate why optimised combinational logic circuits are important in various computer
applications
● Explain K-Map method and types
● Discuss the simplification of Boolean Expressions using K-map

Learning Outcomes
Upon completion of this unit, you will be able to:

● Analyse Optimisation by K-maps and types

● List K-map methods and types
● Apply K-maps for the simplification of Boolean Expressions

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3.1.1 Karnaugh Map (K-Map) method
The K-map is a systematic way of simplifying Boolean expressions. With the help of the K-map method,
we can find the simplest POS and SOP expression, which is known as the minimum expression. The
K-map provides a cookbook for simplification.

Just like the truth table, a K-map contains all the possible values of input variables and their
corresponding output values. However, in K-map, the values are stored in cells of the array. In each
cell, a binary value of each input variable is stored.

The K-map method is used for expressions containing 2, 3, 4, and 5 variables. For a higher number
of variables, there is another method used for simplification called the Quine-McClusky method. In
K-map, the number of cells is similar to the total number of variable input combinations. For example,
if the number of variables is three, the number of cells is 23=8, and if the number of variables is four,
the number of cells is 24. The K-map takes the SOP and POS forms. The K-map grid is filled using
0’s and 1’s. The K-map is solved by making groups. There are the following steps used to solve the
expressions using K-map:

1. First, we find the K-map as per the number of variables.

2. Find the maxterm and minterm in the given expression.
3. Fill cells of K-map for SOP with 1 respective to the minterms.
4. Fill cells of the block for POS with 0 respective to the maxterm.
5. Next, we create rectangular groups that contain total terms in the power of two like 2, 4, 8,
… and try to cover as many elements as we can in one group.
6. With the help of these groups, we find the product terms and sum them up for the SOP
form.

1) Two Variable K-Map

The number of cells in 2 variable K-map is four, since the number of variables is two. The following
figure shows 2 variable K-Map.

     

Table 1: Two Variable K-Map

● There is only one possibility of grouping 4 adjacent min terms.

● The possible combinations of grouping 2 adjacent min terms are {(m0, m1), (m2, m3), (m0,
m2) and (m1, m3)}.

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2) Three Variable K-Map
The number of cells in 3 variable K-map is eight, since the number of variables is three. The following
figure shows 3 variable K-Map.

Table 2: Three Variable K-Map

● There is only one possibility of grouping 8 adjacent min terms.

● The possible combinations of grouping 4 adjacent min terms are {(m0, m1, m3, m2), (m4, m5,
m7, m6), (m0, m1, m4, m5), (m1, m3, m5, m7), (m3, m2, m7, m6) and (m2, m0, m6, m4)}.
● The possible combinations of grouping 2 adjacent min terms are {(m0, m1), (m1, m3), (m3, m2),
(m2, m0), (m4, m5), (m5, m7), (m7, m6), (m6, m4), (m0, m4), (m1, m5), (m3, m7) and (m2, m6)}.
● If x=0, then 3 variable K-map becomes 2 variable K-map.

3) Four Variable K-Map

The number of cells in 4 variable K-map is sixteen, since the number of variables is four. The following
figure shows 4 variable K-Map.

     

                                                          Table 3: Four Variable K-Map

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 ● There is only one possibility of grouping 16 adjacent min terms.

● Let R1, R2, R3 and R4 represents the min terms of first row, second row, third row and fourth
row, respectively. Similarly, C1, C2, C3 and C4 represents the min terms of first column,
second column, third column and fourth column, respectively. The possible combinations
of grouping 8 adjacent min terms are {(R1, R2), (R2, R3), (R3, R4), (R4, R1), (C1, C2), (C2, C3),
(C3, C4), (C4, C1)}.

● If w=0, then 4 variable K-map becomes 3 variable K-map.

4) Five Variable K-Map

The number of cells in 5 variable K-map is thirty-two, since the number of variables is 5. The following
figure shows 5 variable K-Map.

                                                       Table 4: Five Variable K-Map

● There is only one possibility of grouping 32 adjacent min terms.

● There are two possibilities of grouping 16 adjacent min terms. i.e., grouping of min terms
from m0 to m15 and m16 to m31.

● If v=0, then 5 variable K-map becomes 4 variable K-map.

In the above all K-maps, we used exclusively the minterms notation. Similarly, you can use exclusively
the maxterms notation.

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 Self-Assessment Questions

1) A Karnaugh map (K-map) is a theoretical form of representing ___________.

A) Circuit diagram
B) Block diagram
C) Logic diagram
D) Venn diagram

2) Which of the following method is used to minimise Boolean expressions?

A) Fourier transform
B) Gray code
C) Karnaugh mapping
D) Venitch method

3) If n denotes the number of variables, then the number of cells is given as:

A) 2n
B) 2 + n
C) 2 – n
D) 2n

4) A 4-variable Karnaugh map has:

A) 12 cells
B) 16 cells
C) 18 cells
D) 20 cells

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3.1.2 Simplification of Boolean expressions using Karnaugh Map
As we know that K-map takes both SOP and POS forms. So, there are two possible solutions for
K-map, i.e., minterm and maxterm solution. Let us start and learn about how we can find the minterm
and maxterm solution of K-map.

1) Minterm Solution of K Map

There are the following steps to find the minterm solution or K-map:

Step 1:

Firstly, we define the given expression in its canonical form.

Step 2:

Next, we create the K-map by entering 1 to each product-term into the K-map cell and fill the remain-
ing cells with zeros.

Step 3:

Next, we form the groups by considering each one in the K-map.

                                            Fig. 1: Grouping of 1’s in K-map

Notice that each group should have the largest number of ‘ones’. A group cannot contain an empty
cell or cell that contains 0.

Fig. 2: Right representation of grouping of 1’s

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In a group, there is a total of 2n number of ones. Here, n=0, 1, 2, …n.

Example: 20=1, 21=2, 22=4, 23=8, or 24=16.

Fig. 3: Grouping of three 1’s of K-Map

We group the number of ones in the decreasing order. First, we have to try to make the group of eight,
then for four, after that two and lastly for 1.

Fig. 4: Grouping of 1’s in decreasing order

In horizontal or vertical manner, the groups of ones are formed in shape of rectangle and square. We
cannot perform the diagonal grouping in K-map.

                                 Fig. 5: Grouping of 1’s in horizontal or vertical manner

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The elements in one group can also be used in diverse groups only when the size of the group is
increased.

Fig. 6: Grouping of 1’s in different group

The elements located at the edges of the table are adjacent. So, we can group these elements.

                                          Fig. 7: Grouping of 1’s at the adjacent of table

We can consider the ‘don’t care condition’ only when they aid in increasing the group-size. Otherwise,
‘don’t care’ elements are discarded.

Fig. 8: Grouping of 1’s in the “do not care condition”

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Step 4:

In the next step, we find the Boolean expression for each group. By looking at the common variables
in cell-labelling, we define the groups in terms of input variables. In the below example, there is a total
of two groups, i.e., group 1 and group 2, with two and one number of ‘ones’.

In the first group, the ones are present in the row for which the value of A is 0. Thus, they contain the
complement of variable A. Remaining two ‘ones’ are present in adjacent columns. In these columns,
only B term in common is the product term corresponding to the group as A’B. Just like group 1, in
group 2, the one’s are present in a row for which the value of A is 1. So, the corresponding variables of
this column are B’C’. The overall product term of this group is AB’C’.

         

Fig. 9: Grouping of 1’s in AB’C’

Step 5:

Lastly, we find the Boolean expression for the Output. To find the simplified Boolean expression in the
SOP form, we combine the product-terms of all individual groups. So, the simplified expression of the
above k-map is as follows:

A’+AB’C’

Let us take some examples of 2-variable, 3-variable, 4-variable, and 5-variable K-map examples.

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Example 1: Y=A’B’ + A’B+AB

Simplified expression: Y=A’+B

Example 2: Y=A’B’C’+A’ BC’+AB’ C’+AB’ C+ABC’+ABC

Simplified expression: Y=A+C’

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Example 3: Y=A’B’C’ D’+A’ B’ CD’+A’ BCD’+A’ BCD+AB’ C’ D’+ABCD’+ABCD

Simplified expression: Y=BD+B’D’

2) Maxterm Solution of K-Map

To find the simplified maxterm solution using K-map is the same as to find for the minterm solution.
There are some minor changes in the maxterm solution, which are as follows:

● We will populate the K-map by entering the value of 0 to each sum-term into the K-map cell
and fill the remaining cells with one’s.

● We will make the groups of ‘zeros’ not for ‘ones’.

● Now, we will define the Boolean expressions for each group as sum-terms.

● At last, to find the simplified Boolean expression in the POS form, we will combine the sum-
terms of all individual groups.

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1) Two Variable K-map:

Table 5: Sum of minterms representation               Table 6: Product of maxterms representation

2) Three Variable K-map:

Table 7: Sum of minterms representation           Table 8: Product of maxterms representation

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3) Four Variable K-map:

Table 9: Sum of minterms representation    Table 10: Product of maxterms representation

4) Five Variable K-map:

                                              Table 11: Five Variable K-Map

Let us take some examples of 2-variable, 3-variable, 4-variable and 5-variable K-maps.

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Example 1: Y=(A’+B’). (A+B’). (A+B)

Simplified expression: A.B’

Example 2: Y= (A + B + C’) + (A + B’ + C’) + (A’ + B’ + C) + (A’ + B’ + C’)

Simplified expression: Y= (A + C’). (A’ + B’)

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Example 3: F (A, B, C, D) =π (3,5,7,8,10,11,12,13)

Simplified expression: Y=(A+B+C’). (A+B’+D”). (A’+B’+C). (A’+C’+D)

Simplification Algorithm:
Simplification of logical functions using K-maps is based on the principle of combining terms in adja-
cent cells. Two cells are said to be adjacent if they differ in only one variable.

1. Identify the ones which cannot be combined with any other ones and encircle them. These
are called essential prime implicants.

2. Identify the ones that can be combined in groups of two in only one way. Encircle them.

3. Identify the ones that can be combined with three other ones, to make a group of four ad-
jacent ones, in only one way. Encircle such group of ones.

4. Identify the ones that can be combined with seven other ones, to make a group of eight
adjacent ones, in only one way. Encircle them.

5. After identifying the essential groups of 2, 4, and 8 ones, if there remain some ones which
have not been encircled, then these are to be combined with each other or with other al-
ready encircled ones.

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Optimisation of SOP and POS Boolean equations using K-MAPs

Problem-1

Simplify the Boolean function F=A′C+A′B+AB′C+BC

   Sol: F=A′C+A′B+AB′C+BC=A′B′C+A′BC′+A′BC+AB′C+AB′C

F=C+A′B
Problem-2

A,B,C,D=∑m (0, 1, 2, 3, 5, 7, 8, 9, 11, 14)

F=A′B′+A′D+ABCD′+B′C′+B′D

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Problem-3

FA,B,C,D=∑m (1, 2, 3, 5, 7, 8, 9, 10, 13)

Problem-4

FA,B,C,D=∏M (0, 1, 2, 3, 4, 10, 11)

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Problem-5

F= ∑m 1, 2,3, 5, 13+∑d (6, 7, 8, 9, 11, 15)

F=D+A’C

Problem-6

F= ∑m0, 2, 4, 9, 12, 15+∑ϕ (1, 5, 7, 10)

F=A′B′D′+BCD+BC′D′+B′C′D

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 Self-Assessment Questions

5) Do not care conditions can be used for simplifying Boolean expression in:

A) Logic diagram
B) Minterms
C) K-maps
D) Maxterms

6) Four adjacent ‘1’s in a Karnaugh map forms a/an:

A) octet
B) singlet
C) pair
D) quad

7) The Karnaugh map, each cell represents ___________ minterm derived from the Boolean
expression.

A) 1
B) 2
C) 3
D) 4

8) In a Karnaugh map, a group of eight 1’s adjacent to each other is called:

A) Pairs
B) Triad
C) Quads
D) Octet

9) In a Karnaugh map the formation of Quad results in the elimination of _________ variables
and their complements.

A) 2
B) 3
C) 4
D) 8

10) The binary number designations of the rows and columns of the K-map are in

A) binary code
B) BCD code
C) Gray code
D) XS-3 code.

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Summary
● A Karnaugh map (K-map) is a visual method used to simplify the algebraic expressions in
Boolean functions without having to resort to complex theorems or equation manipulations.

● K-Map is used for expressions containing 2,3,4 and 5 variables and for higher variables,
Quin-McClusky method is used.

● Solving K-Map is done by making groups, the K-Map grid is filled by 0’s and 1’s.

● Depending on the number of variables, the types of K- Map are two variable K-Map, three
variable K-Map, four variable K-Map, five variable K-Map.

● Minterm solutions and Maxterm solutions of K-Map are the simplification methods of
Boolean expression using K-Map.

● The principle of combining terms in adjacent cells is used as a method of logical functions
to simplify K-Maps.  

Terminal Questions
1. Using K-map, minimise the following function F (A, B, C) = ∏ M (0,1,3,6)

2. Simplify F (A, B, C, D) = ∑m (1,3,4,6,8,9,12,15) using K-Map

3. Using K-map, minimise the following function: F (A, B, C, D) = ∏ M (0,2,4,5,8,9,14,15)

4. Solve F (X, Y, Z) = X′Y + YZ′ + YZ + XY′Z′ using K map

5. Solve using K map F (A, B, C) = A’C + AB’C + BC + AB’ + A’BC’

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 Answer Keys

Self-Assessment Questions
Question No. Answer
1   D
2   C
3   A
4   B
5   C
6 D
7 A
8 D
9 A
10 C

Activity

Activity type: Offline/online Duration: 60 min

Using K-MAP method Construct an Optimised logic circuit for a given SOP and POS:

F (A, B,C) = ∑m (1,3,4,6)

F (A, B,C) = ∏ M (0,2,4,5)

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Glossary
● Karnaugh Mapping: Two-dimensional form of a truth table used to simplify a sum of
products expression.

● SOP: Sum of Products, one of the forms of Boolean expression consisting purely of
Minterms (product terms).

● POS: Product of Sums, one of the forms of Boolean expression consisting purely of
Maxterms (sum terms).

Bibliography

● Mano, M. (1992). Computer System Architecture. PHI.

● Stallings, W. (2015). Computer System Architecture. PHI.
● Brown, S., & Vranesic, Z. (2008). Fundamentals of Digital Logic with Verilog Design
(2nd ed.). McGraw-Hill.
● Mano, M. (2017). Digital Logic and Computer Design. Pearson.
● Jain, R. P. (2009). Modern Digital Electronics (4th ed.). Tata McGraw Hill.

e-References

● https://www.usna.edu/Users/cs/lmcdowel/courses/ic220/S21/resources/kmaps.html

● https://www.allaboutcircuits.com/technical-articles/karnaugh-map-boolean-algebraic-
simplification-technique/

Video Links

● https://youtu.be/y-aYzGdlM-8
● https://youtu.be/wjM2RDG5yTI
● https://youtu.be/JRR8RCKMKjA

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 Image Credits

Fig.1: Grouping of 1’s in K-map

● https://www.javatpoint.com/simplification-of-boolean-expressions-using-karnaugh-map

Fig.2: Right representation of grouping of 1’s  

● https://www.javatpoint.com/simplification-of-boolean-expressions-using-karnaugh-map

Fig.3: Grouping of three 1’s of K - Map

● https://www.javatpoint.com/simplification-of-boolean-expressions-using-karnaugh-map

Fig.4: Grouping of 1’s in decreasing order

● https://www.javatpoint.com/simplification-of-boolean-expressions-using-karnaugh-map

Fig.5: Grouping of 1’s in horizontal or vertical manner.

● https://www.javatpoint.com/simplification-of-boolean-expressions-using-karnaugh-map

Fig.6: Grouping of 1’s in different group

● https://www.javatpoint.com/simplification-of-boolean-expressions-using-karnaugh-map

Fig.7: Grouping of 1’s at the adjacent of table

● https://www.javatpoint.com/simplification-of-boolean-expressions-using-karnaugh-map

Fig.8: Grouping of 1’s in the” do not care condition”

● https://www.javatpoint.com/simplification-of-boolean-expressions-using-karnaugh-map

Fig.9: Grouping of 1’s in AB’C’

● https://www.javatpoint.com/simplification-of-boolean-expressions-using-karnaugh-map

Keywords

● K-Maps

● Boolean Equations
● Maxterms
● Minterms
● Combinational logic

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 Computer Organisation and Architecture

Module - 3
Unit - 2

Minimisation Techniques

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 Table of Contents
Unit 3.2 Minimisation Techniques

Aim --------------------------------------------------------------------------------------------------- 163

Instructional Objectives  ------------------------------------------------------------------------ 163
Learning Outcomes  ----------------------------------------------------------------------------- 163

3.2.1 POS and SOP form representation of a Boolean Function -------------------- 164
         Self-Assessment Questions ----------------------------------------------------------- 168
3.2.2 Min and Max Terms Notation in Boolean algebra -------------------------------- 169
Self-Assessment Questions ----------------------------------------------------------- 176

Summary -------------------------------------------------------------------------------------------    117

Terminal Questions ------------------------------------------------------------------------------   117
Answer Keys -------------------------------------------------------------------------------------- 117
Activity ---------------------------------------------------------------------------------------------- 178
Glossary --------------------------------------------------------------------------------------------    178
Bibliography ---------------------------------------------------------------------------------------    178
e-References -------------------------------------------------------------------------------------- 179
Video Links  --------------------------------------------------------------------------------------- 179
Keywords  ------------------------------------------------------------------------------------------ 179

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Aim
To introduce students to the basic concepts of POS/SOP and Minterm/Maxterm-based
Combinational Logic circuits for computer architecture modules.  

Instructional Objectives
This unit intends to:

● Demonstrate SOP and POS form representation of a Boolean function

● Describe the design minterm/maxterm of combinational logic circuits
● Explain the SOP/POS conversion forms

Learning Outcomes
Upon completion of this unit, you will be able to:

● Elaborate on SOP and POS representation of a Boolean Function

● Illustrate various logic circuits design for minterm/maxterm based Boolean equations
● Summarise the SOP/POS conversion forms

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3.2.1 POS and SOP form representation of a Boolean Function
There are four ways in which a Boolean function can be expressed:

1. Product of Sum (POS) Form

2. Sum of Product (SOP) Form

3. Canonical Form of POS/SOP Form

4. Standard Form

A) Product of Sum (POS) Form

As the name suggests, A POS expression contains the sum of various terms ANDed/multiplied
together.

Example: Y = (A + B). (C + D). (E + F)

B) Sum of Product (SOP) Form

As the name suggests, A SOP expression is a group of product terms ORed/added together.

Example: Y = (A. B) + (C. D) + (E. F)

C) Canonical Form of POS/SOP Form

If each term of SOP/POS expression contains all the literals in the Boolean function, then they
are said to be in canonical form. Suppose we have a Boolean function (Y) having three literals A, B
and C, then canonical Boolean expressions can be written as,

Y = ABC + A. B. C + A.B.C

This is an example of canonical SOP Form, because each term in the SOP form contains all the lit-
erals A, B, and C.

Similarly, Y = (A+B+C). (A + B + C). (A+B+C)

This is an example of canonical POS form, because each term of the POS form contains all the lit-
erals.

Now, let us see a few problems on canonical form.

Example 1: Convert the following expressions in their canonical form.

1. Y (A, B, C) = AB + BC + CA

2. Y (X, Y, Z) = X. (X + Y). (X + Y + Z)

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Solution (i):

Y (A, B, C) = AB + BC + CA, this expression is a SOP expression, since we notice the Boolean
function has three literals A, B and C, so each term of the Boolean expression must contain all the
three literals to convert it into canonical SOP form. Therefore,

= Y (A, B, C) = AB + BC + CA

= AB. (C + C) + BC. (A + A) + CA. (B + B) [Since, C + C = 1]

= ABC + AB. C + ABC + A. BC + ABC + A. B. C

= ABC + AB. C + A. BC + A. B. C

Hence,

Y = ABC + AB. C + A. BC + A. B.C

is the required canonical SOP form representation.

Solution (ii):

Y (X, Y, Z) = X. (X + Y). (X + Y + Z), is an example of POS expression, since all the sum terms in
the expression does not have all the literals X, Y, and Z, so we must express it in such a way that it
will have all the three literals in each term.

= Y (X, Y, Z) = X. (X + Y). (X + Y + Z)

= (X + Y. Y + Z. Z) (X + Y + Z. Z). (X + Y + Z)

= (X + Y. Y + Z) (X + Y. Y + Z) (X + Y + Z) (X + Y + Z) (X + Y + Z)

= (X + Y +Z) (X + Y + Z) (X + Y + Z) (X + Y + Z) (X + Y + Z) (X + Y + Z)

= (X + Y +Z) (X + Y + Z) (X + Y + Z) (X + Y + Z)

Hence,

Y = (X + Y +Z) (X + Y + Z) (X + Y + Z) (X + Y + Z)

is the required canonical POS form representation.

Canonical form of SOP and POS

In digital logic, the inputs and output of a function are in the form of binary numbers (Boolean val-
ues) i.e., the values are either zero (0) or one (1). Therefore, digital logic is also known as ‘Boolean
logic.’ These inputs and output can be termed as ‘Boolean Variables.’ The output Boolean variable
of a digital signal can be expressed in terms of input Boolean variables which forms the ‘Boolean
Expression.’  

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Representation of Boolean expression can be primarily done in two ways. They are as follows:

● Sum of Products (SOP) form  

● Product of Sums (POS) form  
  
Note:  
If the number of input variables are n, then the total number of combinations in Boolean algebra is
2n.  

If the input variable (let A) value is:

● Zero (0) – a is LOW -It should be represented as A’ (Complement of A)  

● One (1) – a is HIGH -It should be represented as A  

● Minterm: A minterm is a standard product which consists of all variables in either

complemented or un-complemented form for which the output is 1.

● Maxterm: A maxterm is a standard sum which consists of all variables in either

complemented or un-complemented form for which the output is 0.

Sum of Products (SOP):

It is one of the ways of writing a Boolean expression. As the name suggests, it is formed by adding
(OR operation) the product terms. These product terms are also called as ‘minterms’. Minterms are
represented with ‘m’, they are the product (AND operation) of Boolean variables either in normal form
or complemented form.

Therefore, SOP is the sum of minterms and is represented as:  

F in SOP = ∑m (0, 3)  

Here, F is sum of minterm0 and minterm3.  

For Example:  

A=0, B=0, C=0   Minterm is A’. B’.C’

A=1, B=0, C=1   Minterm is A.B’.C   

X (SOP) = ∑m (1, 3, 6)
X = A’. B.’C + A.’B.C + A.B.C’

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Product of Sums (POS):
As the name suggests, it is formed by multiplying (AND operation) the sum terms. These sum terms
are also called as ‘maxterms’. Maxterms are represented with ‘M’, they are the sum (OR operation) of
Boolean variables either in normal form or complemented form.  

Therefore, POS is a product of maxterms and is represented as:

F in POS = ∏M (1, 2) Here,  

F is product of maxterm1 and maxterm2.  

For Example:   

A=0, B=1, C=0   Maxterm is A+B’+C

A=1, B=1, C=1   Maxterm is A’+B’+C’

X (POS) = ∏M (0, 2, 4, 5, 7)   

       X = (A+B+C). (A+B›+C). (A›+B+C). (A›+B+C›). (A›+B›+C›)  

  

Difference between SOP and POS:

Table 1: Comparison of SOP and POS

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 Self-Assessment Questions
1) Which of the following is an example of standard POS expression is?

A) A(B+C) +CĀ
B) (A+B) (Ā+B+C)
C) Ā+B+BC
D) Both (a) and (b)

2) An example of a SOP expression is:

A) A+B(C+D)
B) A’B+AC’+AB’C
C) (A’+B+C) (A+B’+C)
D) Both (a) and (b)

3) Product-of-Sums expressions can be implemented using ___________.

A) 2-level OR-AND logic circuits

B) 2-level NOR logic circuits
C) 2-level XOR logic circuits
D) Both 2-level OR-AND and NOR logic circuits

4) Using the transformation method you can realise any POS realisation of OR-AND with only:

A) XOR
B) NAND
C) AND
D) NOR

5) The NAND-NAND realisation is equivalent to:

A) AND-NOT realisation
B) AND-OR realisation
C) OR-AND realisation
D) NOT-OR realisation

6) OR-AND realisation of a combinational circuit is equivalent to:

A) NAND-NOR realisation
B) NAND-NAND realisation   
C) NOR-NAND realisation
D) NOR-NOR realisation

7) The AND-OR realisation of a combinational circuit requires three 3-input AND gates and
one 3-input OR gate. This circuit can be designed using:

A) Four input NAND gates only

B) Three 3-input OR gates and one 3-input AND gate
C) Three 3-input NAND gates and one 3-input NOR gate
D) None of the above

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3.2.2 Min and Max Terms Notation in Boolean algebra
In short or for convenience purposes, we represent canonical SOP/POS form in min/max terms.

Minterm
Each of the product terms in the canonical SOP form is called a minterm. Minterm are represented
as binary numbers in terms of 0s and 1s. The binary words are formed by representing each non-
complemented variable by 1 and each complemented variable by 0, and the decimal equivalent of
this binary word is represented as a subscript of m as m0, m1, m2, etc. We use the ∑ (sigma) notation
to represent minterms.

Maxterm
Each of the sum terms in the canonical POS form is called a maxterm. Maxterm can also be
represented using binary numbers where each non-complemented variable is represented using 0 and
complemented variable using 1, and the decimal equivalent of this binary word is represented as a
subscript of M as M0, M2, M2, etc. We use ∏ (pi) notation to represent the max terms.

Note: For n-variable logic function there are 2n minterms and 2n maxterms.  

Table 2: Min and Max terms for two literal binary expressions  

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 Table 3: Min and Max terms for three literal binary expressions  

  

Example: Express the following in corresponding minterm and maxterm expression

1. Y = ABC + A.B.C + A.B. C + A. B. C  

2. Y= (A+B+C) (A+ B+C) (A+ B+ C)  

Solution (a):  

Y = ABC + A. B.C + A.B. C + A. B. C, is an example of canonical SOP expression, so its each term can
be represented in minterm notation. Therefore,  

    Y = ABC + A. B.C + A.B. C + A. B. C  

    = m7 + m3 + m5 + m4  

    = ∑m (3, 4, 5, 7) [ ∑ is used to denote CSOP]  

  

Solution (b):  

Y= (A+B+C) (A+ B+ C) (A+ B+ C), is an example of canonical POS expression, so its each term can
be represented in maxterm notation.  

    Y= (A+B+C) (A+ B+ C) (A+ B+ C)  

    = M0 + M5 + M7  

    = ∏M (0, 5, 7) [ ∏ is used to denote CPOS]  

  

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Note: If a truth table is given, and if the output is 1 then it corresponds to minterm and in case the
output is 0 then it corresponds to 0.  

Canonical Form – In Boolean algebra, Boolean function can be expressed as Canonical Disjunctive
Normal Form known as minterm and some are expressed as Canonical Conjunctive Normal Form
known as maxterm.

In Minterm, we look for the functions where the output results in “1” while in Maxterm we look for
function where the output results in “0”.

We perform Sum of minterm also known as Sum of products (SOP).  

We perform Product of Maxterm also known as Product of sum (POS).  

Boolean functions expressed as a sum of minterms or product of maxterms are said to be in canonical
form.

Standard Form – A Boolean variable can be expressed in either true form or complemented form. In
standard form Boolean function will contain all the variables in either true form or complemented form
while in canonical number of variables depends on the output of SOP or POS.

A Boolean function can be expressed algebraically from a given truth table by forming a:

● minterm for each combination of the variables that produces a 1 in the function and then
taking the OR of all those terms.

● maxterm for each combination of the variables that produces a 0 in the function and then
taking the AND of all those terms.

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Truth table representing minterm and maxterm –

Table 4: Three Variable Minterms and Maxterms

From the above table it is clear that minterm is expressed in product format and maxterm is expressed
in sum format.  

Sum of minterms   
The minterms whose sum defines the Boolean function are those which give the 1’s of the function
in a truth table. Since the function can be either 1 or 0 for each minterm, and since there are 2^n
minterms, one can calculate all the functions that can be formed with n variables to be (2^(2^n)). It is
sometimes convenient to express a Boolean function in its sum of minterm form.  
  

Example – Express the Boolean function F = A + B’C as standard sum of minterms.

Solution –  
A = A(B + B’) = AB + AB’  
This function is still missing one variable, so  
A = AB(C + C’) + AB’(C + C’) = ABC + ABC’+ AB’C + AB’C’  
The second term B’C is missing one variable; hence,  
B’C = B’C(A + A’) = AB’C + A’B’C  
Combining all terms, we have  
F = A + B’C = ABC + ABC’ + AB’C + AB’C’ + AB’C + A’B’C  
But AB’C appears twice, and  
according to theorem (x + x = x), it is possible to remove one of those occurrences. Rearranging the
minterms in ascending order, we finally obtain  
F = A’B’C + AB’C’ + AB’C + ABC’ + ABC  
= m1 + m4 + m5 + m6 + m7  
SOP is represented as ∑m (1, 4, 5, 6, 7)

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Example – Express the Boolean function F = xy + x’z as a product of maxterms

Solution –  
F = xy + x’z = (xy + x’)(xy + z) = (x + x’)(y + x’)(x + z)(y + z) = (x’ + y)(x + z)(y + z)  
x’ + y = x’ + y + zz’ = (x’+ y + z)(x’ + y + z’)
x + z = x + z + yy’ = (x + y + z)(x + y’ + z)
y + z = y + z + xx’ = (x + y + z)(x’ + y + z)  
F = (x + y + z)(x + y’ + z)(x’ + y + z)(x’ + y + z’)  
= M0*M2*M4*M5  
POS is represented as ∏M (0, 2, 4, 5)

Example –  

F(A, B, C) = ∑m(1, 4, 5, 6, 7)  

F’(A, B, C) = ∑m (0, 2, 3) = m0 + m2 + m3  
Now, if we take the complement of F’ by DeMorgan’s theorem, we obtain F in a different form:  
F = (m0 + m2 + m3)’  
= m0’m2’m3′  
= M0*M2*M3  
= ∏M(0, 2, 3)  

Conversion of SOP from standard to canonical form

Example -1. Express the Boolean function F = A + B’C as a sum of minterms.  

Solution: The function has three variables: A, B, and C. The first term A is missing two variables;
therefore,  

A = A (B + B’) = AB + AB’  

This function is still missing one variable, so  

A = AB (C + C’) + AB’ (C + C’)  

   = ABC + ABC’ + AB’C + AB’C’  

The second term B’C is missing one variable; hence,  

B’C = B’C (A + A’) = AB’C + A’B’C  

Combining all terms, we have  

F = A + B’C = ABC + ABC’ + AB’C + AB’C’+ A’B’C  

But AB’C appears twice, and according to theorem (x + x = x), it is possible to remove one of those
occurrences. Rearranging the minterms in ascending order, we finally obtain  

F = A’B’C + AB’C + AB’C + ABC’ + ABC  

   = m1 + m4 + m5 + m6 + m7  

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When a Boolean function is in its sum-of-minterms form, it is sometimes convenient to express the
function in the following brief notation:  

F (A, B, C) = ∑m (1, 4, 5, 6, 7)  

Example - 2. Express the Boolean function F = xy + x’z as a product of maxterms.  

Solution: First, convert the function into OR terms by using the distributive law:  

F = xy + x’z = (xy + x’) (xy + z)  

= (x + x’) (y + x’) (x + z) (y + z) = (x’+ y) (x + z) (y + z)  

The function has three variables: x, y, and z. Each OR term is missing one variable; therefore,  

x’+ y = x’ + y + zz’  

= (x’ + y + z) (x’ + y + z’) x + z  

= x + z + yy’ = (x + y + z) (x + y’ + z) y + z  

= y + z + xx’ = (x + y + z) (x’ + y + z)  

Combining all the terms and removing those which appear more than once, we finally obtain  

F = (x + y + z) (x + y’ + z) (x’ + y + z) (x’ + y + z)  

F= M0.M2.M4.M5 A  

Convenient way to express this function is as follows:  

F (x, y, z) = πM (0, 2, 4, 5)  

The product symbol, π, denotes the ANDing of maxterms; the numbers are the indices of the maxterms
of the function.

Conversion from Canonical SOP to Canonical POS

Standard SOP expression can be converted into standard POS (product of sum) expression. For ex-
ample, the function given above is in canonical SOP form.

Convert SOP to POS: F = xy’ + yz’

F = xy’ + yz’  

= xy’(z + z’) + (x + x’)yz’

= xy’z + xy’z’ + xyz’ + x’yz’

= Σm (2, 4, 5, 6)  

= πM (0, 1, 3, 7)

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Conversion from Canonical POS to SOP
The product of Sum expression can be converted into Sum of Product form only if the expression is
in canonical form. Canonical POS and canonical SOP are inter-convertible i.e., they can be converted
into one another. Example of POS to SOP conversion is given below.

POS canonical form:

                F = (A+B+C) (A̅+B+C) (A̅+B̅+C) (A̅+B̅+C̅)

In canonical form each sum term is a max term so it can also be written as:

                F = ∏M (0,4,6,7)

The remaining combinations of inputs are minterms of the function for which its output is true. To
convert it into SOP expression first we will change the symbol to summation (∑) and use the remaining
minterm.

                F = ∑m (1,2,3,5)

Now we will expand the summation sign to form canonical SOP expression.

                F = A̅B̅C + A̅BC̅ + A̅BC + AB̅C

Minterms are complements of Maxterms for the same combination of inputs.

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 Self-Assessment Questions

8) Each product term of a group, w’.x.y’ and w.y, represents the _________ in that group.

A) Input
B) POS
C) Sum-of-Minterms
D) Sum of Maxterms

9) Each term in the standard SOP form is called a:

A) Minterm
B) Maxterm
C) Don’t care.
D) Literal

10) Each term in the standard POS form is called a:

A) Minterm
B) Maxterm
C) Don’t care.
D) Literal

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Summary
● The four ways Product of Sum (POS) Form, Sum of Product (SOP) Form, Canonical
Form of POS/SOP Form, Standard Form are used to express a Boolean Function.
● SOP stands for Sum of Products. It is a technique of defining the Boolean terms as the
sum of product terms.
● POS stands for Product of Sums. It is a technique of defining Boolean terms as a prod-
uct of sum terms.
● The canonical SOP/POS form is represented in min/max terms.
● Minterm is the product term in the canonical SOP form and are represented as binary
numbers in terms of 0s and 1s.
● Maxterm is the sum term in the canonical POS form and are represented as binary num-
bers in terms of 0s and 1s.
● Boolean function in standard form will contain all the variables in either true form or
complemented form.

Terminal Questions

1. Convert the SOP function F = ∑m A, B, C (2, 3, 5) = A B’ C’ + A B’ C + ABC’ into POS

2. Convert the function F = (A’ + B + C) * (B’ + C + D’) * (A + B’ + C’ + D) into SOP
3. Find Minterm Boolean equation and construct logic circuit for given: F=∑m (1,3,4,6,7)
4. Find Maxterm Boolean equation and construct logic circuit for given: F=∏M (1,3,4,6,7)

Answer Keys

Self-Assessment Questions
Question No. Answer
1   B
2   B
3   D
4   D
5   D
6 B
7 D
8 C
9 A
10 B

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 Activity
Activity Type: Offline Duration: 30-45 min

1) Convert SOP to POS and POS to SOP:  

F=AB+CD

H=(A+B). (C+D)

Glossary

● Maxterm: a logical sum of all variables with or without the complement

● Minterm: a logical product of all variables with or without the complement

● Included minterm: one of the terms in a canonical SOP is the Included maxterm

● Excluded minterm: A minterm not in a particular canonical SOP is the Excluded maxterm

● Canonical SOP: a sum of products, the terms of which are all minterms, that is, each term
contains all input variables with or without the complement operator.

● Canonical POS: a product of sums, the factors of which are all maxterms, that is, each
term includes all input variables OR’d together with or without the complement operator
on each variable.

Bibliography
● Mano, M. (1992). Computer System Architecture. PHI.
● Stallings, W. (2015). Computer System Architecture. PHI.
● Brown, S., & Vranesic, Z. (2008). Fundamentals of Digital Logic with Verilog Design (2nd
ed.). McGraw-Hill.
● Mano, M. (2017). Digital Logic and Computer Design. Pearson.
● Jain, R. P. (2009). Modern Digital Electronics (4th ed.). Tata McGraw Hill.

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e-References
● https://www.electronics-tutorials.ws/boolean/sum-of-product.html
● https://www.electronics-tutorials.ws/boolean/product-of-sum.html
● https://www.electroniclinic.com/sop-and-pos-digital-logic-designing-with-solved-
examples/

Video links
● https://youtu.be/K2cpJex0o_A
● https://youtu.be/YmKmS9bpMqM

Keywords
● SOP
● POS
● Boolean variable
● Sum of minterm
● Product of maxterm
● NAND realisation

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 Computer Organisation and Architecture

Module - 4
Unit - 1

Combinational Circuits
&
Sequential Circuits

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Module Description
Digital circuits or digital electronics is a branch of electronics which deals with digital signals to perform
various tasks to meet various requirements. Digital circuit systems are designed to overcome the
disadvantage of analog systems which are slower and the output data which is obtained may contain
an error.

A digital circuit is designed using several logic gates on a single integrated circuit – IC. The input to
any digital circuit is in the binary form “0’s” and “1’s”. The output obtained from processing raw digital
data is of precise value. These circuits can be represented in 2 ways either in a combinational way or
a sequential way.

Combinational and Sequential circuits are the most used type of digital circuits in digital electronics.
The sequential circuits and combinational circuits are being used in the displays such as boarding
flights, bus stations, in weight machines, in weather forecast instruments, etc.

With real life application like a traffic light controller, a vending machine (the money acceptance and
change return), a password checker (in an electronic door lock) etc., the growing importance and
usage of these type of digital circuits acquires prominence without any doubt.

The development of the digital electronics on large scale promotes the Research and Development
work in other areas like Health, Education, Space etc.; that paves way for new inventions in the
respective fields that would serve the global needs. Therefore, it is vital to learn each, and every
development related to the digital circuits with more focus on the combinational and sequential circuits
to make oneself more knowledgeable in the relevant domain.

Hence, this module attempts to introduce the basic concepts of digital circuits with emphasis on the
combinational and sequential circuits.

Unit 4.1 - Combinational Circuits - Adders

Unit 4.2 - Combinational Circuits - Subtractors

Unit 4.3 - Combinational Circuits - Multiplexers and De-multiplexers

Unit 4.4 - Sequential Circuits

Unit 4.5 - Conversion of Flip-Flops

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 Table of Contents
Unit 4.1 Combinational Circuits - Adders

Aim ---------------------------------------------------------------------------------------------- 183

Instructional Objectives -------------------------------------------------------------------- 183
Learning Outcomes ------------------------------------------------------------------------- 183
4.1 Combinational Circuits - Adders ---------------------------------------------------- 184
4.1.1 Half Adder, Full Adder --------------------------------------------------------- 185
       Self-Assessment Questions -------------------------------------------------------- 191
Summary --------------------------------------------------------------------------------------    195
Terminal Questions -------------------------------------------------------------------------   195
Answer Keys --------------------------------------------------------------------------------- 196
Activity -----------------------------------------------------------------------------------------    196
Glossary  -------------------------------------------------------------------------------------- 197
Bibliography ----------------------------------------------------------------------------------    197
e-References  -------------------------------------------------------------------------------- 197
Video Links  ---------------------------------------------------------------------------------- 198
Image Credits --------------------------------------------------------------------------------   198
Keywords  ------------------------------------------------------------------------------------ 198

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Aim
To introduce students the basic concepts of Logic gates based Combinational Logic circuits,
Adder, for computer architecture modules.  

Instructional Objectives
This unit intends to:

● Explain the architectural and logic design of combinational logic circuit - Adder.
● Describe their relevance and applications in new age.

Learning Outcomes
Upon completion of this unit, you will be able to:
● Illustrate architectural and logic design of combinational logic circuit - Adder.
● Summarise their relevance and applications in new age.

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4.1 Combinational Circuits - Adders
Combinational Logic Circuits are memoryless digital logic circuits whose output at any instant in time
depends only on the combination of its inputs. The outputs of Combinational Logic Circuits are only
determined by the logical function of their current input state, logic “0” or logic “1”, at any given instant
in time. Fig.1 is showing the block diagram of combinational Logic Circuit.  

The result is that combinational logic circuits have no feedback, and any changes to the signals being
applied to their inputs will immediately have an effect at the output. In other words, in a Combinational
Logic Circuit, the output is always dependant on the combination of its inputs. Thus, a combinational
circuit is memoryless.

So, if one of its inputs condition changes states, from 0-1 or 1-0, so too will the resulting output as by
default combinational logic circuits have “no memory”, “timing” or “feedback loops” within their design.

Fig. 1 Block Diagram of Combinational Logic Circuit

Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT gates that are “com-
bined” or connected to produce more complicated switching circuits. These logic gates are the build-
ing blocks of combinational logic circuits. An example of a combinational circuit is a decoder, which
converts the binary code data present at its input into several different output lines, one at a time
producing an equivalent decimal code at its output.

Combinational logic circuits can be quite simple or complicated and any combinational circuit can be
implemented with only NAND and NOR gates as these are classed as “universal” gates.

The three main ways of specifying the function of a combinational logic circuit are:

1) Boolean Algebra – This forms the algebraic expression showing the operation of the logic circuit
for each input variable either True or False those results in a logic “1” output.

Example:  

Y=A+B

2) Truth Table – A truth table defines the function of a logic gate by providing a concise list that shows
all the output states in tabular form for each possible combination of input variable that the gate could
encounter.

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Example:  

Table 1: Truth Table of OR Gate

3) Logic Diagram – This is a graphical representation of a logic circuit that shows the wiring and
connections of each individual logic gate, represented by a specific graphical symbol, that implements
the logic circuit.

Example:

Fig. 2: Logic diagram of OR Gate

As combinational logic circuits are made up from individual logic gates only, they can also be consid-
ered as “decision making circuits” and combinational logic is about combining logic gates together to
process two or more signals to produce at least one output signal according to the logical function of
each logic gate. Common combinational circuits made up from individual logic gates that carry out a
desired application include Half and Full Adders, Subtractors, Multiplexers, De-multiplexers, Encod-
ers, and Decoders etc.

4.1.1 Half Adder, Full Adder

Introduction:

A half adder is a digital logic circuit that performs binary addition of two single-bit binary numbers. It
has two inputs, A and B, and two outputs, SUM and CARRY. The SUM output is the least significant
bit (LSB) of the result, while the CARRY output is the most significant bit (MSB) of the result, indicating
whether there was a carry-over from the addition of the two inputs. The half adder can be implemented
using basic gates such as XOR and AND gates.

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The half adder is a basic building block for more complex adder circuits such as full adders and
multiple-bit adders. It performs binary addition of two single-bit inputs, A and B, and provides two
outputs, SUM, and CARRY.  

Half Adder Logic Design:

Half adder is the simplest of all adder circuits. Half adder is a combinational arithmetic circuit that adds
two numbers and produces a sum bit (s) and carry bit (c) both as output. The addition of 2 bits is done
using a combination circuit called a Half adder. The input variables are augend and addend bits, and
output variables are sum & carry bits. A and B are the two input bits.

Let us consider two input bits A and B, then sum bit (s) is the X-OR of A and B. it is evident from the
function of a half adder that it requires one X-OR gate and one AND gate for its construction.  

Truth Table:

Table 2: Truth Table of half adder

Here we perform two operations Sum and Carry, thus we need two K-maps one for each to derive the
expression.

Logical Expression:

Fig. 3: Logical expression of Half Adder

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The characteristic equations of half adder, i.e., equations of sum (S) and carry (C) are obtained
according to the rules of binary addition. These equations are given below −

The sum (S) of the half-adder is the XOR of A and B. Thus,

For Sum, S = A⊕B = AB’+A’B

For Carry, C = A●B = AB

Implementation:

Fig. 4: Block diagram and Circuit diagram of half adder

Note: Half adder has only two inputs and there is no provision to add a carry coming from the lower
order bits when multi addition is performed.

Applications of Half Adder

The following are some important applications of half adder:

● Half adder is used in ALU (Arithmetic Logic Unit) of computer processors to add binary bits.

● Half adder is used to realise full adder circuit.

● Half adder is used in calculators.

● Half adder is used to calculate addresses and tables.

Full Adder:

Introduction
Addition is one of the most basic operations performed by different electronic devices like computers,
calculators, etc. The electronic circuit that performs the addition of two or more numbers, more
specifically binary numbers, is called as adder. As we know, the logic circuits use binary number sys-
tem to perform the operations, hence the adder is referred to as binary adder.

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A combinational logic circuit that can add two binary digits (bits) and a carry bit, and produces a sum
bit and a carry bit as output is known as a full-adder.

In other words, a combinational circuit which is designed to add three binary digits and produces two
outputs (sum and carry) is known as a full adder. Thus, a full adder circuit adds three binary digits,
where two are the inputs and one is the carry forwarded from the previous addition.

Full Adder Logic Design: Full adder takes three inputs namely A, B, and Cin. Where, A and B are the
two binary digits, and Cin is the carry bit from the previous stage of binary addition. The sum output of
the full adder is obtained by XORing the bits A, B, and Cin. While the carry output bit (Cout) is obtained
using AND and OR operations.

Truth Table: Truth table is one that indicates the relationship between input and output variables of
a logic circuit and explains the operation of the logic circuit. The following is the truth table of the full-
adder circuit:

Table 3: Truth Table of full adder

Hence, from the truth table, the sum output of the full adder is equal to 1 when only 1 input is equal
to 1 or when all the inputs are equal to 1. While the carry output has a carry of 1 if two or three inputs
are equal to 1.

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Logical Expression:

The characteristic equations of the full adder, i.e., equations of sum (S) and carry output (Cout) are
obtained according to the rules of binary addition. These equations are given below:

The sum (S) of the full-adder is the XOR of A, B, and Cin. Therefore,

Sum, S = A⊕B⊕Cin=A’B’Cin+A’BC’in+ABCin

The carry (C) of the half-adder is the AND of A and B. Therefore,

Carry, C=AB+ACin+BCin

Implementation:

Fig. 5: Block diagram and Circuit diagram of full adder

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Advantages of Full Adder
The following are the important advantages of full adder over half adder:

● Full adder provides facility to add the carry from the previous stage.

● The power consumed by the full adder is less as compared to half adder.

● Full adder can be easily converted into a half subtractor just by adding a NOT gate in the
circuit.

● Full adder produces higher output that half adder.

● Full adder is one of the essential parts of critic digital circuits like multiplexers.

● Full adder performs operation at higher speed.

Applications of Full Adder

The following are the important applications of full adder:

● Full adders are used in ALUs (arithmetic logic units) of CPUs of computers.

● Full adders are used in calculators.

● Full adders also help in carrying out multiplication of binary numbers.

● Full adders are also used to realize critic digital circuits like multiplexers.

● Full adders are used to generate memory addresses.

● Full adders are also used in generation of program counterpoints.

● Full adders are also used in GPU (Graphical Processing Unit).

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Self-Assessment Questions

1) In parts of the processor, adders are used to calculate ____________.

A) Addresses
B) Table indices
C) Increment and decrement operators
D) All of the Mentioned

2) In which operation carry is obtained.

A) Subtraction
B) Addition
C) Multiplication
D) Both addition and subtraction

3) Half-adders have a major limitation in that they cannot __________.

A) Accept a carry bit from a present stage

B) Accept a carry bit from a next stage
C) Accept a carry bit from a previous stage
D) Accept a carry bit from the following stages

4) How does an arithmetic operation take place in binary adders.

A) By addition of two bits corresponding to 2n digit

B) By addition of resultant to carry from 2n-1 digit
C) Both a & b
D) None of the above

5)Two-bit addition is done by

A) Ripple carry adder

B) Carry sum adder
C) Full adder
D) Half adder

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 6) The most significant bit of arithmetic addition is called

A) Overflow
B) Output
C) Zero bit
D) Carry

7) If A and B are the inputs of a half adder, the sum is given by __________.

A) A AND B
B) A OR B
C) A XOR B
D) A EX-NOR B

8) If A and B are the inputs of a half adder, the carry is given by __________.

A) A AND B
B) A OR B
C) A XOR B
D) A EX-NOR B

9) Half adder circuits require two binaries.

A) Inputs
B) Outputs
C) Both a and b
D) Digits

10) Which of the following is known as half adder?

A) XOR gate
B) XNOR gate
C) NAND gate
D) NOT gate

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11) The difference between half adder and full adder is __________.

A) Half adder has two inputs while full adder has four inputs
B) Half adder has one output while full adder has two outputs
C) Half adder has two inputs while full adder has three inputs
D) All of the Mentioned

12) If A, B and C are the inputs of a full adder then the sum is given by __________.

A) A AND B AND C
B) A OR B AND C
C) A XOR B XOR C
D) A OR B OR C

13) If A, B and C are the inputs of a full adder then the carry is given by __________.

A) A AND B OR (A OR B) AND C
B) A OR B OR (A AND B) C
C) (A AND B) OR (A AND B) C
D) A XOR B XOR (A XOR B) AND C

14) How many AND, OR and EXOR gates are required for the configuration of full adder.

A) 1, 2, 2
B) 2, 1, 2
C) 3, 1, 2
D) 4, 0, 1

15) A full-adder can be made of ____________.

A) Two half-adders
B) Two half-adders and a NOT gate
C) Two half-adders and an OR gate
D) Two half-adders and an AND gate

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 16) Why XOR gate is called an inverter?

A) Because of the same input

B) Because of the same output
C) It behaves like a NOT gate
D) It behaves like a AND gate

17) A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is
____________.

A) Ex-NOR gate
B) OR gate
C) Ex-OR gate
D) NAND gate

18) What are the two types of basic adder circuits?

A) Sum and carry

B) Half-adder and full adder
C) Asynchronous and synchronous
D) One and two’s-complement

19) Which of the following is correct for full adders?

A) Full adders have the capability of directly adding decimal numbers

B) Full adders are used to make half adders
C) Full adders are limited to two inputs since there are only two binary digits
D) In a parallel full adder, the first stage may be a half adder

20) What is the major difference between half-adders and full adders?

A) Full adders are made up of two half-adders

B) Full adders can handle double-digit numbers
C) Full adders have a carry input capability
D) Half adders can handle only single-digit numbers

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Summary
● Combinational circuit is a memoryless circuit whose output is always dependent on the
combinations of inputs given.

● Logic gates NAND, NOR or NOT gates are combined to form combinational logic circuits.

● Boolean Algebra, Truth Table and Logic Diagram are used to specify combinational logic
circuit.

● A half adder is a type of adder, an electronic circuit that performs the addition of numbers.  

● The half adder can add two single binary digits and provide the output plus a carry value.
It has two inputs, called A and B, and two outputs S (sum) and C (carry).

● Two K-Maps are required to derive the logical expression of Sum and Carry.

● The rules of binary addition are used to derive the characteristic equation of Half adder.

● The applications of Half adder include calculators, full adder, ALU of the computer.

● A full adder takes two binary numbers plus a carry or overflow bit. The output is a sum and
another carry bit.  

● Full adders are made from XOR, AND and OR gates in hardware.

● Full adders are commonly connected to each other to add bits to an arbitrary length of bits,
such as 32 or 64 bits.

Terminal Questions
1. Draw half adder logic circuit.
2. Explain truth table of half adder.
3. Write Boolean equation of half adder sum and carry.
4. Draw full adder logic circuit.
5. Explain truth table of full adder.
6. Write Boolean equation of full adder sum and carry.
7. List the full adder advantage and applications.

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 Answer Keys

Self-Assessment Questions
Question No. Answer
1   B
2   D
3   C
4   C
5   D
6 D
7 C
8 A
9 C
10 A
11 C
12 C
13 A
14 B
15 C
16 C
17 A
18 B
19 D
20 C

Activity
Activity type: Online/offline Duration: 60 mins

1. Explain truth table of half adder using logic circuit

2. Explain truth table of full adder using logic circuit

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Glossary
● Combinational system: a logical system with no memory for which the output depends
only on the current input values.
● Truth table: tabular list of all possible input combinations for a combinational system and
the corresponding output(s)
● Logical Product: a logical term that is the Boolean AND of two or more variables.
● Logical Sum: the Boolean OR of two or more variables.
● Combinational Logic: Circuits made up of a mixture of logic gates, with no feedback from
outputs to inputs.
● Half Adder: Logic circuit with two inputs and two outputs. The inputs are a bit from the
augend and a bit from the addend, respectively.
● Full Adder: Logic circuit with three inputs and two outputs. The inputs are a carry bit (Cin)
from a former stage, a bit from the augend, and a bit from the added, respectively.

Bibliography
● Mano, M. (1992). Computer System Architecture. PHI.
● Stallings, W. (2015). Computer System Architecture. PHI.
● Brown, S., & Vranesic, Z. (2008). Fundamentals of Digital Logic with Verilog Design (2nd
ed.). McGraw-Hill.
● Mano, M. (2017). Digital Logic and Computer Design. Pearson.
● Jain, R. P. (2009). Modern Digital Electronics (4th ed.). Tata McGraw Hill.

  

e-References
● https://www.elprocus.com/introduction-to-combinational-logic-circuits/

● https://www.elprocus.com/half-adder-and-full-adder/

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 Video links
● https://youtu.be/_yHo2qq82P0
● https://youtu.be/C4MdUQJIhSE
● https://youtu.be/aLUY-s7LSns
● https://youtu.be/RK3P9L2ZXk4

Image credits
● Fig.1: Block Diagram of Combinational Logic Circuit
● https://www.electronics-tutorials.ws/combination/comb_1.html
● Fig.2: Logic diagram of OR Gate
● https://cse14-iiith.vlabs.ac.in/exp/transistor-level-xor/
● Fig.3: Logical expression of Half Adder.
● https://silo.tips/download/tema-11-sistemas-combinacionales
● Fig.4: Block diagram and Circuit diagram of half adder
● https://sites.ualberta.ca/~gingrich/courses/phys395/notes/node129.html

Keywords
● Half Adder
● Full Adder
● Truth Table
● Boolean Equation
● Logic Circuit

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 Computer Organisation and Architecture

Module - 4

Unit - 2

Combinational Circuits
Subtractors

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 Table of Contents
Unit 4.2 Combinational Circuits - Subtractors

Aim -------------------------------------------------------------------------------------------------- 201

Instructional Objectives ------------------------------------------------------------------------ 201
Learning Outcomes ----------------------------------------------------------------------------- 201
4.2.1 Half Subtractor, Full Subtractor ------------------------------------------------------ 202
         Self-Assessment Questions ----------------------------------------------------------- 207
Summary ------------------------------------------------------------------------------------------    210
Terminal Questions  ---------------------------------------------------------------------------- 210
Answer Keys ------------------------------------------------------------------------------------- 211
Activity ---------------------------------------------------------------------------------------------    211
Glossary -------------------------------------------------------------------------------------------   212
Bibliography --------------------------------------------------------------------------------------   212
e-References  ------------------------------------------------------------------------------------ 212
Video links  ---------------------------------------------------------------------------------------- 212
Image credits -------------------------------------------------------------------------------------  213
Keywords ------------------------------------------------------------------------------------------ 213

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Aim
To introduce students to the basic concepts of Logic gates-based Combinational Logic
circuits, Subtractor, for computer architecture modules.  

Instructional Objectives
This unit intends to:
● Explain the architectural and logic design of combinational logic circuit - Subtractor
● Describe their relevance and applications in new age

Learning Outcomes
Upon completion of this unit, you will be able to:
● Illustrate architectural and logic design of combinational logic circuit - Subtractor
● Analyse their relevance and applications in new age

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4.2.1 Half Subtractor, Full Subtractor
Introduction:
In digital electronics, a subtractor is a combinational logic circuit that can perform the subtraction of
two number (binary numbers) and produce the difference between them. It is a combinational circuit
that means its output depends on its present inputs only. Although, in practice, the subtraction of two
binary number is accomplished by taking the 1’s or 2’s compliment of the subtrahend and adding it to
the minuend. In this way, the subtraction operation of binary numbers can be converted into simple
addition operation which makes hardware construction simple and less expensive.

Half Subtractor Logic Design:

A half-subtractor is a combinational logic circuit that have two inputs and two outputs (i.e., difference
and borrow). The half subtractor produces the difference between the two binary bits at the input and
produces a borrow output (if any). In the subtraction (A-B), A is called as Minuend bit and B is called
as Subtrahend bit.

Truth Table:
Now, let us understand the operation of the half subtractor circuit. Half subtractor performs its operation
to find the difference of two binary digits according to the rules of binary subtraction, which are as
follows:

The output borrow of b is zero (0) if the minuend bit (A) is greater than or equal to the subtrahend bit
(B), i.e. A ≥ B. The output borrow is a 1 when A = 0 and B = 1.

From the logic circuit diagram of the half subtractor, the difference bit (d) is obtained by the XOR
operation of the two inputs A and B, and the borrow bit is obtained by AND operation of the compliment
of the minuend (A’) with the subtrahend (B).

Table 1: Truth Table of half subtractor

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Logical Expression:

           

                             Fig. 1: Logical Expression of Half Subtractor

The characteristic equations of the half subtractor, i.e., equations of the difference bit (d) and the
output borrow bit (b) are obtained by following the rules of binary subtraction. These equations are
given as follows:

The difference bit (d) of the half subtractor is given by XORing the two inputs A and B.

Therefore,

Difference, d = A⊕B = AB’+A’B

The borrow (b) of the half subtractor is the AND of A’ (compliment of A) and B. Therefore,

Barrow, b = A’B

Implementation:
Hence, from the logic circuit diagram, a half subtractor can be realized using an XOR gate together
with a NOT gate and an AND gate.

In the half subtractor as shown in the figure, A and B are the inputs, d and b are the outputs. Where,
d indicates the difference and b indicates the borrow output. The borrow output (b) is the signal that
tells the next stage that a 1 has been borrowed.

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 Fig. 2: Block diagram and Circuit diagram of half subtractor

Applications of half Subtractor

The following are some important applications of half subtractor:

● Half subtractor is used in ALU (Arithmetic Logic Unit) of processors.

● Half subtractor can also be used in amplifiers to compensate the sound distortion.

● It is also used to decrease the force of radio signals or audio signals.

● Half subtractor is also used to increase or decrease operators.

Full Subtractor

Introduction:
A full-subtractor is a combinational circuit that has three inputs A, B, and bin and two outputs d and
b, where, A is the minuend, B is subtrahend, bin is borrow produced by the previous stage, d is the
difference output and b are the borrow output.

Since, the half subtractor can only be used to find the difference of LSBs (Least Significant Bits) of
two binary numbers. Thus, if there is any borrow during the subtraction of the LSBs, it will affect the
subtraction of the next bits of numbers. To overcome this problem of the half subtractor, a full subtractor
is realised.  

Full Subtractor Logic Design:

Now, let us understand the operation of the full subtractor. Full subtractor performs its operation to find
the difference between two binary numbers according to the rules of binary subtraction, which are as
follows:

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In the case of a full subtractor, the 1s and 0s for the output variables (difference and borrow) are
determined from the subtraction of A – B – bin.

From the logic circuit diagram of the full subtractor, the difference bit (d) is obtained by the XOR
operation of the two inputs A, B, and bin, and the output borrow bit (b) is obtained by NOT, AND, and
OR operations of variable A, B, and bin.

Truth Table:
The truth table is one that gives the relationship between the input and output of a logic circuit. The
following is the truth table of the full-subtractor:

Table 2: Truth Table of full subtractor

Logical Expression:

                                      Fig. 3: Logical Expression of Full Subtractor

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The characteristic equations of the full subtractor, i.e., equations of the difference (d) and borrow
output (b) are obtained by following the rules of binary subtraction. These equations are given below:
The difference (d) of the full subtractor is the XOR of A, B, and bin. Therefore,
Difference, d = A⊕B⊕bin = A’B’b’in+A’Bb’in+ABbin
The borrow (b) of the full subtractor is given by,
Borrow, b = A’B’bin+A’Bb’in+ABbin
Or

Borrow, b = A’B (bin+b’in) + (AB+A’B’) bin = A’B+(A⊕B)’bin

Implementation:
We can realise the full-subtractor using two XOR gates, two NOT gates, two AND gates, and one OR
gate.

Fig. 4: Block diagram and Circuit diagram of full subtractor

Applications of Full Subtractor

The following are some important applications of full subtractor:

● Full subtractors are used in ALU (Arithmetic Logic Unit) in computers CPUs (Central
Processing Unit).

● Full subtractors are extensively used to perform arithmetical operations like subtraction in
electronic calculators and many other digital devices.

● Full subtractors are used in different microcontrollers for arithmetic subtraction.

● They are used in timers and program counters (PC).

● Full subtractors are also used in processors to compute addresses, tables, etc.

• Full subtractors are also used in DSP (Digital Signal Processing) and networking-based
systems.

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Self-Assessment Questions

1) The binary subtraction of 0 – 0 =?

A) Difference = 0, borrow = 0
B) Difference = 1, borrow = 0
C) Difference = 1, borrow = 1
D) Difference = 0, borrow = 1

2) How many basic binary subtraction operations are possible?

A) 1
B) 4
C) 3
D) 2

3) When performing subtraction by addition in the 2’s-complement system ____________.

A) The minuend and the subtrahend are both changed to the 2’s-complement
B) The minuend is changed to 2’s-complement and the subtrahend is left in its
original form
C) The minuend is left in its original form and the subtrahend is changed to its
2’s-complement
D) The minuend and subtrahend are both left in their original form

4) Half subtractor is used to perform subtraction of ___________.

A) 2 bits
B) 3 bits
C) 4 bits
D) 5 bits

5) For subtracting 1 from 0, we use to take a _______ from neighbouring bits.

A) Carry
B) Borrow
C) Input
D) Output

6) How many outputs are required for the implementation of a subtractor.

A) 1
B) 2
C) 3
D) 4

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 7) Let A and B is the input of a subtractor then the output will be ___________.

A) A XOR B
B) A AND B
C) A OR B
D) A EXNOR B

8) Let A and B is the input of a subtractor then the borrow will be ___________.

A) A AND B’
B) A’ AND B
C) A OR B
D) A AND B

9) What does minuend and subtrahend denote in a subtractor?

A) Their corresponding bits of input

B) Its outputs
C) Its inputs
D) Borrow bits

10) Which condition do Bout (borrow output) is set to “1”, when X and Y are 2 inputs?

A) x
B) x>y
C) x=y
D) x=0

11) Full subtractor is used to perform subtraction of ___________.

A) 2 bits
B) 3 bits
C) 4 bits
D) 8 bits

12) The full subtractor can be implemented using ___________.

A) Two XOR and an OR gates

B) Two half subtractors and an OR gate
C) Two multiplexers and an AND gate
D) Two comparators and an AND gate

13) The output of a subtractor is given by (if A, B and X are the inputs).

A) A AND B XOR X
B) A NOR B XOR X
C) A OR B NOR X
D) A XOR B XOR X

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14) The output of a full subtractor is same as ____________.

A) Half adder
B) Half subtractor
C) Full adder
D) Decoder

15)When the inputs A, B, Bin is (0,0,0) then the Difference output of full subtractor
is________?

A) 0
B) 1
C) x
D) All the above

16) When the inputs A, B, Bin is (0,1,0) then the Borrow output of full subtractor is________?

A) 0
B) x
C) 1
D) All the above

17) Which of the following is used to represent full subtractor logical circuits equation?

A) K-map
B) Q-map
C) Graph
D) All the above

18) Which of the following gates do full subtractor Difference component requires to obtain
output?

A) XOR
B) AND
C) NOT  
D) OR

19) Which of the following is the first step of Borrow equation of full subtractor?

A) Do AND operation of 2 inputs

B) Do XOR operation of 2inputs
C) Do OR operation of 2 outputs of previous step
D) All the above

20) The input to full subtractor is in ___ form.

A) Binary
B) Analog
C) Signal
D) Both a and b

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 Summary
● A half-subtractor is a combinational logic circuit that have two inputs and two outputs (i.e.,
difference and borrow).  
● The half subtractor produces the difference between the two binary bits at the input and
produces a borrow output (if any).
● By following the rules of binary subtraction, the characteristic equations of the half
subtractor obtained.
● The logic circuit diagram of Half Subtractor is formed using an XOR gate together with a
NOT and AND gate.
● A full subtractor is a combinational circuit that performs subtraction involving three bits,
namely A (minuend), B (subtrahend), and Bin (borrow-in).  
● It accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces
two outputs: D (difference) and Bout (borrow out).
● By following the rules of binary subtraction, the characteristic equations of the full subtractor
obtained.
● The logic circuit diagram of Full Subtractor is formed using two XOR, two NOT, two AND,
and one OR.

Terminal Questions
1. Draw half subtractor logic circuit.
2. Explain truth table of half subtractor.
3. Write Boolean equation of half subtractor difference and barrow.
4. Draw full subtractor logic circuit.
5. Explain truth table of full subtractor.
6. Write Boolean equation of full subtractor difference and barrow.
7. List the full subtractor advantage and applications.

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Answer Keys

Self-Assessment Questions
Question No. Answer
1   A
2   B
3   C
4   A
5   B
6 B
7 A
8 B
9 C
10 A
11 B
12 B
13 D
14 C
15 A
16 C
17 A
18 A
19 A
20 D

Activity
Activity type: Online/offline Duration: 50 mins

1. Explain truth table of half subtractor using logic circuit

2. Explain truth table of full subtractor using logic circuit

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 Glossary
● Half Subtractor: A Half Subtractor is a multiple output Combinational Logic Circuit that
does the subtraction of two 1-bit binary numbers.
● It has two inputs and two outputs.
● The two inputs correspond to the two 1-bit binary numbers and the two outputs corresponds
to the Difference bit and Borrow bit (in contrast to Sum and Carry in Half Adder).
● Full Subtractor: A Full Subtractor is a combinational logic circuit which performs a
subtraction between the two 1-bit binary numbers
● It also considers the borrow of the previous bit, i.e., whether 1 has been borrowed by the
previous minuend bit.

Bibliography
● Mano, M. (1992). Computer System Architecture. PHI.
● Stallings, W. (2015). Computer System Architecture. PHI.
● Brown, S., & Vranesic, Z. (2008). Fundamentals of Digital Logic with Verilog Design (2nd
ed.). McGraw-Hill.
● Mano, M. (2017). Digital Logic and Computer Design. Pearson.
● Jain, R. P. (2009). Modern Digital Electronics (4th ed.). Tata McGraw Hill.

e-References

● https://www.elprocus.com/half-subtractor-circuit-construction-using-logic-gates/

Video links
● https://youtu.be/SV4VTYWxKV4

● https://youtu.be/dBXGGWbtt6U

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Image credits
Fig.1: Logical Expression of Half Subtractor

● https://teachics.org/computer-organization-and-architecture-tutorial/half-subtractor/

Fig.2: Block diagram and Circuit diagram of half subtractor

● https://geek-docs.com/computer/digital-electronic/t_realization-of-a-full-subtractor-us-
ing-two-half-subtractors.html

Fig.3: Logical Expression of Full Subtractor

● https://www.eeeguide.com/half-subtractor-and-full-subtractor-circuit/

Fig.4: Block diagram and Circuit diagram of full subtractor

● https://geek-docs.com/computer/digital-electronic/t_realization-of-a-full-subtractor-us-
ing-two-half-subtractors.html

Keywords
● Half Subtractor
● Full Subtractor
● Truth Table
● Boolean Equation
● Logic Circuit

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 Computer Organisation and Architecture

Module - 4

Unit - 3

Combinational Circuits
Multiplexers and
De-multiplexers

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Table of Contents
Unit 4.3 Combinational Circuits - Multiplexers and De-multiplexers
Aim  ----------------------------------------------------------------------------------------------------------- 216
Instructional Objectives   --------------------------------------------------------------------------------- 216
Learning Outcomes  -------------------------------------------------------------------------------------- 216
4.3.1 Multiplexer, De-multiplexer ----------------------------------------------------------------------- 217
         Self-Assessment Questions --------------------------------------------------------------------- 232
Summary  ----------------------------------------------------------------------------------------------------   235
Terminal Questions  --------------------------------------------------------------------------------------- 235
Answer Keys ------------------------------------------------------------------------------------------------ 236
Activity   ------------------------------------------------------------------------------------------------------ 236
Glossary  ----------------------------------------------------------------------------------------------------- 237
Bibliography   ----------------------------------------------------------------------------------------------- 237
e-References   ---------------------------------------------------------------------------------------------- 237
Video links ---------------------------------------------------------------------------------------------------   237
Image credits  ----------------------------------------------------------------------------------------------- 238
Keywords  --------------------------------------------------------------------------------------------------- 239

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 Aim
To introduce students the basic concepts of Logic gates based Combinational Logic circuits,
Multiplexer and De-multiplexer, for computer architecture modules.  

Instructional Objectives
This unit intends to:

● Explain the architectural and logic design of combinational logic circuit – Multiplexer and
De-multiplexer

Learning Outcomes
Upon completion of this unit, you will be able to:

● Illustrate architectural and logic design of combinational logic circuit – Multiplexer and
De-multiplexer

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4.3.1 Multiplexer, De-multiplexer
Introduction:
A multiplexer is a combinational circuit that has 2n input lines and a single output line. Simply, the
multiplexer is a multi-input and single-output combinational circuit. The binary information is received
from the input lines and directed to the output line. Based on the values of the selection lines, one of
these data inputs will be connected to the output.

Unlike encoder and decoder, there are n selection lines and 2n input lines. So, there is a total of 2N
combinations of inputs. A multiplexer is also treated as Mux.

Multiplexer Logic Design

2×1 Multiplexer (With Enable-E):

In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S0 and single
outputs, i.e., Y. Based on the combination of inputs which are present at the selection line S0, one
of these 2 inputs will be connected to the output. The block diagram and the truth table of the 2×1
multiplexer is given below.

Fig. 1: Block diagram of 2x1 multiplexer

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Truth Table:

Table 1: Truth Table of 2x1 multiplexer

Logical Expression:
The logical expression of the term Y is as follows:

Y=E.S0’. A0+ E.S0.A1

Implementation:

Fig. 2: Logic diagram of 2x1 multiplexer

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4×1 Multiplexer (Without Enable-E):
In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1, A2, and A3, 2 selection lines, i.e., S0
and S1 and single output, i.e., Y. Based on the combination of inputs that are present at the selection
lines S0 and S1, one of these 4 inputs are connected to the output. The block diagram and the truth
table of the 4×1 multiplexer is given below:

Fig. 3: Block diagram of 4x1 multiplexer

Table 2: Truth Table of 4x1 multiplexer

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The logical expression of the term Y is as follows:

Y=S1’ S0’ A0+S1’ S0 A1+S1 S0’ A2+S1 S0 A3

Logical circuit of the above expression is given below:

Fig. 4: Logic diagram of 4x1 multiplexer

Logic Design using Multiplexer

Example - 1: Implementation of NOT gate using 2: 1 Mux

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 Fig. 5: Block diagram of NOT gate using 2x1 multiplexer

We can analyse it  

Y = x.’1 + x.0 = x’

It is NOT Gate using 2:1 MUX.

The implementation of NOT gate is done using “n” selection lines. It cannot be implemented using “n-1”
selection lines. Only NOT gate cannot be implemented using “n-1” selection lines.

Example - 2: Implementation of AND gate using 2: 1 Mux

Fig. 6: Block diagram of AND gate using 2x1 multiplexer

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Example - 3: Implementation of OR gate using 2: 1 Mux

Fig. 7: Block diagram of OR gate using 2x1 multiplexer

Implementation of NAND, NOR, XOR and XNOR gates requires two 2:1 Mux. First, the multiplexer will
act as a NOT gate which will provide complemented input to the second multiplexer.

Example - 4: Implementation of NAND gate using 2: 1 Mux

Fig. 8: Block diagram of NAND gate using 2x1 multiplexer

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Example - 5: Implementation of NOR gate using 2: 1 Mux

Fig. 9: Block diagram of NOR gate using 2x1 multiplexer

Example - 6: Implementation of EXOR gate using 2: 1 Mux

Fig. 10: Block diagram of EXOR gate using 2x1 multiplexer

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Example - 7: Implementation of EXNOR gate using 2: 1 Mux

Fig. 11: Block diagram of ENXOR gate using 2x1 multiplexer

Example - 8: Implementation of 4:1 Mux using 2: 1 Mux

Fig. 12: Block diagram of 4:1 Multiplexer using 2x1 multiplexer

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Example - 9: Implement f (A, B, C) = Σ (1, 2, 3, 5, 6) with do not care (7) using 4:1 MUX
1) AB as select: ​Expanding the minterms to its Boolean form and will see its 0 or 1 value in Cth place
so that they can be placed in that manner

Fig. 13: Block diagram of SOP Logic using 4x1 multiplexer [AB as Select]

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2) AC as select: Expanding the minterms to its Boolean form and will see its 0 or 1 value in Bth
place so that they can be place in that manner.

Fig. 14: Block diagram of SOP Logic using 4x1 multiplexer [AC as Select]

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3) BC as select: ​Expanding the minterms to its Boolean form and will see its 0 or 1 value in Ath place
so that they can be place in that manner.

Fig. 15: Block diagram of SOP Logic using 4x1 multiplexer [BC as Select]

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De-multiplexer

Introduction:
A De-multiplexer is a combinational circuit that has only 1 input line and 2N output lines. Simply, the
multiplexer is a single-input and multi-output combinational circuit. The information is received from
the single input lines and directed to the output line. Based on the values of the selection lines, the
input will be connected to one of these outputs. De-multiplexer is opposite to the multiplexer.

Unlike encoder and decoder, there are n selection lines and 2n outputs. So, there is a total of 2n
combinations of inputs. De-multiplexer is also treated as De-mux.

De-multiplexer Logic Design

1×2 De-multiplexer (With Enable-E):

In the 1 to 2 De-multiplexers, there are only two outputs, i.e., Y0, and Y1, 1 selection lines, i.e., S0,
and single input, i.e., A. Based on the selection value, the input will be connected to one of the outputs.
The block diagram and the truth table of the 1×2 multiplexer is given below.

Fig. 16: Block diagram of 1x2 de-multiplexer

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Truth Table:

Table 3: Truth Table of 1x2 de-multiplexer

Logical Expression
The logical expression of the term Y is as follows:

Y0= E.S0’. A

Y1= E.S0.A

Implementation:

Fig. 17: Logic diagram of 1x2 de-multiplexer

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1×4 De-multiplexer (Without Enable-E):
In 1 to 4 De-multiplexer, there are a total of four outputs, i.e., Y0, Y1, Y2, and Y3, 2 selection lines,
i.e., S0 and S1 and single input, i.e., A. Based on the combination of inputs which are present at the
selection lines S0 and S1, the input is connected to one of the outputs. The block diagram and the
truth table of the 1×4 multiplexer is given below:

Fig. 18: Block diagram of 1x4 de-multiplexer

Table 4: Truth Table of 1x4 de-multiplexer

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The logical expression of the term Y is as follows:

Y0=S1’ S0’ A

y1=S1’ S0 A

y2=S1 S0’ A

y3=S1 S0 A

Logical circuit of the above expressions is given below:

Fig. 19: Logic diagram of 1x4 de-multiplexer

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 Self-Assessment Questions

1) A digital multiplexer is a combinational circuit that selects ___________.

A) One digital information from several sources and transmits the selected one
B) Many digital information and convert them into one
C) Many decimal inputs and transmits the selected information
D) Many decimal outputs and accepts the selected information

2) In a multiplexer, the selection of a particular input line is controlled by ___________.

A) Data controller
B) Selected lines
C) Logic gates
D) Both data controller and selected lines

3) If the number of n selected input lines is equal to 2^m then it requires _________ select
lines.

A) 2
B) m
C) n
D) 2n

4) How many select lines would be required for an 8-line-to-1-line multiplexer:

A) 2
B) 4
C) 8
D) 3

5) A basic multiplexer principle can be demonstrated by a ___________.

A) Single-pole relay
B) DPDT switch
C) Rotary switch
D) Linear stepper

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6) How many NOT gates are required for the construction of a 4-to-1 multiplexer:

A) 3
B) 4
C) 2
D) 5

7) The enable input is also known as ___________.

A) Strobe
B) Decoded input
C) Select input
D) Sink

8) If inputs (a,b) are (0,1) for a 2by 1 mux with selector ‘0’. Then the output is __________.

A) 1
B) 0
C) x
D) None of the above

9) A multiplexer is constructed using __________ components.

A) Active
B) Passive
C) Both a and b
D) Zero components

10) Which of the following is the Digital type of multiplexer?

A) Frequency Division Multiplexing

B) Asynchronous TDM
C) Synchronous TDM
D) Both b and c

11) The word demultiplex means ___________.

A) One into many

B) Many into one
C) Distributor
D) One into many as well as Distributor

12) Why is a demultiplexer called a data distributor?

A) The input will be distributed to one of the outputs

B) One of the inputs will be selected for the output
C) The output will be distributed to one of the inputs
D) Single input to Single Output

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 13) Most demultiplexers facilitate which type of conversion:

A) Decimal-to-hexadecimal
B) Single input, multiple outputs
C) AC to DC
D) Odd parity to even parity

14) In a 1-to-4 demultiplexer, how many select lines are required:

A) 2
B) 3
C) 4
D) 5

15) In a multiplexer the output depends on its ___________.

A) Data inputs
B) Select inputs
C) Select outputs
D) Enable pin

16) Where do the demultiplexers use?

A) Receiver
B) Transmitter
C) Both a and b
D) None of the above

17) When the enable input is zero, s1=0, S0=0 in the 1:4 demultiplexer then the outputs Y0,
Y1, Y2, and Y3 are ________________?

A) Y0=Y1=Y2=Y3=1
B) Y0=Y1=Y2=Y3=0
C) Y1=Y2=Y3=0, Y0=1
D) Y1=Y2=Y3=1, Y0=0

18) Which one of the following is a disadvantage of a demultiplexer?

A) Used as decoders
B) Increases the communication system efficiency
C) Wastage of bandwidth may occur
D) All of the above  

19) Which one of the following logics circuits the memory element is not present?

A) Sequential logic circuit

B) Combinational logic circuit
C) Both a and b
D) None of the above

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20) The encoder, multiplexers, decoder, and demultiplexers are examples for
__________________ logic circuit?

A) Sequential logic circuit

B) Combinational logic circuit
C) Both a and b
D) None of the above

Summary

● A multiplexer makes it possible for several input signals to share one device or resource,
for example, one analogue-to-digital converter or one communications transmission medi-
um, instead of having one device per input signal.  
● Multiplexers can also be used to implement Boolean functions of multiple variables.
● In the 2×1 multiplexer, two inputs, one selection lines and one single output constitutes the
operation.
● In the 4×1 multiplexer, four inputs, two selection lines and one single output constitutes the
operation.
● As the name infers, a demultiplexer performs the opposite function to that of a multiplexer.
A single data line can be connected to any one of the output lines provided by the choice
of an appropriate select signal. If there are s select inputs, then the number of output lines
to which the data can be routed is n = 2s.
● 1 to 2 De-multiplexers comprise one single input, two outputs and one selection line.  
● 1 to 4 De-multiplexers comprise one single input, four outputs and two selection lines.

Terminal Questions
1. Draw a 2x1 multiplexer logic circuit with enable.

2. Explain the truth table of the 4x1 multiplexer with enable.

3. Write the Boolean equation of 4x1 multiplexer without enabling.

4. Design 4X1 multiplexer using 2x1 multiplexer.

5. Draw 1x2 de-multiplexer logic circuit with enable.

6. Explain the truth table of 1x4 de-multiplexer with enable.

7. Write the Boolean equation of 1x4 de-multiplexer without enabling.

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 Answer Keys

Self-Assessment Questions
Question No. Answer
1   A
2   B
3   B
4   D
5   C
6 C
7 A
8 A
9 C
10 D
11 D
12 A
13 B
14 A
15 B
16 A
17 B
18 C
19 B
20 B

Activity
Activity type: Online/offline Duration: 50 min

1. Explain the truth table of 8x1 the multiplexer using the logic circuit.

2. Explain the truth table of 1x8 demultiplexer using a logic circuit

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Glossary
● Multiplexer (MUX): A logic circuit that, depending on the status of its selected inputs, will
channel one of several data inputs to its outputs.
● Demultiplexer (DEMUX): A logic circuit that depending on the position of its select inputs,
will channel its data input to one of several data outputs.

Bibliography
● Mano, M. (1992). Computer System Architecture. PHI.
● Stallings, W. (2015). Computer System Architecture. PHI.
● Brown, S., & Vranesic, Z. (2008). Fundamentals of Digital Logic with Verilog Design (2nd
ed.). McGraw-Hill.
● Mano, M. (2017). Digital Logic and Computer Design. Pearson.
● Jain, R. P. (2009). Modern Digital Electronics (4th ed.). Tata McGraw Hill.

e-References
● https://www.elprocus.com/what-is-multiplexer-and-demultiplexer-types-and-differences/

Video links

● https://youtu.be/t3Ed13z9uz8
● https://youtu.be/FKvnmxte98A

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 Image Credits
Fig.1: Block diagram of 2x1 multiplexer

● https://www.javatpoint.com/multiplexer-digital-electronics

Fig.2: Logic diagram of 2x1 multiplexer

● https://www.javatpoint.com/multiplexer-digital-electronics

Fig.3: Block diagram of 4x1 multiplexer

● https://www.javatpoint.com/multiplexer-digital-electronics

Fig.4: Logic diagram of 4x1 multiplexer

● https://www.javatpoint.com/multiplexer-digital-electronics

Fig.5: Block diagram of NOT gate using 2x1 multiplexer.

● https://www.geeksforgeeks.org/multiplexers-in-digital-logic/

Fig.6: Block diagram of AND gate using 2x1 multiplexer

● https://www.geeksforgeeks.org/multiplexers-in-digital-logic/

Fig.7: Block diagram of OR gate using 2x1 multiplexer

● https://www.geeksforgeeks.org/multiplexers-in-digital-logic/

Fig.8: Block diagram of NAND gate using 2x1 multiplexer.

● https://www.geeksforgeeks.org/multiplexers-in-digital-logic/

Fig.9: Block diagram of NOR gate using 2x1 multiplexer.

● https://www.geeksforgeeks.org/multiplexers-in-digital-logic/

Fig.10: Block diagram of EXOR gate using 2x1 multiplexer.

● https://www.geeksforgeeks.org/multiplexers-in-digital-logic/

Fig.11: Block diagram of ENXOR gate using 2x1 multiplexer

● https://www.geeksforgeeks.org/multiplexers-in-digital-logic/

Fig.12: Block diagram of 4:1 Multiplexer using 2x1 multiplexer

● https://www.geeksforgeeks.org/multiplexers-in-digital-logic/

Fig.13: Block diagram of SOP Logic using 4x1 multiplexer [AB as Select]

● https://www.geeksforgeeks.org/multiplexers-in-digital-logic/

Fig.14: Block diagram of SOP Logic using 4x1 multiplexer [AC as Select]

● https://www.geeksforgeeks.org/multiplexers-in-digital-logic/

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Fig.15: Block diagram of SOP Logic using 4x1 multiplexer [BC as Select]

● https://www.geeksforgeeks.org/multiplexers-in-digital-logic/

Fig.16: Block diagram of 1x2 de-multiplexer

● https://www.javatpoint.com/de-multiplexer-digital-electronics

Fig.17: Logic diagram of 1x2 de-multiplexer

● https://www.javatpoint.com/de-multiplexer-digital-electronics

Fig.18: Block diagram of 1x4 de-multiplexer

● https://www.javatpoint.com/de-multiplexer-digital-electronics

Fig.19: Logic diagram of 1x4 de-multiplexer

● https://www.javatpoint.com/de-multiplexer-digital-electronics

Keywords
● Multiplexer
● De-multiplexer
● Truth Table
● Boolean Equation
● Logic Circuit

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 Computer Organisation and Architecture

Module - 4

Unit - 4

Sequential Circuits
Flip Flops

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Table of Contents
Unit 4.4 Sequential Circuits - Flip Flops

Aim  ---------------------------------------------------------------------------------------------------- 242
Instructional Objectives  -------------------------------------------------------------------------- 242
Learning Outcomes  ------------------------------------------------------------------------------- 242
4.4 Sequential Circuits ---------------------------------------------------------------------------- 243
4.4.1 SR Flip Flops --------------------------------------------------------------------------------- 244
         Self-Assessment Questions -------------------------------------------------------------- 247
4.4.2 JK Flip Flop ----------------------------------------------------------------------------------- 249
Self-Assessment Questions -------------------------------------------------------------- 251
4.4.3 D Flip Flop ------------------------------------------------------------------------------------ 253
Self-Assessment Questions -------------------------------------------------------------- 255
4.4.4 T Flip Flop ------------------------------------------------------------------------------------ 257
Self-Assessment Questions -------------------------------------------------------------- 259
4.4.5 Master Slave JK Flip Flop ---------------------------------------------------------------- 261
Self-Assessment Questions -------------------------------------------------------------- 263
Summary ---------------------------------------------------------------------------------------------    265
Terminal Questions   ------------------------------------------------------------------------------- 266
Answer Keys ----------------------------------------------------------------------------------------- 267
Activity    ---------------------------------------------------------------------------------------------- 268
Glossary   --------------------------------------------------------------------------------------------- 269
Bibliography   ---------------------------------------------------------------------------------------- 269
e-References   -------------------------------------------------------------------------------------- 269
Video Links   ---------------------------------------------------------------------------------------- 270
Image Credits   -------------------------------------------------------------------------------------- 270
Keywords  -------------------------------------------------------------------------------------------- 271

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 Aim
To introduce students to the basic concepts of Flip-flop based sequential logic circuits for
computer architecture modules.  

Instructional Objectives
This unit intends to:
● Describe the design of sequential logic circuit – Flip Flops.
● Explain the Flip-Flops function.
● Demonstrate why sequential logic circuits are important in various computer applications.

Learning Outcomes
Upon completion of this unit, you will be able to:
● Identify the basic components and applications of an architectural and logic design of
sequential logic circuit- Flip Flops.
● Summarise various flip-flop functions.
● Analyse why the architectural and logic design of sequential logic circuits are essential
in digital system.

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4.4 Sequential Circuits
The sequential circuit is a special type of circuit that has a series of inputs and outputs. The outputs
of the sequential circuits depend on both the combination of present inputs and previous outputs. The
previous output is treated as the present state. So, the sequential circuit contains the combinational
circuit and its memory storage elements. A sequential circuit doesn’t need to always contain a
combinational circuit. So, the sequential circuit can contain only the memory element.

Fig. 1: Block diagram of sequential logic circuit

Types of Sequential Circuits

1) Asynchronous sequential circuits

The clock signals are not used by the Asynchronous sequential circuits. The asynchronous circuit
is operated through the pulses. So, the changes in the input can change the state of the circuit. The
asynchronous circuits do not use clock pulses. The internal state is changed when the input variable
is changed. The un-clocked flip-flops or time-delayed are the memory elements of asynchronous
sequential circuits. The asynchronous sequential circuit is similar to the combinational circuits with
feedback.

2) Synchronous sequential circuits

In synchronous sequential circuits, synchronization of the memory element’s state is done by the clock
signal. The output is stored in either flip-flops or latches (memory devices). The synchronization of the
outputs is done with either only the negative edges of the clock signal or only positive edges.

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4.4.1 SR Flip Flops
Introduction:
A flip-flop is a sequential digital electronic circuit having two stable states that can be used to store one
bit of binary data. Flip-flops are the fundamental building blocks of all memory devices.

Types of Flip Flop:  

● S-R flip-flop
● J-K flip-flop
● D flip-flop
● T flip-flop

1) SR Flip Flop:
This is the simplest flip-flop circuit. It has a set input (S) and a reset input (R). When in this circuit when
S is set as active, the output Q would be high and the Q’ will be low. If R is set to active, then the output
Q is low and the Q’ is high. Once the outputs are established, the results of the circuit are maintained
until S or R get changed, or the power is turned off.

Fig. 2: Logic diagram of SR Flip Flop

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Truth Table of S-R flip-flop

Table 1: Truth Table of SR Flip Flop

Characteristics Table of S-R flip-flop

Table 2: Characteristics Table of SR Flip Flop

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Characteristics equation of S-R flip-flop

Q(t+1) = S+R’Q(t)

Excitation Table of SR flip-flop

Table 3: Excitation Table of SR Flip Flop

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Self-Assessment Questions

1) The output of the sequential circuit depends upon _________.

A) Present input
B) Past input
C) Present input and present state
D) None of the above

2) What is the standard form of S-R flip flop?

A) Set Reset
B) Simple-Reset
C) Single-Reset
D) None of the above

3) When the set is enabled in S-R flip flop then the output will be __________.

A) Reset
B) Set
C) No change
D) Indeterminate

4) When both set and reset are disabled in S-R flip flop then the output will be __________.

A) Set
B) Reset
C) No change
D) Indeterminate

5) A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates.

A) AND or OR gates
B) XOR or XNOR gates
C) NOR or NAND gates
D) AND or NOR gates

6) The truth table for an S-R flip-flop has how many VALID entries.

A) 4
B) 3
C) 2
D) 1

7) The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?

A) Because of inverted outputs

B) Because of triggering functionality
C) Because of cross-coupled connection
D) Because of inverted outputs & triggering functionality

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 8) How many possible conversions are there to convert SR flip flop to other flip flops.

A) One
B) Two
C) Three
D) Four

9) _________ are the applications of flip flop.

A) Registers
B) Counters
C) Storage devices
D) All of the above

10) Which circuit doesn’t have a memory unit?

A) Combinational
B) Sequential
C) Both a and b
D) None of the above

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4.4.2 JK Flip Flop
Because of the invalid state corresponding to S=R=1 in the SR flip-flop, there is a need of another flip-
flop. The JK flip-flop operates with only positive or negative clock transitions. The operation of the JK
flip-flop is similar to the SR flip-flop. When the input J and K are different then the output Q takes the
value of J at the next clock edge. When J and K both are low then NO change occurs at the output. If
both J and K are high, then at the clock edge, the output will toggle from one state to the other.

Fig. 3: Logic diagram of JK Flip Flop

Truth Table of J-K flip-flop

Table 4: Truth Table of JK Flip Flop

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Characteristics Table of J-K flip-flop

Table 5: Characteristics Table of JK Flip Flop

Characteristics equation J-K flip-flop

Q(t+1) = JKQ’(t)+R’Q(t)

Excitation Table of JK flip-flop

Table 6: Excitation Table of JK Flip Flop

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Self-Assessment Questions

11) The J-K flip flops has ___________ memory.

A) Temporary
B) Random
C) Nonrandom
D) True

12) The JK flip flop convert to other flip flops in __________.

A) One-way
B) Two ways
C) Three ways
D) Four ways

13) The flip flop is a _______ device.

A) Unstable
B) Bi-stable
C) Both a and b
D) None of the above

14) The J-K flip flop characteristic similar to _________ flip flop.

A) D flip flop
B) T flip flop
C) S-R flip flop
D) None of the above

15) When toggle condition occurs in JK flip flop?

A) J=1, K=1
B) J=0, K=0
C) J=1, K=0
D) J=0, K=1

16) The no-change conditions occur when ________ in JK flip flop.

A) J=1, K=1
B) J=0, K=0
C) J=1, K=0
D) J=0, K=1

17) What is the required flip flop in JK to D flip flop conversion?

A) D flip flop
B) T flip flop
C) S-R flip flop
D) None of the above

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 18) The flip flops are activated by _____________ trigger.

A) Only positive edge

B) Only negative edge
C) Either positive or negative edge
D) None of the above

19) In SR to JK flip flop conversion which one is a required flip flop?

A) SR
B) JK
C) T
D) Both SR and JK

20) The flip flops work with ________.

A) Binary inputs
B) Clock signal
C) Both a and b
D) None of the above

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4.4.3 D Flip Flop:
In a D flip-flop, the output can only be changed at positive or negative clock transitions, and when the
inputs change at other times, the output will remain unaffected. The D flip-flops are generally used for
shift-registers and counters. The change in the output state of the D flip-flop depends upon the active
transition of clock. The output (Q) is the same as input and changes only at active transition of clock.

Fig. 4: Logic diagram of D Flip Flop

Truth Table of D flip-flop

Table 7: Truth Table of D Flip Flop

Characteristics Table of D flip-flop

Table 8: Characteristics Table of D Flip Flop

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Characteristics equation D flip-flop

Q(t+1) = D

Excitation Table of D flip-flop

Table 9: Excitation Table of D Flip Flop

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Self-Assessment Questions

21) In D flip-flop, D stands for ____________.

A) Distant
B) Data
C) Desired
D) Delay

22) The D flip-flop has _______ input.

A) 1
B) 2
C) 3
D) 4

23) A D flip-flop can be constructed from an ______ flip-flop.

A) S-R
B) J-K
C) T
D) S-K

24) In D flip-flop, if clock input is LOW, the D input __________.

A) Has no effect
B) Goes high
C) Goes low
D) Has effect

25) Which statement describes the BEST operation of a negative-edge-triggered D flip-flop?

A) The logic level at the D input is transferred to Q on NGT of CLK

B) The Q output is ALWAYS identical to the CLK input if the D input is HIGH
C) The Q output is ALWAYS identical to the D input when CLK = PGT
D) The Q output is ALWAYS identical to the D input

26) Which of the following describes the operation of a positive edge-triggered D flip-flop?

A) If both inputs are HIGH, the output will toggle

B) The output will follow the input on the leading edge of the clock
C) When both inputs are LOW, an invalid state exists
D) The input is toggled into the flip-flop on the leading edge of the clock and is passed
to the output on the trailing edge of the clock

27) The type of operation performed by flip flop is _______.

A) Synchronous
B) Asynchronous  
C) Both a and b
D) None of the above

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 28) How many possible conversions are there to convert D flip flop to other flip flops.

A) One-way
B) Two ways
C) Three ways
D) Four ways

29) How many NAND gates does the D flip flop circuit consists of.

A) One
B) Two
C) Three
D) Four

30) A positive edge-triggered D flip-flop will store a 1 when ________.

A) The D input is HIGH and the clock transitions from HIGH to LOW
B) The D input is HIGH and the clock transitions from LOW to HIGH
C) The D input is HIGH and the clock is LOW
D) The D input is HIGH and the clock is HIGH

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4.4.4 T Flip Flop
A T flip-flop (Toggle Flip-flop) is a simplified version of JK flip-flop. The T flop is obtained by connecting
the J and K inputs together. The flip-flop has one input terminal and clock input. These flip-flops are
said to be T flip-flops because of their ability to toggle the input state. Toggle flip-flops are mostly used
in counters.

Fig. 5: Logic diagram of T Flip Flop

Truth Table of T flip-flop

Table 10: Truth Table of T Flip Flop

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Characteristics Table of T flip-flop

Table 11: Characteristics Table of T Flip Flop

Characteristics equation T flip-flop

Q(t+1)=T′Q(t)+TQ(t)′=T⊕Q(t)

Excitation Table of T flip-flop

Table 12: Excitation Table of T Flip Flop

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Self-Assessment Questions

31) What is the standard form of T flip flop?

A) Trigger
B) Toggle
C) Trigger or toggled
D) None of the above

32) How many possible conversions are there to convert T flip flop to other flip flops.

A) One way
B) Two ways
C) Three ways
D) Four ways

33) The flip flops require ________.

A) More power
B) More area
C) Less power
D) Both a and b

34) What is the available flip flop in T to D flip flop conversion?

A) D flip flop
B) T flip flop
C) S-R flip flop
D) None of the above

35) The sequential circuit is also called ___________.

A) Flip-flop
B) Latch
C) Strobe
D) Adder

36) Which flip-flop plays a vital role by functioning as the basic building block of a ripple count-
er?

A) S-R flip-flop
B) J-K flip-flop
C) D flip-flop
D) T flip-flop

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 37) T flip- flop finds its application in the form of frequency division since it divides the clock
frequency by __________.

A) 2
B) 4
C) 2n – 1
D) 4n – 1

38) Which among the following statements is correct for the triggering associated with
bistable elements?

A) Latch is level-triggered flip-flop

B) Latch is edge-triggered flip-flop
C) Flip-flop is edge-triggered latch
D) Flip-flop is not edge sensitive

39)   In delay flip-flop, _______ after the propagation delay.

A) Input follows input

B) Input follows output
C) Output follows input
D) Output follows output

40) Which among the following is not a mode of Flip Flop representation?

A) Characteristic Equations
B) Excitation Tables
C) Finite State Machines (FSM)
D) Variable Entered Mapping (VEM)

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4.4.5 Master-Slave JK Flip Flop
A JK flip flop is a type of 1-bit memory element having inputs namely J and K, one clock input, and
two output specified by Q and Q’. The JK flip flop is an improved version of SR flip flop which does not
have forbidden state. To avoid the forbidden or indeterminate state, the outputs of the JK flip flop are
fed back to its inputs.

However, due to these feedback paths, a new problem is raised in the circuit, which is called race
around condition. Race around condition in the JK flip is a major problem in which the outputs of flip
flop are toggled continuously till the end of applied clock signal.

To avoid the problem of race around condition in JK flip flop, we use the JK flip flop in the Master and
Slave Mode. Hence, the JK flip flop is called Master-Slave Flip Flop.

Fig. 6: Logic diagram of Master Slave JK Flip Flop

Master Slave JK Flip Flop is a combination of two JK flip flops which are connected in the cascaded
manner as shown in Figure-1.

In this combination of two JK flip flop, one acts as a master flip flop and the other acts as a slave flip
flop. In this master-slave flip flop, the outputs of the master JK flip flop are connected to the inputs of
the slave JK flip flop. The outputs of the slave flip flop are fed back to the inputs of the master JK flip
flop.

In the master-slave JK flip flop, a NOT gate (Inverter) is also used which is connected to clock signal
in a manner that the inverted clock signal is applied to the slave flip flop.

Therefore, when clock signal to master flip flop is 0, then for slave flip flop the clock signal is 1, and if
the clock signal to master flip flop is 1, then for the slave flip flop it 0.

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Operation of Master-Slave JK Flip Flop

When the clock pulse goes to high, the slave flip flop becomes inactive and the inputs J and K can
control the state of the system.

When the clock pulse goes back to low, the information is transferred from master flip flop to the slave
flip flop, and the final output of the system is obtained.

From the circuit, it is clear that the master flip flop is positive level triggered and the slave flip flop is
negative level triggered. Consequently, the master flip flop responds before the slave flip flop. Now, let
us discuss the operation of the master-slave JK flip flop for different combinations of inputs J and K.

When J = 0 and K = 0, both JK flip flops remains inactive and hence the output Q remains unchanged.
This is called Hold State of the master-slave JK flip flop.

When J = 0 and K = 1, the output Q’ of the master flip flop is high and goes to the input K of the slave
flip flop. The clock signal forces the slave flip flop to reset. Therefore, the slave flip flop has the same
output has the master flip flop, i.e., high Q’ and low Q. This is called reset state of the master-slave
JK flip flop.

When J = 1 and K = 0, the output Q of the master flip flop is high and goes to the input J of the slave
flip flop, the negative transition of the clock signal sets the slave flip flop. Hence, this is called the set
state of the master-slave JK flip flop.

When J = 1 and K = 1, for this input combination, the master flip flop toggles on the positive transition
of the clock pulse and the slave flip flop toggles on the negative transition of the clock pulse. Hence,
the problem of the race around condition of the JK flip flop is solved.

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Self-Assessment Questions

41) Master slave flip flop is also referred to as ____________.

A) Level triggered flip flop

B) Pulse triggered flip flop
C) Edge triggered flip flop
D) Edge-Level triggered flip flop

42) In a positive edge triggered JK flip flop, a low J and low K produces.

A) High state
B) Low state
C) Toggle state
D) No Change State

43) If one wants to design a binary counter, the preferred type of flip-flop is ___________.

A) D type
B) S-R type
C) Latch
D) J-K type

44) Which of the following flip-flops is free from the race around the problem?

A) T flip-flop
B) SR flip-flop
C) Master-Slave Flip-flop
D) D flip-flop

45) Which of the following is the Universal Flip-flop?

A) S-R flip-flop
B) J-K flip-flop
C) Master slave flip-flop
D) D Flip-flop

46) In JK flip flop same input, i.e., at a particular time or during a clock pulse, the output will
oscillate back and forth between 0 and 1. At the end of the clock pulse the value of output Q
is uncertain. The situation is referred to as:

A) Conversion condition
B) Race around condition
C) Lock out state
D) Forbidden State

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 47) S-R type flip-flop can be converted into D type flip-flop if S is connected to R through
____________.

A) OR Gate
B) AND Gate
C) Inverter
D) Full Adder

48) How many types of triggering take place in a flip flop:

A) 3
B) 2
C) 4
D) 5

49) Flip-flops are ____________.

A) Stable devices
B) Astable devices
C) Bistable devices
D) Monostable devices

50) The term synchronous means ____________ .

A) The output changes state only when any of the input is triggered
B) The output changes state only when the clock input is triggered
C) The output changes state only when the input is reversed
D) The output changes state only when the input follows it

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Summary
● SR flip-flop is a gated set-reset flip-flop. The S and R inputs control the state of the flip-flop
when the clock pulse goes from LOW to HIGH. The flip-flop will not change until the clock
pulse is on a rising edge.
● When both S and R are simultaneously HIGH, it is uncertain whether the outputs will be
HIGH or LOW.
● A J-K flip-flop is nothing more than an S-R flip-flop with an added layer of feedback. This
feedback selectively enables one of the two set/reset inputs so that they cannot both carry
an active signal to the multivibrator circuit, thus eliminating the invalid condition.
● A D (or Delay) Flip Flop (Figure 1) is a digital electronic circuit used to delay the change of
state of its output signal (Q) until the next rising edge of a clock timing input signal occurs.
● T Flip-Flop is a single input logic circuit that holds or toggles its output according to the
input state.
● Toggling means changing the next state output to complement the current state. T is an
abbreviation for Toggle. A good example to explain this concept is using a light switch.
● The master-slave flip flop is constructed by combining two JK flip flops. These flip flops
are connected in a series configuration.
● In these two flip flops, the 1st flip flop work as “master”, called the master flip flop, and
the 2nd work as a “slave”, called slave flip flop.

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 Terminal Questions
1. Explain the SR flip-flop state table and excitation table.  

2. Draw and explain the operation of the SR Flip-flop.

3. With the help of a logic circuit and truth table explain the operation of the SR Flip flop.

4. Compare the truth table and excitation table of the SR flip-flop.

5. Explain the JK flip-flop state table and excitation table.  

6. Draw and explain the operation of the JK Flip-flop.

7. With the help of a logic circuit and truth table explain the operation of JK Flip flop.

8. Compare the truth table and excitation table of the JK flip-flop.

9. Explain the D flip-flop state table and excitation table.  

10. Draw and explain the operation of the D Flip-flop.

11. With the help of a logic circuit and truth table explain the operation of the D Flip flop.

12. Compare the truth table and excitation table of the D flip-flop.

13. Explain the T flip-flop state table and excitation table.  

14. Draw and explain the operation of T Flip-flop.

15. With the help of logic circuit and truth table explain the operation of T Flip flop.

16. Compare the truth table and excitation table of T flip-flop.

17. Draw the diagram of Master-Slave JK Flip-flop.

18. Draw and explain the operation of Master-Slave JK Flip-flop.

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Answer Keys

Self-Assessment Questions
Question No. Answer
1 C
2 A
3 B
4 C
5 C
6 B
7 C
8 C
9 D
10 A
11 D
12 C
13 B
14 C
15 A
16 B
17 A
18 C
19 D
20 B
21 D
22 A
23 A
24 A
25 A
26 B
27 A
28 C
29 D
30 B

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 31 C
32 C
33 D
34 B
35 A
36 D
37 A
38 A
39 C
40 D
41 B
42 D
43 D
44 A
45 B
46 B
47 C
48 A
49 C
50 B

Activity
Activity type: Online/offline Duration: 60 mins

1. Explain truth table of SR Flip-Flop using logic circuit.

2. Explain truth table of JK Flip-Flop using logic circuit.

3. Explain truth table of D Flip-Flop using logic circuit.

4. Explain truth table of T Flip-Flop using logic circuit.

5. Explain truth table of Master-Slave JK Flip-Flop using logic circuit.

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Glossary
● Sequential Logic: Logic that is based on the output of a previous state.
● Set: To preset or turn on a flip-flop and cause the output, Q, of a flip flop to assume a 1
level.
● Reset: Term synonymous with “CLEAR” (Q = 0 Logic level)
● Latch: Type of Flip Flop. A circuit that assumes an on state or an off state according to the
input signal.
● R-S Flip Flop: A flip flop that can be turned on with the set input and turn off with the reset.
● JK Flip Flop: A flip flop that can be turned on, turned off, toggled, or left the same according
to control signals on the J and K inputs.
● D flip-flop: A type of bistable multivibrator in which the output assumed the state of the D
input on the triggering edge of a clock pulse.
● Toggle: When a digital device changes state, it is said to toggle.
● Master-Slave Flip Flop: A type of flip flop in which the input data are entered into the
device on the leading edge of the clock pulse and appear at the output on the trailing edge.

Bibliography
● Mano, M. (1992). Computer System Architecture. PHI.
● Stallings, W. (2015). Computer System Architecture. PHI.
● Brown, S., & Vranesic, Z. (2008). Fundamentals of Digital Logic with Verilog Design (2nd
ed.). McGraw-Hill.
● Mano, M. (2017). Digital Logic and Computer Design. Pearson.
● Jain, R. P. (2009). Modern Digital Electronics (4th ed.). Tata McGraw Hill.

e-References
● https://www.tutorialspoint.com/digital_circuits/digital_circuits_sequential_circuits.htm
● https://www.tutorialspoint.com/digital_circuits/digital_circuits_latches.htm
● https://www.tutorialspoint.com/digital_circuits/digital_circuits_flip_flops.htm
● https://www.tutorialspoint.com/digital_circuit/digital_circuits_conversion_of_flip_flops.htm
● https://www.electronics-tutorials.ws/sequential/seq_2.html
● http://www.pmcgibbon.net/teachcte/electron/degloss1.htm

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 Video links
● Introduction to Sequential Circuits | Important
● Introduction to SR Flip Flop
● Introduction to JK flip flop
● Introduction to D flip flop
● Introduction to T flip flop
● https://youtu.be/t2LZtaNck_g

Image Credits

Fig.1: Block diagram of sequential logic circuit

● https://www.javatpoint.com/sequential-circuits-in-digital-electronics

Fig.2: Logic diagram of SR Flip Flop

● https://forums.ni.com/t5/LabVIEW/JK-ff-in-counter-circuit/td-p/1009411

Fig.3: Logic diagram of JK Flip Flop

● https://www.ques10.com/p/14914/draw-the-circuit-of-jk-ff-using-nand-gates-and-wri/?

Fig.4: Logic diagram of D Flip Flop

● https://electronics.stackexchange.com/questions/497756/what-is-the-relevance-of-a-q-
in-the-d-flip-flop-when-using-for-a-memory-module

Fig.5: Logic diagram of T Flip Flop

● https://www.javatpoint.com/basics-of-flip-flop-in-digital-electronics

Fig.6: Logic diagram of Master Slave JK Flip Flop

● https://www.javatpoint.com/master-slave-jk-flip-flop-in-digital-electronics

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Keywords
● SR Flip-Flop
● JK Flip-Flop
● D Flip-Flop
● T Flip-Flop
● Master Slave JK Flip-Flop
● Logic Circuit
● Truth Table
● Characteristics Table
● Characteristics Equation
● Excitation Table

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 Computer Organisation and Architecture

Module - 4

Unit - 5

Conversion of Flip-Flops

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Table of Contents
Unit 4.5 Conversion of Flip - Flops

Aim --------------------------------------------------------------------------------------------- 274

Instructional Objectives ------------------------------------------------------------------- 274
Learning Outcomes  ----------------------------------------------------------------------- 274
4.5.1 Conversion of Flip-Flops ---------------------------------------------------------- 275
         Self-Assessment Questions ------------------------------------------------------ 289
Summary  -------------------------------------------------------------------------------------  290
Terminal Questions -------------------------------------------------------------------------   290
Answer Keys --------------------------------------------------------------------------------- 290
Activity -----------------------------------------------------------------------------------------    291
Glossary --------------------------------------------------------------------------------------   291
Bibliography  --------------------------------------------------------------------------------- 291
e-References   ------------------------------------------------------------------------------- 291
Video links  ----------------------------------------------------------------------------------- 292
Keywords  ------------------------------------------------------------------------------------ 292

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 Aim
To introduce students the basic concepts of Conversion of Flip-Flops to different types.  

Instructional Objectives
This unit intends to:
● Demonstrate the conversion of Flip-Flops to different types

Learning Outcomes
Upon completion of this unit, you will be able to:
● List the several forms of conversion of Flip-Flops and their relevance
  

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4.5.1 Conversion of Flip-Flops
Conversion of flip-flops causes one type of flip-flop to behave like another type of flip-flop. To make
one flip-flop mimic the behaviour of another certain additional circuitry and/or connections become
necessary.

1) Conversion of JK Flip-Flop to SR Flip-Flop

Step 1: Write the Truth Table of the Desired Flip-Flop

Here SR flip-flop is to be designed using JK flip-flop. Thus, one needs to write the truth table for SR
flip-flop.

Table 1: Truth table of SR Flip-Flop

Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table

Excitation tables provide the details regarding the inputs which must be provided to the flip-flop to ob-
tain a definite next state (Qn+1) from the known current state (Qn).

Table 2: Truth Table for JK Flip-Flop Table Table 3: Excitation Table for JK Flip-Flop

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From the truth table of JK flip-flop one can see that Qn+1 will become 0 from Qn = 0 for both (i) J = K
= 0 and (ii) J = 0 and K =1 (blue entries in first and third rows of the truth table).

This means that to obtain the next state, Qn+1 as 0 from the current state Qn = 0, J must be made
zero while K can be either 0 or 1.

This is indicated by the first row of the excitation table (blue entries in the first row of excitation table)
where the value of K is expressed as ‘X’ indicating do not care condition. Similarly, to obtain the next
state as 1 from the current state 0, one must have J equal to 1 while K can be either 0 or 1 (indicated
by green entries of the truth table).

This leads to the second row of excitation table (green entries) to be filled with values Qn = 0, Qn+1 =
1, J = 1 and K = X. On the same grounds, the entire excitation table needs to be filled (entries in pink
and dark red colours).

Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop
appropriately to obtain Conversion Table.

Here the conversion table is obtained by filling-up the values of the J and K inputs for the given Qn
and Qn+1, by referring to the excitation table.

Table 4: Conversion Table

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Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop.

In this case, one needs to arrive at the logical expressions for the inputs J and K in terms of S, R, and
Qn using suitable simplification techniques like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly

Here neither additional circuit nor new connections are necessary.

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2) Conversion of JK Flip Flop to D Flip Flop

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3) Conversion of JK Flip Flop to T Flip Flop

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4) Conversion of SR Flip Flop to JK Flip Flop

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5) Conversion of SR Flip Flop to D Flip Flop

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6) Conversion of SR Flip Flop to T Flip Flop

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7) Conversion of D Flip Flop to JK Flip Flop

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8) Conversion of D Flip Flop to SR Flip Flop

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9) Conversion of D Flip Flop to T Flip Flop

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10) Conversion of T Flip Flop to JK Flip Flop

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11) Conversion of T Flip Flop to SR Flip Flop

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12) Conversion of T Flip Flop to D Flip Flop

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Self-Assessment Questions

1) The output of the sequential circuit depends upon _________ .

A. Present input
B. Past input
C. Present input and present state
D. None of the above

2) The flip flops are categorized into ________ .

A. 2
B. 4
C. 1
D. 3

3) What is the standard form of S-R flip flop?

A. Set Reset
B. Simple-Reset
C. Single-Reset
D. None of the above

4) There are total ______ steps for flip flop conversions.

A. One
B. Two
C. Three
D. Five

5) In SR to JK flip flop conversion which one is an available flip flop?

A. SR
B. JK
C. T
D. Both SR and JK

6) In SR to JK flip flop conversion which one is a required flip flop?

A. SR
B. JK
C. T
D. Both SR and JK

7) How many conversions are there to convert JK flip flop to other flip flops?

A. One
B. Two
C. Three
D. Four

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 Summary
● The conversion of flip-flops from one type to another can be accomplished very easily as
only slight modifications are required to convert one type to another.
● Flip-flops can be constructed using logic gate circuits with feedback.
● The conversion of Flip-Flops from one type to another includes the following steps.
● The truth table of the Desired Flip-Flop must be written.
● The Excitation Table for the given flip-flop is obtained from the Truth Table.
● To append the Excitation Table to the Truth Table of the desired Flip-Flop.
● To simplify the Expressions for the inputs of the given Flip-Flop.
● To design the necessary circuit and make the connections accordingly.

Terminal Questions
1. Convert of T Flip Flop to D Flip Flop.
2. Convert of T Flip Flop to JK Flip Flop.
3. Convert of SR Flip Flop to D Flip Flop.
4. Convert of JK Flip Flop to T Flip Flop.

Answer Keys

Self-Assessment Questions
Question No. Answer
1   C
2   B
3   A
4   D
5   A
6 B
7 B

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Activity
Activity type: Online/offline Duration: 50 min

1. Give a summary report on conversion of flip-flops steps

Glossary
● Q and Q’: The complementary outputs of a flip flop
● Edge-Triggered D Flip Flop: A flip-flop circuit in which the inputs are clocked, and the
outputs appear on the same clock edge.
● Pulse: A sudden change from one level to another, followed a time by a sudden change
back to the original level.
● Truth Table: Method for describing how a logic circuit’s output is dependent upon the
logic levels present at the circuit’s inputs.

Bibliography
● Mano, M. (1992). Computer System Architecture. PHI.
● Stallings, W. (2015). Computer System Architecture. PHI.
● Brown, S., & Vranesic, Z. (2008). Fundamentals of Digital Logic with Verilog Design (2nd
ed.). McGraw-Hill.
● Mano, M. (2017). Digital Logic and Computer Design. Pearson.
● Jain, R. P. (2009). Modern Digital Electronics (4th ed.). Tata McGraw Hill.

e-References
● https://www.tutorialspoint.com/digital_circuit/digital_circuits_conversion_of_flip_flops.htm

● https://www.watelectronics.com/mcq/flip-flops/

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 Video links
● https://youtu.be/JvC-434_T5E
● https://youtu.be/ApJ972OYyXQ
● https://youtu.be/PMJ09EwvnF0
● https://youtu.be/iAEgeuIoEBQ
● https://youtu.be/bl77FRTAXWA

Keywords
● Truth Table
● Excitation Table
● Conversion Table
● K-Map
● Circuit Diagram

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