EXPERIMENT 5 FSM VENDING MACHINE

CODING :
module fsm_40_tb_v;
// Inputs
reg clk;
reg [1:0] coin;
reg rst;

// Outputs
wire nw_pa;

// Instantiate the Unit Under Test (UUT)

fsm_40 uut (
.nw_pa(nw_pa),
.clk(clk),
.coin(coin),
.rst(rst)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
coin = 0;
#100;
clk = 0;
rst = 0;
coin = 1;
#100;
clk = 0;
rst = 1;
coin = 0;
#100;
clk = 0;
rst = 1;
coin = 1;
#100;
clk = 1;
rst = 0;
coin = 0;
#100;
clk = 1;
rst = 0;
coin = 1;
#100;
 clk = 1;
rst = 1;
coin = 0;
#100;
clk = 1;
rst = 1;
coin = 1;
#100;
end
endmodule

TEST BENCH :
module fsm_40_tbs_v;
// Inputs
reg clk;
reg [1:0] coin;
reg rst;

// Outputs
wire nw_pa;

// Instantiate the Unit Under Test (UUT)

fsm_40 uut (
.nw_pa(nw_pa),
.clk(clk),
.coin(coin),
.rst(rst)
);
initial begin
clk=0;
coin=1;
rst=1;
#100
coin=2'b00;
rst=0;
#100
coin=2'b01;
rst=0;
#100
coin=2'b10;
rst=0;
#100
coin=2'b11;
rst=0;
#100
 coin=2'b00;
rst=0;
end
always
#50 clk=~clk;
endmodule

=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : fsm_40.ngr
Top Level Output File Name : fsm_40
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO

Design Statistics
# IOs :5

Macro Statistics :
# Registers :4
# 1-bit register :4

Cell Usage :
# BELS :7
# LUT2 :2
# LUT4 :5
# FlipFlops/Latches :9
# FDC :4
# FDP :1
# LD :4
# Clock Buffers :1
# BUFGP :1
# IO Buffers :4
# IBUF :3
# OBUF :1
=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s100evq100-4

Number of Slices: 5 out of 960 0%

Number of Slice Flip Flops: 9 out of 1920 0%
Number of 4 input LUTs: 7 out of 1920 0%
Number of bonded IOBs: 5 out of 66 7%
Number of GCLKs: 1 out of 24 4%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |5 |
_n0011(_n00112:O) | NONE(*)(next_state_1) | 4 |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with
BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock
signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4
 Minimum period: No path found
Minimum input arrival time before clock: 6.028ns
Maximum output required time after clock: 6.198ns
Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00112:O'
Total number of paths / destination ports: 8 / 4
-------------------------------------------------------------------------
Offset: 6.028ns (Levels of Logic = 3)
Source: coin<1> (PAD)
Destination: next_state_0 (LATCH)
Destination Clock: _n00112:O falling

Data Path: coin<1> to next_state_0

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 5 1.930 1.167 coin_1_IBUF (coin_1_IBUF)
LUT4:I0->O 1 0.752 0.905 _n0000<0>1 (N2)
LUT2:I1->O 1 0.752 0.000 _n0000<0>2 (_n0000<0>)
LD:D 0.522 next_state_0
----------------------------------------
Total 6.028ns (3.956ns logic, 2.072ns route)
(65.6% logic, 34.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 6.198ns (Levels of Logic = 1)
Source: state_3_1 (FF)
Destination: nw_pa (PAD)
Source Clock: clk rising

Data Path: state_3_1 to nw_pa

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 1 0.522 0.801 state_3_1 (state_3_1)
 OBUF:I->O 4.875 nw_pa_OBUF (nw_pa)
----------------------------------------
Total 6.198ns (5.397ns logic, 0.801ns route)
(87.1% logic, 12.9% route)

=========================================================================
CPU : 0.91 / 1.02 s | Elapsed : 1.00 / 1.00 s

-->

Total memory usage is 181040 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 1 ( 0 filtered)
Number of infos : 2 ( 0 filtered)

Post lab :

module asml(input clk,

input reset,
input in,
output reg out);
localparam S0 = 2'b00;
localparam S1 = 2'b01;
localparam S2 = 2'b10;

// State registers
reg [1:0] current_state, next_state;

// State transition logic (Sequential block)

always @(posedge clk or posedge reset) begin
if (reset)
current_state <= S0; // Reset to state S0
else
current_state <= next_state; // Move to the next state
 end
// Next state logic and output logic (Combinational block)
always @(*) begin
// Default values
next_state = current_state;
out = 0;

case (current_state)
S0: begin
if (in)
next_state = S1;
out = 1; // Output in state S0
end
S1: begin
if (in)
next_state = S2;
end

S2: begin
// Stay in S2
out = 1; // Output in state S2
end

default: next_state = S0; // Default to state S0

endcase
end
endmodule

Test bench :
module asml_40tb_v;

// Inputs
reg clk;
reg reset;
reg in;
// Outputs
wire out;

// Instantiate the Unit Under Test (UUT)

asml uut (
.clk(clk),
.reset(reset),
.in(in),
.out(out)
);

initial begin
// Initialize Inputs
clk = 0;
reset = 0;
in = 0;

// Wait 100 ns for global reset to finish

#100;
clk = 0;
reset = 0;
in = 1;
#100;

clk = 0;
reset = 1;
in = 0;
#100;

clk = 0;
reset = 1;
in = 1;
#100;

clk = 1;
reset = 0;
in = 0;
#100;

clk = 1;
reset = 0;
in = 1;
#100;
 clk = 1;
reset = 1;
in = 0;
#100;

clk = 1;
reset = 1;
in =1;
#100;

// Add stimulus here

end

endmodule