UNIT-III

Digital Logic Design (TBC303)

COMBINATIONAL CIRCUITS:

[1]. Combinational Logic

Logic circuits are of two types: 1. Combinational 2. Sequential.

A combinational circuit consists of logic gates. In Combinational circuits the output depends on inputs (at
that time) only, and does not depend on any past I/Ps or O/Ps.A combinational circuit performs a specific
operation, fully specified by a set of Boolean functions. The block diagram of a combinational circuit with m
inputs and n outputs is shown in

Fig. Block diagram of combinational logic circuit

In a combinational circuit, for a change in the input, the output appears immediately, except for the
propagation delay through circuit gates.

Sequential circuits consists of logic gates and memory elements (to store the o/p). The o/p of sequential
circuits depends on the present inputs and the previos o/p. In other words, the outputs of a sequential circuit
depend not only on present inputs, but also on past outputs,

Step 4 : Implement the simplified expression using logic gates.

[2]. Adder

1. Adders Address are used to perform binary addition.

Half Adder

1. A half adder is a combinational circuit. A half adder is used to add only 2 binary bits. A half adder
has two inputs A and B and two outputs S (sum) and C (carry. ). S and C are produced by addition of
A and B. Following Fig. shows block diagram of a half adder (HA).

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2. Truth Table

Inputs Outputs
A B Sum(S) Carry (C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Using a two variable k-map, separately

The equation of sum is  S = A'B + AB' = A ⊕ B

The equation of carry is  C = AB

3. Logical Implementation shown in Fig.

The circuit diagram of half address is given below:

The above diagram can be drawn as given below because A'B + AB' = A ⊕ B

4. Working of Half Adder

Inputs Sum Carry Conclusion

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 S=A⊕B C= AB Sum of 0 and 0 is 0. No
Case1: When A=0, B=0 = 0⊕0 = 0.0 carry generated
= 0 =0
S=A⊕B C= AB Sum of 0 and 1 is 1. No
Case1: When A=0, B=1 = 0⊕1 = 0.1 carry generated
=1 =0
S=A⊕B C= AB Sum of 1 and 0 is 1. No
Case1: When A=1, B=0 = 1⊕0 = 1.0 carry generated
=1 =0
S=A⊕B C= AB Sum of 1 and 1 is 0. carry
Case1: When A=1, B=1 = 1⊕1 = 1.1 generated 1.
= 0 =0

Full Adder

1. A full adder is a combinational circuit. A full adder is used to add 3 binary bits. It has three inputs A,
B and C and two outputs Sum (S) and Carry (C) produced by addition of three input bits. Following
Fig. shows block diagram of a full adder (FA).

2. Truth Table
The truth table of full adder is shown below. We observe that when all the three inputs are 1, the sum
and carry both outputs, are 1.

Inputs Output
A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Using a three variable map for both outputs.

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The equation of sum is  S = ABC + AB'C' + A'BC' + A'B'C
= (A ⊕ B) ⊕ C
The equation of carry is  C0 = AB + AC + BC.

Logical Implementation shown in Fig.

A ‘Full Adder’ can also be implemented using two half adders and an ‘OR’ Gate as shown in Fig.

The Sum can be written as S = ABC + AB'C' + A'BC' + A'B'C = (A ⊕ B) ⊕ C

The carry can be written as C = AB + AC + BC = AB + C (A ⊕ B)

[3]. Subtractors

Subtractor circuits are used used for subtracting binary numbers.

Half Subtractor :

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 1. A half subtractor is a combinational circuit. It is used to subtract only 2 binary bits. Fig. shows a half
subtractor (HS). A half subtractor has two inputs A and B and two outputs D (difference) and
B(borrow. ). Fig. shows a half subtractor. (HS).

2. Truth table
Truth table of hals subtractor is shown below. Remember that if A < B, the subtraction is done by
borrowing 1 from the next higher order bit.

Inputs Outputs
A B D B0
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

3. Using a two variable map, for outputs D and B.

The equation of difference is  D = A'B + AB' = A ⊕ B

The equation of borrow is  Bo = A' B

Logical Implementation shwon in Fig.

(a) Using Basic gates (b) using XOR gate

Basic gate implementation X-OR gate implementation

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Full subtractor:

1. Full subtractor is a combinational circuit that performs the subtraction of three binary digits with
borrow. Suppose you have to subtract A-B (0 – 1) then you have to take borrow. So here C=1 is a
borrow bit.
Fig. shows a full subtractor (FS). It has three inputs A, B and C and two outputs D and B0. Its truth
table is given below:

2. Truth Table

Inputs Output
A B C Difference Borrow
A-B-C
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Using a three variable K-map for both outputs

The equation of difference is  D = ABC + AB'C' + A'BC' + A'B'C

= (A ⊕ B) ⊕C
The equation of borrow is  Bo = A'B + A'C + BC
= A'B + C (A ⊕ B)'

Logical Implementation shown in Fig.

A ‘full subtractor’ can also be implemented using two ‘half subtractors’ and an ‘OR’ gate as shwon in Fig.

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[4]. Parallel adder

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders. Figure shows the interconnection of four full-adder (FA) circuits.

B3 A3 B2 A2 B1 A1 B0 A0
B0 A0 B0 A0 B0 A0 B0 A0

FA-1 FA-1 FA-1 FA-1 Cin

B0 A0

C4 S3 S2 S1 S0

Circuit explanation

 It has 4 full adders FA1, FA2, FA3, FA4. Let the two 4-bit words are A=A3 A2 A1 A0 and B=B3 B2
B1 B0.
 Bits number A and B are connected to all full adders. First bits of both numbers (A0, B0) are
connected to FA-1, second bits of both numbers (A1, B1) are connected to FA-2, third bits of both
numbers (A2, B2) are connected to FA-3, fourth bits of both numbers (A3, B3) are connected to FA-4.
 C0 is initial carry which is equal to 0.
 FA-1 gives sum S0 and carry C1, FA-2 gives sum S1 and carry C2, FA-3 gives sum S2 and carry C3,
FA-4 gives sum S3and carry C4.

Let we Consider an example1101+1010,

A3 A2 A1 A0 B3 B2 B1 B0
A= 1 1 0 1 B= 1 0 1 0

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Here initial carry C0=0
I/P to full adder FA1 are A0 = 1, B0 = 0, C0 = 0
Thus S0 = 1,
C1 = 0

I/P to full adder FA2 are A1 = 0, B1 = 1, C1 = 0

Thus S1 = 1,
C2 = 0

I/P to full adder FA3 are A2 = 1, B2 = 0, C2 = 0

Thus S2 = 1,
C3 = 0

I/P to full adder FA4 are A3 = 1, B3 = C3 = 0

Thus S3 = 0, C4 = 1

So,
C S3 S2 S1 S0
S= 1 0 1 1 1
[5]. Parallel Subtractor.

The 4-bit binary parallel adder/subtractor can be realized with the circuit of 4-bit binary parallel adder. It
uses 2’s complement method of subtraction.

The subtraction of two binary number can be done by adding 2’s complement of the subtrahend with
subtractor. For ex- A-B can be done as A+B'+1.

The 4-bit binary parallel adder/subtractor circuit is shown in Fig. It performs both addition and subtraction.
It has two four bit inputs A3A2A1A0 and B3B2B1B0. The control input line C, connected with the input carry
of the LSB of the full adder, is used to perform both operations. To perform subtraction, the C (control
input) is kept high. The controlled inverter produces the 1's complement of the adder (B'3B'2B'1B'0). Since 1
is given to input carry of the LSB of the adder, it is added to the complemented addend producing 2's
complement of the addend before addition.

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 Fig. Bit binary parallel adder/subtractor

Now the angend (A3A2A1A0) will be added to the 2's complement of addend (A3A2A1A0) to produce the
sum, i.e., the diffrence between the addend and angend, and Cout (output carry), i.e. the borrow output of the
4-bit subtractor.

When the control input ‘C’ is kept low, the controlled inverter allows the addend (B3B2B1B0) without any
change to the input of full adder, and the input carry Cin of LSB of full adder, becomes zero, Now the augend
(A3 A2 A1 A0) and addend (B3 B2 B1 B0) are added with Cin = 0.

Hence, the circuit functions as 4-bit adder resulting in sum S3 S2 S1 S0 and carry output Cout.

[6]. Multiplexer

A digital multiplexer (MUX) is a combinational circuit. It is also called as “Data Selector”. It has n inputs,
some Selection lines and only one output. It select only one input among n inputs and send it in the o/p. For
selecting only one I/P it uses Selection lines or Control lines. There are following types of multiplexer

(i) 2x1 MUX (ii) 4x1 MUX (iii) 8x1 MUX (iv) 16x1 MUX

Note:

In 2x1 MUX  inputs = 2 Selection lines=1 (as2=21) O/Ps = One

In 4x1 MUX  inputs = 4 Selection lines=2 (as 4=22) O/Ps = One
In 8x1 MUX  inputs = 8 Selection lines=3 (as 8=23) O/Ps = One
In 16x1 MUX  inputs = 16 Selection lines=4 (as16=24) O/Ps = One

2x1 MUX

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A 2x1 multiplexer has 2 inputs, one control line (as2=21) and one O/P. Its circuit diagram and truth table is
shown below:

Control I/P O/P

0 I0

1 I1

It has two inputs I0 and I1. S0 is selection line.

Working

Case1: When S0=0 then upper AND gate has I/Ps I0 and 1. AND gate multiples them and gives O/P I0. The
lower AND gate has I/Ps I0 and 0 so lower AND gate gives O/P 0. The OR gate add these I/Ps I0 and 0. So
the final O/P is I0

Case2: When S0=1 then upper AND gate has I/Ps I1 and 0. AND gate multiples them and gives O/P 0. The
lower AND gate has I/Ps I1 and 1 so lower AND gate gives O/P I1. The OR gate add these I/Ps 0 and I1. So
the final O/P is I1

4x1 MUX

A 4x1 multiplexer has 4 inputs (I0, I1, I2, I3,) two selection line (S0 and S1) and one O/P. Its block diagram,
circuit diagram and truth table is shown below:

Block Diagram of 4x1 MUX

Selection I/P O/P

S0 S1
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Truth Table of 4x1 MUX

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Working

Case 1: When S0=0 and S1=0 then upper AND gate has I/Ps 1, 1, I0. AND gate multiples them and gives O/P
I0. All other AND gate give O/P 0.

Case 2: When S0=0 and S1=1 then second AND gate has I/Ps 1, 1, I1. AND gate multiples them and gives
O/P I1. All other AND gate give O/P 0.

Case 4: When S0=1 and S1=1 then last AND gate has I/Ps 1, 1, I3. AND gate multiples them and gives O/P
I3. All other AND gate give O/P 0.

Design 8x1 MUX and explain its working with truth table. Do it yourself in subject copy

Design 16x1 MUX and explain its working with truth table. Do it yourself in subject copy

[7]. Demultiplexer

A De-multiplexer(DMUX) is opposite of multiplexer. It has single input, n selection lines and 2n output
lines. It passes the I/P in one O/P line among 2n O/P lines. It is also called as “Data Distributor”.

There are following types of D-MUX.

(i) 1x2 D-MUX (ii) 1x4 D-MUX (iii) 1x8 D-MUX (iv) 1x16 D-MUX

Note:

In 1x2 D-MUX  inputs = one Selection lines=1 O/Ps = 2

In 1x4 D-MUX  inputs = one Selection lines=2 O/Ps = 4
In 1x8 D-MUX  inputs = one Selection lines=3 O/Ps = 8
In 1x16 D-MUX  inputs = one Selection lines=4 O/Ps = 16

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2x1 D-MUX

A 1x2 D-MUX has only one input, one selection line and 2 O/Ps. Its circuit diagram and truth table is
shown below:

It has ONE input I0. S0 is selection line.

Working

Case1: When S0=0 then upper AND gate has I/Ps I0 and 1. AND gate multiples them and gives O/P I0 from
O/P line O0 , hence O0 = I0. The lower AND gate has I/Ps I0 and 0 so lower AND gate gives O/P 0. The OR
gate add these I/Ps I0 and 0.

Case2: When S0=1 then upper AND gate has I/Ps I0 and 0. AND gate multiples them and gives O/P 0. The
lower AND gate has I/Ps I0 and 1 so lower AND gate gives O/P I0 from O/P line O1, hence O1 = I0 .

4x1 D-MUX

A 1x4 D-MUX has only one input, 2 selection line (S0 and S1) and four O/Ps (O0, O1, O2, O3,). Its block
diagram, circuit diagram and truth table is shown below:

Working

Case 1: When S0=0 and S1=0 then upper AND gate has I/Ps 1, 1, I0. AND gate multiples them and gives
O/P I0. So we get O/P from line O0. All other AND gate give O/P 0.

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Case 2: When S0=0 and S1=1 then second AND gate has I/Ps 1, 1, I0. AND gate multiples them and gives
O/P I1. So we get O/P from line O1. All other AND gate give O/P 0.

Case 4: When S0=1 and S1=1 then last AND gate has I/Ps 1, 1, I3. AND gate multiples them and gives O/P
I3. So we get O/P from line O3. All other AND gate give O/P 0.

Design 1x8 MUX and explain its working with truth table. Do it yourself in subject copy

Design 1x16 MUX and explain its working with truth table. Do it yourself in subject copy

[8]. Encoder

An encoder is a digital circuit that performs the inverse operation of a decoder. It converts information into
Binary number system. An encoder has 2n (or fewer) input lines and n output lines. Example of an encoder is
the octal-to-binary encoder whose truth table and circuit diagram are given below. It has 8 I/Ps and 3 O/Ps.

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Working: ( by students)

Decimal to Binary Encoder

A Decimal to Binary Encoder converts decimal I/P into Binary O/P. It has 10 I/Ps and 4 O/Ps. Its circuit
diagram and truth table is given below:

for working and truth table by students.

[9]. Decoder

A Decoder is a combinational circuit. It coverts (or decode) binary number into another number system. It
has n inputs and 2n outputs.

The types of Decoder are:

(i) 2x4 line decoder

(ii) 3x8 line decoder (Binary to Octal Decoder)
(iii) 4x16 line decoder

2x4 Decoder

A 2x4 Decoder has 2 inputs (A and B) and 4 O/Ps (D0, D1, D2, D3). Its circuit diagram and truth table is
shown below:

I/P O/P
A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

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Working

Case 1: When A=0 and B=0 then upper AND gate has I/Ps 1, 1. AND gate multiples them and gives O/P 1.
So we get O/P from line D0. All other AND gate give O/P 0.

Case 2: When A=0 and B=1 then second AND gate has I/Ps 1, 1. AND gate multiples them and gives O/P
1. So we get O/P from line D1. All other AND gate give O/P 0.

Case 4: When A=1 and B=1 then last AND gate has I/Ps 1, 1. AND gate multiples them and gives O/P 1. So
we get O/P from line D3. All other AND gate give O/P 0.

Binary to Octal Decoder (3x8 Decoder)

It has 3 inputs (A, B and C) and has 8 O/Ps (D0, D1………D7). It takes binary input and gives Octal o/p. Its
circuit diagram and truth table is shown below:

Working

Case 1: When A=0, B=0, C=0 then upper AND gate has I/Ps 1,1,1. This AND gate multiples them and gives
O/P 1. So we get O/P from line D0. All other AND gate give O/P 0.

It shows that when we apply 0000(Binary 0) then we get O/P from D0 (0 in Octal)

Case 2: When A=0, B=0, C=1 then second AND gate has I/Ps 1,1,1. This AND gate multiples them and
gives O/P 1. So we get O/P from line D1 All other AND gate give O/P 0.

It shows that when we apply 001(Binary 1) then we get O/P from D0 (1 in Octal)

Case 3: When A=0, B=1, C=0 then Third AND gate has I/Ps 1,1,1. This AND gate multiples them and gives
O/P 1. So we get O/P from line D2. All other AND gate give O/P 0.

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It shows that when we apply 010 then we get O/P from D2 (2 in Octal)

Case 7: When A=1, B=1, C=1 then last AND gate has I/Ps 1,1,1. This AND gate multiples them and gives
O/P 1. So we get O/P from line D7. All other AND gate give O/P 0. It shows that when we apply
111 then we get O/P from D0 (7 in Octal)

I/P O/P
A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Binary to Decimal Decoder (4x10 line Decoder)

It has 4 inputs (A, B, C and D) and has 10 O/Ps (D0, D1………D9). It takes binary input and gives Decimal o/p.
Its circuit diagram and truth table is shown below:

Working

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Case 1: When A=0, B=0, C=0, D=0 then upper AND gate has I/Ps 1,1,1,1. This AND gate multiples them
and gives O/P 1. So we get O/P from line D0. All other AND gate give O/P 0. It shows that when we
apply 0000(Binary 0) then we get O/P from D0 (0 in Decimal)

Case 2: When A=0, B=0, C=0, D=0 then second AND gate has I/Ps 1,1,1,1. This AND gate multiples them
and gives O/P 1. So we get O/P from line D1. All other AND gate give O/P 0. It shows that when we
apply 0001 then we get O/P from D1 (1 in Decimal)

Case 8: When A=1, B=0, C=0, D=0 then second AND gate has I/Ps 1,1,1,1. This AND gate multiples them
and gives O/P 1. So we get O/P from line D8. All other AND gate give O/P 0. It shows that when we
apply 1000 then we get O/P from D8 (8 in Decimal)

Case 9: When A=1, B=0, C=0, D=1 then second AND gate has I/Ps 1,1,1,1. This AND gate multiples them
and gives O/P 1. So we get O/P from line D9. All other AND gate give O/P 0. It shows that when we
apply 1001 then we get O/P from D9 (9 in Decimal)

I/P O/P
A B C D D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0 1 0 0 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 0 1 0 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0 0
1 0 0 0 0 0 0 0 0 0 0 0 1 0
1 0 0 1 0 0 0 0 0 0 0 0 0 1

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[10]. Implementation of combinational logic circuits.

Code Converters
In the previous study of codes, coding was defined as the use of groups of bits to represent items of information
that are multivalued. Assigning each item of information a unique combination of bits makes a transformation
of the original information. This we recognize as information being processed into another form. Moreover,
we have seen that there are many coding schemes exist. Different digital systems may use different coding
schemes.
It is sometimes necessary to use the output of one system as the input to other. Therefor a sort of code
conversion is necessary between the two systems to make them compatible for the same information. ‘A code
converter is a combinational logic circuit that changes data presented in one type of binary code to another
type of binary code.’ A general block diagram of a code converter is shown in Fig.

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To understand the design procedure; we will take a specific example of 4-bit Binary to Gray code
conversion.

1. The block diagram of a 4-bit binary to gray code converter is shown in Fig. 4.13.

If has four inputs (B3 B2 B1 B0) representing 4-bit binary numbers and four outputs (G3 G2 G1 G0)
representing 4-bit gray code.

2. Truth table for binary to gray code converters.

3. Now we solve all the gray outputs distantly with respect to binary inputs From the truth table; the logic
expressions for the gray code outputs can be written as

9, 10, 13, 14).

The above expressions can be simplified using K-map

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4. Now the above expressions can be implemented using X-OR gates to yield the desired code converter
circuit shown in Fig.

IMPLEMENTATION EXAMPLES OF COMBINATIONAL LOGIC DESIGN USING

MUX/DEMUX
The design procedure for combinational circuits using MUX are as follows:

STEP 1: Identify the decimal number corresponding to each minterm in the expression. The input lines
corresponding to these numbers are to be connected to logic 1 (high).

STEP 2 : All other input lines except that used in step 1 are to be connected to logic 0 (low).

STEP 3 : The control inputs are to be applied to select inputs.

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Example 1. Implement the following function with multiplexer.
Y = F (A, B, C, D) = Σm (0, 1, 3, 4, 8, 9, 15)
Solution.
STEP 1 : The input lines corresponding to each minterms (decimal number) are to be connected
to logic 1. Therefore input lines 0, 1, 3, 4, 8, 9, 15 have to be connected to logic 1.

STEP 2 : All other input lines except 0, 1, 3, 4, 8, 9, 15 are to be connected to logic 0.

STEP 3 : The control inputs A, B, C, D are to be applied to select inputs.

Example 2. Implement the following function with a 4×1 multiplexer.

Y = F (A, B, C) = Σm (1, 3, 5, 6)
Solution. Given Y = F (A, B, C) = Σm (1, 3, 5, 6)
= A'B'C + A'BC + AB'C + ABC'

We use the A and B variables as data select inputs. We can use the above equation to construct the table
shown in Fig. The residues are what is “left over” in each minterm when the “address” variables are taken
away.

Input “Address” Other variables (residues)

I0 A'B' C
I1 A'B C
I2 AB' C
I3 AB C'

To implement this circuit, we connect I0, I1 and I2 to C and I3 to _ as shown in Fig.

Example 3. Design a full adder using 8:1 multiplexer.

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Solution. The truth table of a full adder is given as
A B C S CF
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

S (A, B, C) = A'B'C + A'BC' + AB'C' + ABC = Σm( 1,2,4,7)

CF (A, B, C) = A'BC + AB'C + ABC' + ABC = Σm( 3,5,6,7)

The implementation for summation expression is

Step 1: The input lines corresponding to 1, 2, 4, 7 are to be connected to logic 1.
Step 2: Other input lines are to be connected to logic 0.
Step 3: Control inputs A, B, C are to be applied to select inputs. Fig. A.

Similarly for carry expression.

Step 1: The input lines corresponding to 3, 5, 6, 7 are to be connected to logic 1.
Step 2: Other input lines are to be connected to logic 0.
Step 3: Control inputs A, B, C are to be applied to select inputs. Fig. B.

Example 4. Implement a full adder with a decoder and two OR-gates.

Solution. From the previous example we note that expression for summation is given by
S (A, B, C) = Σm (1, 2, 4, 7)
and expression for carry is given by
CF (A, B, C) = Σm (3, 5, 6, 7)
The combinational logic of full adder can be implemented with due help of 3-line to 8- line decoder/1:8
demultiplexer as shown in Fig.

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Fig. Full adder implementation using 3 × 8 decoder

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