ES9023

Premier Stereo DAC with 2Vrms Driver

Analog Reinvented Datasheet

DNR Power Supply No DC-blocking Pop-Noise

Device Description Package
(dB) (Output Level) capacitor Free
Sabre Premier Stereo DAC +3.6V (2Vrms)
ES9023 112   16-SOP
with 2Vrms Op-Amp Driver +3.3V (1.9Vrms)

The ES9023 is a 24-bit stereo audio DAC with an integrated 2Vrms op-amp driver. Powered by the industry
proven Sabre DAC technology, the ES9023 combines best-sounding audio with lowest system cost and
highest performance into the ideal D/A converter for line-level output applications such as Blu-ray players,
CD / DVD players, set-top boxes, digital TVs and audio receivers.

With patented HyperStream® architecture and Time Domain Jitter Eliminator, the ES9023 delivers jitter-free
studio quality audio with 112dB DNR.

Using an integrated charge pump to generate the negative supply, the ES9023 can operate from a single
AVCC supply to drive a ground-referenced 2Vrms output, eliminating the need for output dc-blocking
capacitors. Optionally, the output level can be adjusted by using an external resistor, allowing for output
level below 2Vrms. Pop-noise is eliminated through a comprehensive suppression on power up/down,
mute, reset, loss of power or clock. Dedicated control/status pins allow easy system integration without the
need for microcontroller programming.

FEATURE BENEFIT
▪ Lowest system cost by minimizing external components
Sabre DAC and 2Vrms op-amp driver
▪ Highest performance
integration
▪ Best sounding audio – powered by Sabre DAC technology
Patented HyperStream® and Jitter ▪ Best dynamic range: 112dB
Elimination Architecture ▪ Immune to Clock Jitter
▪ Allow designer to customize output level (up to 2Vrms)
Adjustable output level
based on application requirements via an external resistor
Ground-referenced output ▪ Reduce cost by eliminating blocking capacitors

Pop-noise suppression ▪ Pop-free on power up/down, mute and reset

Dedicated control / status pins
▪ I2S or left-justified select ▪ Easy to use – no programming required
▪ Soft-mute enable
▪ Zero-detect output
Charge pump for negative supply ▪ Single AVCC simplifies power supply

Low power consumption in 16-SOP ▪ Simple power supply to reduce PCB size

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
 0.72 August 26, 2022

ES9023 Datasheet

FUNCTIONAL BLOCK DIAGRAM

Control/Status ES9023

BCK
2Vrms
LRCK PCM Oversampling Jitter HyperStream Op-Amp AOUTL
SDI Interface Filter Reduction DAC (2x) Driver AOUTR
(2x)
MCLK

Power Supply &

VEE
Charge Pump
AVSS
CN

AVDD
CP

APPLICATION DIAGRAM

Blu-Ray Player
AVCC

DVD Player Audio L

Audio Out
Processor (2Vrms)
ES9023 R

Home Theater Receiver

PC Pro-Audio Sound Card

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA Tel (408) 643-8800 •WWW.ESSTECH.COM 2
 August 26, 2022 0.72

ES9023 Datasheet

PIN LAYOUT

BCK 1 16 ZD
LRCK 2 15 MUTE_B
SDI 3 14 DGND
DIF 4 ES9023 13 MCLK
AVCC 5 16SOP 12 AGND
VREG 6 11 NEG
AOUTL 7 10 CN
AOUTR 8 9 CP

PIN DESCRIPTIONS
Pin # Name Type Pin Description
1 BCK I I2S Bit Clock
2 LRCK I I2S L/R (Word) Clock
3 SDI I I2S Serial Data Input
4 DIF I Input to select Left Justified or I2S data
5 AVCC P AVCC Power supply
6 VREG P Analog Reference Output
7 AOUTL O Left Analog Output
8 AOUTR O Right Analog Output
9 CP I Positive Terminal of External Charge Pump Capacitor
10 CN I Negative Terminal of External Charge Pump Capacitor
11 NEG P Negative Power Supply (Internally Generated)
12 AGND GND Analog Ground
13 MCLK I Master (System) Clock
14 DGND GND Digital Ground
15 MUTE_B I Active Low Mute Input
16 ZD O Zero Detect Output

3 ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95035, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
 0.72 August 26, 2022

ES9023 Datasheet

FUNCTIONAL DESCRIPTION
I2S Decoder
Run by the I2S bit clock, typically a 64 x FS clock, the I2S Decoder translates the incoming I2S data to 24-bit signed PCM data.
If a smaller bit-width is used, the remaining is ‘zero-padded’. Driving the DIF pin low will set the DAC in I2S mode while
driving the pin high will set the DAC in LJ mode. Below is a timing diagram illustrating the two modes (LJ and I 2S) utilized by
the ES9023.

Zero Detect
The zero-detect function outputs an external status signal (ZD) based on a zero-valued input for a given number of clock
cycles. The ZD output signal is set high when both data channels are zero for 8192 LRCK cycles.

MCLK
Asynchronous mode: MCLK must be > 192 x fs.
Synchronous mode: Please see table below for supported configurations.

LRCK (kHz) MCLK (MHz)

fs 128 x fs 192 x fs 256 x fs 384 x fs 512 x fs 768 x fs 1152 x fs
32 - - - 12.288 16.384 24.576 36.864
44.1 - - 11.2896 16.9344 22.5792 33.8688 -
48 - - 12.288 18.432 24.576 36.864 -
88.2 11.2896 16.9344 22.5792 33.8688 45.1584 - -
96 12.288 18.432 24.576 36.864 49.152 - -
176.4 22.5792 33.8688 45.1584 - - - -
192 24.576 36.864 49.152 - - - -

For best performance, 256 x fs or greater is recommended for 32kHz to 96kHz sampling.

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA Tel (408) 643-8800 •WWW.ESSTECH.COM 4
 August 26, 2022 0.72

ES9023 Datasheet

MUTE_B Pin (Active Low)

This input pin provides the ability to slowly ramp down the audio volume, and then enter low power standby. Release of mute
will cause the ES9023 to emerge from low power mode and then slowly ramp the audio to provide a pop free startup.

MUTE_B

25600 / fs 32768 / MCLK 49512 / fs

(Internal) 0dB
Attenuation

-
Power up delay
(Internal)
Power Down

AOUT

Activation/release of the MUTE_B input pin initiates a sequence of internal events detailed below:
• On assertion of the MUTE_B pin:
o The output signal will ramp to the - level. The ramping takes 25600 / fs seconds, where fs = sampling rate in Hz.
o After the output signal reaches the - level, analog section is turned off and the ES9023 enters a low power standby
state.
• On release of the MUTE_B pin:
o The ES9023 emerges from low power standby, starts an internal counter and activates the analog section
o During the delay counter time, the internal charge pump and Vref stabilize.
o When the counter reaches 32768 MCLK cycles, the audio signal is applied and the volume is ramped over 49512 / fs
seconds to maximum, where fs = sampling rate in Hz.

To minimize pop noise at power up, an external circuit should be used to hold the MUTE_B pin asserted until tDMUTE (see
p.10) after the power supply and MCLK are stabilized.
• This can be realized using a reset IC, an MCU GPIO pin (default to low at power-up and changed to high by software
later), or an RC time delay on this pin.
• If MUTE_B pin is released too early, pop noise may occur due to the ramp-up of internal voltage.
~
~

AVCC
~
~

MCLK
Same time as AVCC or later
tDMUTE

MUTE_B
Assert MUTE_B until tDMUTE after
the power supply and MCLK are
stabilized
5 ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95035, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
 0.72 August 26, 2022

ES9023 Datasheet

DAC / OP-AMP
Each HyperStream® DAC is followed by an op-amp circuit for each channel. A pop suppression circuit is added on the
output to eliminate any “pop” noise that may be heard during muting, un-muting, power-up and power-down sequences. In
some conditions, pop noise may be audible. See the MUTE_B pin section above.

Charge Pump (Negative Voltage Generation)

This is an analog circuit required to generate an internal negative supply. With positive and negative supplies, the op-amp
circuits will be able to generate a ground-referenced 2Vrms output.

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA Tel (408) 643-8800 •WWW.ESSTECH.COM 6
August 26, 2022 0.72

ES9023 Datasheet

APPLICATION DIAGRAM

100k

2.2uF

ES9023
10uF

GND

R8: see p.9 for more details.

7 ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95035, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
 0.72 August 26, 2022

ES9023 Datasheet

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

PARAMETER RATING
Storage temperature –65°C to +105°C
Voltage range for 5V tolerant pins –0.5V to +5.5V
Voltage range for all other pins –0.5V to (AVCC+ 0.5V)

WARNING: Stress beyond those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions section of this
specification is not implied. Exposure to the Absolute Maximum Ratings conditions for extended periods may affect device reliability.
WARNING: Electrostatic Discharge (ESD) can damage this device. Proper procedures must be followed to avoid ESD when handling this device.

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL CONDITIONS

Operating temperature TA 0°C to 70°C
+3.6V ±5%, 31mA nominal (Note 1), or
Power supply voltage AVCC
+3.3V ±5%, 23mA nominal (Note 1)
Note
1) fs = 48kHz, MCLK = 27MHz, I2S input, output unloaded

DC ELECTRICAL CHARACTERISTICS
Table 1 DC Electrical Characteristics

SYMBOL PARAMETER MIN MAX UNIT COMMENTS

All inputs TTL levels except CLK
2 AVCC V
VIH High-level input voltage and 5V tolerant input pins
2 5.5 V All 5V tolerant inputs
VIL Low-level input voltage –0.3 0.8 V All input TTL levels except CLK
VCLKH CLK high-level input 2 AVCC+ 0.25 V
TTL level input
VCLKL CLK low-level input –0.3 0.8 V
VOH High-level output voltage 3 V IOH = 1mA
VOL Low-level-output voltage 0.45 V IOL = 4mA
ILI Input leakage current 15
A
ILO Output leakage current 15
CIN Input capacitance 10
pF fc = 1MHz
CO Input/output capacitance 12
CCLK CLK capacitance 20 pF fc = 1MHz

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA Tel (408) 643-8800 •WWW.ESSTECH.COM 8
 August 26, 2022 0.72

ES9023 Datasheet

MCLK Timing
tMCH

MCLK
tMCL
tMCY

Parameter Symbol Min Max Unit

MCLK pulse width high TMCH 9 ns
MCLK pulse width low TMCL 9 ns
MCLK cycle time TMCY 20 ns
MCLK duty cycle 45:55 55:45

Audio Interface Timing

tDCH

BCK
DATACLK
tDCL
tDCY
tDH tDS

SDI/LRCK
DATA[8:1] Valid Invalid Invalid

Parameter Symbol Min Max Unit

BCK pulse width high tDCH 20 ns
BCK pulse width low tDCL 20 ns
BCK cycle time tDCY 44 ns
BCK duty cycle 45:55 55:45
SDI/LRCK set-up time to BCK rising edge tDS 2 ns
SDI/LRCK hold time to BCK rising edge tDH 2 ns

9 ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95035, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
 0.72 August 26, 2022

ES9023 Datasheet

ANALOG PERFORMANCE
Test Conditions (unless otherwise stated)
1. TA = 25oC, AVCC = +3.6V, fs = 44.1kHz, MCLK = 27MHz, 24-bit data, RL  10k, Signal Frequency = 1kHz
2. SNR / DNR: A-weighted over 20Hz-22kHz in averaging mode
3. THD+N: un-weighted over 20Hz-22kHz bandwidth

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

PCM sampling rate fS 200 kHz
Mute Delay tDMUTE 500 ms
DYNAMIC PERFORMANCE
DNR (A-weighted) –60dBFS 112 dB-A
0dBFS 0.002 0.006 %
THD+N
–3dBFS 0.005 %
Interchannel Isolation 100 dB
DC Accuracy
Absolute DC Offset <4 mV
0dBFS, AVCC = +3.6V, R8 = 130k 2.0 Vrms
Output Voltage VO
0dBFS, AVCC = +3.3V, R8 = 220k 1.9 Vrms
Load Resistance RL 5 k
Digital Filter Performance
0.005dB 0.454fs Hz
Pass band
–3dB 0.49fs Hz
Stop band < –115dB 0.546fs Hz
Group Delay 35 / fs s

AVCC=3.6V AVCC=3.3V

VO (Vrms) VO (Vrms)

RC =  RC = 
2.2 2
1.9V
2V

1.8 R8 (k) 1.6 R8 (k)

Select R8 130k for no clipping Select R8  220k for no clipping

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA Tel (408) 643-8800 •WWW.ESSTECH.COM 10
 August 26, 2022 0.72

ES9023 Datasheet

16-Pin SOP Mechanical Dimensions

The solder paste and PCB finish/plating must be 100% lead-free in order to ensure proper solderability.

11 ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95035, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
 0.72 August 26, 2022

ES9023 Datasheet

Reflow Process Considerations

For lead-free soldering, the characterization and optimization of the reflow process is the most important factor you need to
consider.
The lead-free alloy solder has a melting point of 217°C. This alloy requires a minimum reflow temperature of 235°C to
ensure good wetting. The maximum reflow temperature is in the 245°C to 260°C range, depending on the package size
(Table RPC-2). This narrows the process window for lead-free soldering to 10°C to 20°C.
The increase in peak reflow temperature in combination with the narrow process window makes the development of an
optimal reflow profile a critical factor for ensuring a successful lead-free assembly process. The major factors contributing to
the development of an optimal thermal profile are the size and weight of the assembly, the density of the components, the
mix of large and small components, and the paste chemistry being used.
Reflow profiling needs to be performed by attaching calibrated thermocouples well adhered to the device as well as other
critical locations on the board to ensure that all components are heated to temperatures above the minimum reflow
temperatures and that smaller components do not exceed the maximum temperature limits (Table RPC-2).

To ensure that all packages can be successfully and reliably assembled, the reflow profiles studied and recommended by
ESS are based on the JEDEC/IPC standard J-STD-020 revision D.1.

Figure RPC-1. IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1)

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA Tel (408) 643-8800 •WWW.ESSTECH.COM 12
 August 26, 2022 0.72

ES9023 Datasheet

Table RPC-1 Classification reflow profile

Profile Feature Pb-Free Assembly

Preheat/Soak
Temperature Min (Tsmin) 150°C
Temperature Max (Tsmax) 200°C
Time (ts) from (Tsmin to Tsmax) 60-120 seconds
Ramp-up rate (TL to Tp) 3°C / second max.
Liquidous temperature (TL) 217°C
Time (tL) maintained above TL 60-150 seconds
For users Tp must not exceed the Classification
Peak package body temperature (Tp) temperature in Table RPC-2.
For suppliers Tp must equal or exceed the Classification
temperature in Table RPC-2.
Time (tp)* within 5°C of the specified classification
temperature (Tc), see Figure RPC-1 30* seconds
Ramp-down rate (Tp to TL) °C / second max.
Time 25 °C to peak temperature 8 minutes max.
* Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum.

Note 1: All temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly reflow (e.g., live-bug).
If parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e., dead-bug), Tp shall be within ±2°C of the live-bug Tp and still
meet the Tc requirements, otherwise, the profile shall be adjusted to achieve the latter. To accurately measure actual peak package body
temperatures refer to JEP140 for recommended thermocouple use.
Note 2: Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles. Actual board assembly
profiles should be developed based on specific process needs and board designs and should not exceed the parameters in Table RPC-1.
For example, if Tc is 260°C and time tp is 30 seconds, this means the following for the supplier and the user.
For a supplier: The peak temperature must be at least 260°C. The time above 255°C must be at least 30 seconds.
For a user: The peak temperature must not exceed 260°C. The time above 255°C must not exceed 30 seconds.
Note 3: All components in the test load shall meet the classification profile requirements.

Table RPC-2 Pb-Free Process – Classification Temperatures (Tc)

Package Thickness Volume mm3, <350 Volume mm3, 350 to 2000 Volume mm3, >2000
<1.6 mm 260°C 260°C 260°C
1.6 mm – 2.5 mm 260°C 250°C 245°C
>2.5 mm 250°C 245°C 245°C

Note 1: At the discretion of the device manufacturer, but not the board assembler/user, the maximum peak package body temperature (Tp) can exceed the
values specified in Table RPC-2. The use of a higher Tp does not change the classification temperature (Tc).
Note 2: Package volume excludes external terminals (e.g., balls, bumps, lands, leads) and/or non-integral heat sinks.
Note 3: The maximum component temperature reached during reflow depends on package thickness and volume. The use of convection reflow processes
reduces the thermal gradients between packages. However, thermal gradients due to differences in thermal mass of SMD packages may still exist.

13 ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95035, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
 0.72 August 26, 2022

ES9023 Datasheet

ORDERING INFORMATION
Part Number Description Package
ES9023P Sabre Premier Stereo DAC with 2Vrms Driver 16-SOP
The letter P at the end of the part number identifies the package type SOP.

REVISION HISTORY
Revision Date Notes
0.1 September 17, 2010 Initial version
0.2 November 3, 2010 Update Application Diagram
0.4 October 29, 2013 Update MUTE timing
0.5 July 22, 2014 Updated ESS’ FAX number. Added medical liabilities disclaimer
0.6 January 22, 2015 Cleaned up formatting and corrected typos
0.7 February 18, 2015 Corrected filter formulae in the Analog Performance table
0.71 April 6, 2015 Updated HQ address and phone number
0.72 August 26, 2022 Updated HQ address

ESS IC's are not intended, authorized, or warranted for use as components in military applications, medical devices or life support systems. ESS
assumes no liability whatsoever and disclaims any expressed, implied or statutory warranty for use of ESS IC's in such unsuitable applications.

No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic,
mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no
representations or warranties regarding the content of this document. All specifications are subject to change without prior notice. ESS Technology,
Inc. assumes no responsibility for any errors contained herein. U.S. patents pending.

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA Tel (408) 643-8800 •WWW.ESSTECH.COM 14