HO CHI MINH UNIVERSITY OF TECHNOLOGY
FACULTY OF COMPUTER SCIENCE & ENGINEERING
LAB 3
DIGITAL SYSTEM
GROUP: 1
MENTOR: Ton Huynh Long
Students:
Full Name ID
Vũ Lê Hoàng 2452365
Bùi Trần Quyền 2353033
11/2024
Preparation for upcoming lab:
1. Exc 1: Implement DFF from J-K FF
Logic: When J and K is different, Q=J, thus we can
implement the circuit where J=D and K=D’.
Circuit design:
Simulation:
1
Netlist:
Wire no. 1st end 2nd end
1 5V Pin 14 of U1
2 GND Pin 7 of U1
3 5V Pin 4 of U2
4 GND Pin 11 of U2
5 SW0 Pin 13 of U1
6 SW0 Pin 14 of U2
7 Pin 12 of U1 Pin 4 of U2
8 Pin 1 of U2 CLK1
9 Pin 2 of U2 SW1
10 Pin 12 of U2 LED0
2. Exc 2:
Circuit design:
Simulation:
2
Netlist:
Wire no. 1st end 2nd end
1 5V Pin 14 of U1
2 GND Pin 7 of U1
3 5V Pin 14 of U2
4 GND Pin 7 of U2
5 SW0 Pin 1 of U1
6 SW1 Pin 4 of U1
7 SW2 Pin 13 of U1
8 SW3 Pin 10 of U1
9 SW4 Pin 13 of U2
10 SW5 Pin 10 of U2
3
11 CLK Pin 3 of U1
12 Pin 2 of U1 Pin 6 of U1
13 Pin 5 of U1 Pin 11 of U1
14 Pin 12 of U1 Pin 8 of U1
15 Pin 9 of U1 Pin 11 of U2
16 Pin 12 of U2 Pin 8 of U2
17 LED0 Pin 5 of U1
18 LED1 Pin 8 of U1
19 LED2 Pin 8 of U2
a. We can see that the output (LED) connected to the D
Flip Flop displays half the freq of the corresponding
clock. This makes QA, QB, QC (left to right) in turn
having output freq of ½, ¼, and 1/8 compared to the
clock. If we observing this as a binary string, (with QA
as the LSB), it displaying alll the 3-bits in increasing
order (from 000 to 111).
b. Now that we obtain the logic here, we need to chain the
forth D Flip-Flop so as to have the output freq that is 16
times less than the clock
4
3. Exc 3 (Advance)
a. Design:
Simulation:
5
b. Solving the time diagram for A,B and z
