Cadence

®
Allegro PCB Power Integrity Analysis

(Allegro PCB PI 610 Option)

Jean-
Jean-Michel SAINSON CERN IT − DES/ETS
Engineering Tools Services
September 2005

1 Cadence Allegro® PCB Power Integrity − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −

Need for Power Integrity Analysis Tools

Modern CMOS technology with unreliable Power Delivery System
can be the cause of
 Numerous prototype iterations
 Low production yield
 Impossibility to reach LSB in mixed A/D boards
 High errors rate
 System crash
 Temperature dependant errors
 Power supply dependant errors
 Hot spot increasing common mode EMI

How PDS are done today

 Mainly based on habits and/or experience (any simulation)
 With help of rules of thumbs published by FPGA and A/D ICs manufacturers
 Over design adding more decoupling capacitors than necessary is a consequence
 Bad decoupling capacitors placement, characteristics and number can create more
problems than it is supposed to solve (anti-resonances)

The Cadence approach

 Allow users to determine the needs of the Power Delivery System
 Target impedance (ZTARGET)
 Decoupling capacitor requirements
 Provide frequency domain analysis to find problem areas
 Provide an integrated PCB design editor to optimize capacitor placement

2 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −
 Need for Power Integrity Analysis Tools

Main origin of power supply noise
 Parasitic elements in the PWR/GND supply path cause power supply
noise fluctuation on the chip supply rail

∆V = Leff ( dI )
dt
Power plane spreading
Simplified model
inductance

3 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −

Allegro PI Principles
(Components in a PDS)

Components in a Power Delivery

System
 Voltage Regulator Module (VRM)
 Effective up to 1 KHz
 Electrolytic (bulk) capacitors
 Supply current and maintain a VRM
low PDS impedance from
1kHz to 1 MHz
 Ceramic Capacitors
 High frequency ceramic
capacitors maintain the PDS
impedance from 1 MHz to
several hundred MHz
 Powerplane Pairs
 The interplane capacitance
and the impedance of the
PCB power planes are
important above 100 MHz
Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology
Larry Smith SUN Microsystems, Inc.

4 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −
 Allegro PI Principle (ZTarget)

Target impedance (Z
(ZTARGET)
 The key to a Power Delivery System is the target impedance
 Given power supply voltage and power consumption, current is calculated using
Ohm’s law.

ZTarget = (Power Supply Voltage) x (Ripple Tolerance)

Maximum Delta Current
 Acceptable voltage ripple must be defined (typically 5%)
 Ex: 5% ripple in a 1.8V system means the swing can not be more than
0.09V?
 Delta current refers to the maximum change in current consumption that can
occur
 Maximum current is the maximum dynamic current plus static current
 Maximum delta current is the maximum change in maximum current
 Maximum delta current = sum of delta current of all devices connected
to the same power and ground system. Usually delta current is 20-40%
of maximum current. 50% would be a safe worst-case assumption for
maximum delta current.

5 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −

Allegro PI Principle
(ZTARGET Vs Technology Generations)
Year Voltage Power Current Ztarget Frequency

Power delivery requirement for (Volts) (Watts) (Amps) (m-Ohms) (MHz)
modern high-
high-speed system 1990 5 5 1 250 16
1993 3.3 10 3 54 66
 Each CMOS generation is scaled to
give smaller and faster transistor 1996 2.5 30 12 10 200
(Moore low) 1999 1.8 90 50 1.8 600
2002 1.2 180 150 0.4 1200
 Voltage supply decrease:
5V →1.2V
 Current requirement increase: PDS Impedance
1A →150A
1999 Target Impedance
 Clock rates rise and more function 1.8 m Ohms
is integrated into micro processors
and ASICs / FPGAs etc.., power
2002 Target Impedance
consumed increase 0.4 m Ohms
 Target impedance is dropping by a
factor of five every computer
generation

1 Hz 1 KHz 1 MHz 1 GHz

Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology
Larry Smith SUN Microsystems, Inc.

6 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −
 Allegro PI Principle
(ZTARGET & Frequency of Interest)
Interest)

Frequency of interest should be able to handle all possible current

current
transient frequencies
 In the kHz range for low-frequency (sub-millisecond) activities (e.g. µP-to-disk activity
 MHz range for µP to DRAM clock activity
 GHz range at harmonics of the fastest edges of System Clock frequency
 Equivalent bandwidth of a digital signal expression define the highest frequency

Equivalent bandwidth of a digital signal with switching time (tr):

(tr):

F = 1 ≈ 0.32
Π tr tr
 F = 640 MHz for Xilinx Virtex LVCMOS (trmin ≈ 0.5 ns)
 F = 1.6 Ghz for CML SERDES Output (trmin ≈ 0.2 ns)

7 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −

Allegro PI Workflow

Main Allegro PI workflow phases

 Set up the board database for power integrity analysis

(including decoupling capacitors selection)

 Define the target impedance by specifying simulations parameters such as

powerplane voltage rails, ripple tolerance and the worst-case dynamic current

 With this information Allegro PI recommends (compute) the number of capacitors

needed to maintain a target impedance

 Run a single-node simulation to validate whether the number of capacitors that you
chose can maintain the target impedance over the frequency band. Although decoupling
capacitors are considered in single-node simulations, their placement is not.
Using an ideal simulation like this gives an idea of how good capacitor selection is.

 Finally Multi-node simulation refine capacitors placement in the board layout through
Spice sub-circuit extraction from multiple point on the board. Multi-node simulation
considers decoupling capacitor placement as well a noise source placement.
Powerplane analysis is performed in real conditions..

8 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −
 Preparing for Powerplane Anaysis

Allegro PI capacitor library setup
Capacitor family “npo_1206”

The height of this vertical

mark represents the
capacitor’s ESR at
resonance frequency when
jlω = 1/jcω
See Appendix

9 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −

Preparing for Powerplane Analysis

Capacitor Inductance
Allegro PI decoupling capacitor editor
 Is mostly in the pad and via structure
 Inductance is minimized by minimizing
the era of the current loop

Compute intrinsic
inductance with capacitor
thickness

Capacitor Pad Design Progression
 Pad layout is a major contributor to Compute mounted
capacitor inductance inductance with
powerplane pair,
package and board side
on which to mount the
Earlier design
Earlier design
capacitor.
95 design Mounted inductance is
95 design
Henry

96 design done automatically at

microHenry

96 design
component placement
97 design
97 design
time.
micro

2000 design
2000 design
Current design
Current design

Years
Years
Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology Larry Smith SUN Microsystems, Inc.

10 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −
 Preparing for Powerplane Analysis

VRM schematic
Allegro PI Voltage Regulator Module
editor
VRM PI 4 elements
SPICE model

VRM PI 4 Elements
SPICE Model

11 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −

Allegro PI Design and Analysis

Design and analysis dialog box

Power plane pair

Ripple tolerance

Max delta current

Target impedance

PI tool uses capacitors

selected during library
setup to compute an
initial estimate of the
number of capacitors
required

Single node simulation

Multi node simulation

12 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −
 Allegro PI Design and Analysis
Single-
Single-node

Single-
Single-Node simulation equivalent circuit

1 Amp
AC Current
Source

VRM + plane-pair

Single-
Single-Node simulation
Impedance [Ohms]

Without Caps

With Caps VRM + plane-pair

+ capacitors

Frequency [Hz]

13 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −

Allegro PI Design and Analysis

Multi-node

Multi-
Multi-node grid size with 8x8 meshing
 Cadence PI tool uses a mesh technique to model the parallel plane structure (not field solution).
 The granularity of the mesh is defined by the user
 For greatest accuracy, the size of the mesh should be a maximum of one tenth the wavelength
of the highest frequency of interest define in slide 7
 Ex: 1 GHz on FR4 equivalent wavelength would be: 150 mm
 One-tenth is 15mm per square. You ideally want a mesh of about 20x20 for a board whose size
is 300mm x 300mm
The trans-impedance value for
each node in the mesh represents
the frequency-dependent PDS
impedance

Granularity of the mesh is

defined by the user

Power Plane SPICE Models and Simulated Performance for Materials and Geometries
Larry Smith, Raymond Anderson, Tammoy Roy, Sun Microsystems, Inc.
IEEE Transaction on Advanced Packaging August 2001

14 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −
 Allegro PI Design and Analysis
Multi-node

Noise sources placement

Noise sources placed in the

board layout

VRM placement

VRM in the board

layout

15 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −

Allegro PI Design and Analysis

Multi-node

Decoupling capacitors placement
 As you place decoupling capacitors, an enveloping circle represents its
effective radius.
 This radius is based on a fraction of the resonant frequency’s wavelength for
the decoupling capacitor.
 This help to determine how close to place high frequency capacitor to
noise sources.
Effective radius of the selected
capacitor. This radius
represents 1/200 the actual
wavelength of the capacitor’s
resonant frequency.

16 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −
 Allegro PI Design and Analysis
Multi-node

Cross-
Cross-probing (grid location view)
 100 MHz PCI Interface Card
 Post-Layout analysis Grid size of this plane structure
Designed board without Allegro is selected to yield small
PI analysis squares as highlighted towards
(Post-Layout Analysis) the left, inside the red oval

Using Allegro PCB SI to Analyse a Board’s Power Delivery System from Power Source to Die Pad
International; cadence User group Conference September 15 – 17, 2003 Jurgen Flamm, Cadence

®
17 Cadence Allegro PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −

Allegro PI Design and Analysis

Multi-node

Cross-
Cross-probing (impedance curve view)
 Each curve of the family of plotted curves represents the frequency
dependent source impedance of each grid location

Using Allegro PCB SI to Analyse a Board’s Power Delivery System from Power Source to Die Pad
International; cadence User group Conference September 15 – 17, 2003 Jurgen Flamm, Cadence

18 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −
 Allegro PI Analysis
Conclusion 1/2

Capacitor libraries management issues
 Allegro PCB PI option 610 (aka SQPI) includes capacitor models for over 700 different
devices
 TDK and Murata offer capacitor models that can be used in Allegro PI
 Murata components library for Allegro PI (March 2006) contains equivalent
circuit models of 1294 items of Murata monolithic ceramic capacitor
http://www.murata.com/designlib/sqlib/index.html
 TDK capacitor equivalent model for Allegro PI (March 2001)
http://www.component.tdk.com/tvcl_specctra.php
 Allegro PI gives you the ability to create your own capacitor models when
vendors models are not available.

Only few users in HEP community

 INFN (I) Padova for AGATA application
 CPPM / IN2P3 (F) for LHCb muon processor development
 Other IN2P3 sites?
 Evaluation on existing A/D boards considered at CERN (February 2006)

19 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −

Allegro PI Analysis
Conclusion 2/2
Layout
Designer
Designer
Allegro PI Option
Ztarget
Board outline and
Frequency of Interest

Allegro PI Workflow Stackup
design
and
Grid Size definition

 A well defined workflow Allegro PCB SI Single-node

Simulation
should help Designers to Decoupling
Capacitors Type and
try Allegro PI analysis on Number selection

their new boards

 Clear board design Allegro PI Option NOK
Single Node
Simulation
expertises sharing Component and
OK
between Layout VRM
Placement
Designer and Designer

Noise source
Placement

Allegro PI Option

Multi-node
Decoupling
Capacitors Placement Simulation

Multi Node
NOK Simulation

OK

Allegro PI Option

20 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −
 Appendix 1: Decoupling Capacitor Behaviour

Low Frequency (Bulk) Decoupling
High Frequency Decoupling Capacitor
Capacitor Impedance Profile Impedance Profile
 C1 = C2 but Cap2 has less inductance

Inductive
effect

Capacitive
effect

Effective Series Resistor

(ESR) at resonant
frequencies

 The fact that decoupling capacitors are maximally effective at their resonant
frequency and less effective at all other frequencies is a fundamental and critical
important concept

21 Cadence Allegro® PCB Power Integrity Analysis − Ecole d’Electronique Numérique IN2P3 Roscoff 2006 −