eZ80Acclaim!

® Flash Microcontrollers

eZ80F91 MCU

Product Specification
PS019217-1222

Copyright ©2022 by Zilog®, Inc. All rights reserved.

www.zilog.com
 eZ80F91 MCU
Product Specification

DO NOT USE IN LIFE SUPPORT

Warning:
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.

As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.

Document Disclaimer
©2022 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
Z I L O G A L S O D O E S N O T A S S U M E L I A B I L I T Y F O R I N T E L L E C T U A L P R O P E RT Y
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this
document has been verified according to the general principles of electrical and mechanical engineering.

eZ80, Z80, and eZ80Acclaim! are registered trademarks of Zilog, Inc. All other product or service names
are the property of their respective owners.

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 eZ80F91 MCU
Product Specification

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Revision History
Each instance in the Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages or appropriate links given in
the table below.

Revision Page
Date Level Section Description Number
December 17 Ordering Information Removed PSI’s for MCU’s, kits, 359, 359
2022 modules, and cables that are no
longer supported. Added Acclaim!
Smart Cable. Updated Environmental
flow to “K”.
Updated title page and headers to All
Littelfuse branding
March 16 Chapter 12. Real Time Added clarification about leap year 159
2016 Clock; All compensation when BCD operation is
enabled; updated Zilog logo on title
page and in header.
September 15 All Updated logos and copyright date. All
2010
August 14 Ordering Information Updated Part Number Description 359
2008 section.
May 2008 13 Introduction, Figure 48, ZDI- Replaced ZPAK II with USB Smart 231, 232,
Supported Protocol, and Cable and 233
Figure 49
September 12 General-Purpose Input/ Updated Table 1, Figure 6, Flash 4, 53,
2007 Output, Flash Memory, Program Control Register, UART 112,174,
Universal Asynchronous Transmitter, Figure 40, Table 93, I2C 176, 201,
Receiver/Transmitter, Serial Registers and Ordering Information. 223, and 358
Peripheral Interface, Real-
Time Clock Control Register,
I2C Serial I/O Interface, Pin
Description, and Ordering
Information.
February 11 Register Map, GPIO Mode 7—Alternate Functions, Register Map - 27, 45, 54,
2007 Table 3. Low-Power Modes, Electrical Characteristics chapters. 339
Updated Table 93.

PS019217-1222 Revision History

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Revision Page
Date Level Section Description Number
June 2006 10 Global modifications Updated for new release. All
Pin Identification on the Table 3: The description of the 6
eZ80F91 Device following pins modified: pins 55, 61,
63 and 69
General-Purpose Input/ GPIO chapter totally rewritten 49
Output
Chip Selects and Wait Input/Output chip select operation 65
States modified
Flash Memory The following sections are modified in 97
Flash memory chapter: Erasing Flash
memory, Information page
characteristics, Flash Write/Erase
protection register, Flash program
control registers, and Table 43.
Real-Time Clock Overview Added a note in real time clock 159
overview section
Universal Asynchronous Table 102 and 109 modified 175
Receiver/Transmitter
Infrared Encoder/Decoder The field [7:4] modified in Table 111 199
Control Registers
Zilog Debug Interface Updated the Introduction section, 231
Added two paragraphs to ZDI Read
Memory Registers
On-Chip Oscillators On page 349, Figure 63: 336
Recommended Crystal Oscillator
Configuration, the value of inductance
L is changed to 3.3 μH.
On page 351, Table 232, changed
serial resistance value from 40 kΩ to
50 kΩ
POR and VBO Electrical In Table 235: Min, Typ, and Max 341
Characteristics values of VBO voltage threshold
modified and added ISpor_vbo
parameter
Ordering Information Ordering information modified 358

PS019217-1222 Revision History

 eZ80F91 MCU
Product Specification

Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Table of Contents v
Architectural Overview 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System Clock Source Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Register Map 27
eZ80® CPU Core 39
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
New Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reset 41
External Reset Input and Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Voltage Brownout Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Low-Power Modes 45
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Clock Peripheral Power-Down Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
General-Purpose Input/Output 49
GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
GPIO Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interrupt Controller 57
Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
GPIO Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Chip Selects and Wait States 65
Memory and I/O Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Memory Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Input/Output Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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WAIT Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Chip Selects During Bus Request/Bus Acknowledge Cycles . . . . . . . . . . . . . . . 70
Bus Mode Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
eZ80® Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Z80® Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Intel Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Motorola Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Chip Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Bus Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Random Access Memory 93
RAM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Flash Memory 97
Flash Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Information Page Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Flash Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Watchdog Timer 115
Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Programmable Reload Timers 121
Basic Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Specialty Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Timer Port Pin Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Multi-PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
PWM Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Modification of Edge Transition Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
AND/OR Gating of the PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
PWM Nonoverlapping Output Pair Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Multi-PWM Power-Trip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Multi-PWM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

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Real-Time Clock 159

Real-Time Clock Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Real-Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Real-Time Clock Oscillator and Source Selection . . . . . . . . . . . . . . . . . . . . . . . 160
Real-Time Clock Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Real-Time Clock Recommended Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Universal Asynchronous
Receiver/Transmitter 175
UART Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
UART Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
UART Recommended Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
BRG Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Infrared Encoder/Decoder 195
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Infrared Encoder/Decoder Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Loopback Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Serial Peripheral Interface 201
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
SPI Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Data Transfer Procedure with SPI Configured as a Master . . . . . . . . . . . . . . . 205
Data Transfer Procedure with SPI Configured as a Slave . . . . . . . . . . . . . . . . 206
SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
2
I C Serial I/O Interface 211
I2C General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Transferring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

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Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Zilog Debug Interface 231
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
ZDI-Supported Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
ZDI Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
ZDI Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
ZDI Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
ZDI Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
ZDI Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Operation of the eZ80F91 Device during ZDI Break Points . . . . . . . . . . . . . . . 238
Bus Requests During ZDI Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
ZDI Write Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
ZDI Read Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
ZDI Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
On-Chip Instrumentation 257
Introduction to On-Chip Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
OCI Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
OCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Phase-Locked Loop 265
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
PLL Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Power Requirement to the Phase-Locked Loop Function . . . . . . . . . . . . . . . . . 268
PLL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
eZ80® CPU Instruction Set 275
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Ethernet Media Access Controller 287
EMAC Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
EMAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
EMAC Shared Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
EMAC and the System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

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EMAC Operation in HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

EMAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
EMAC Interpacket Gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
On-Chip Oscillators 335
Primary Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
32 kHz Real-Time Clock Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . 337
Electrical Characteristics 339
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
POR and VBO Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Current Consumption Under Various Operating Conditions . . . . . . . . . . . . . . . 341
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
External Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
External Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
External I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Wait State Timing for Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Wait State Timing for Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
General-Purpose Input/Output Port Input Sample Timing . . . . . . . . . . . . . . . . . 354
General-Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
External Bus Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Packaging 357
Ordering Information 358
Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Customer Support 374

PS019217-1222
 eZ80F91 MCU
Product Specification

Architectural Overview
Zilog’s eZ80F91 device is a member of Zilog’s family of eZ80Acclaim!® Flash micro-
controllers. The eZ80F91 is a high-speed microcontroller with a maximum clock speed
of 50 MHz and single-cycle instruction fetch. It operates in Z80®-compatible address-
ing mode (64 KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the
eZ80F91 makes it suitable for a variety of applications, including industrial control,
embedded communication, and point-of-sale terminals.

Features
Key features of eZ80F91 device include:
• Single-cycle instruction fetch, high-performance, pipelined eZ80® CPU core
(referred as The CPU in this document)
• 10/100 BaseT ethernet media access controller with Media-Independent
Interface (MII)
• 256 KB Flash memory
• 16 KB SRAM (8 KB user and 8 KB Ethernet)
• Low-power features including SLEEP mode, HALT mode, and selective peripheral
power-down control
• Two Universal Asynchronous Receiver/Transmitter (UART) with independent Baud
Rate Generators (BRG)
• Serial Peripheral Interface (SPI) with independent clock rate generator
• I2C with independent clock rate generator
• IrDA-compliant infrared encoder/decoder
• Glueless external peripheral interface with 4 Chip Selects, individual Wait State
generators, an external WAIT input pin—supports Z80-, Intel-, and Motorola-style
buses
• Fixed-priority vectored interrupts (both internal and external) and interrupt controller
• Real-time clock with separate VDD pin for battery backup and selectable on-chip
32 kHz oscillator or external 50/60 Hz input
• Four 16-bit Counter/Timers with prescalers and direct input/output drive
• Watchdog Timer with internal oscillator clocking option
• 32 bits of General-Purpose Input/Output (GPIO)
• On-Chip Instrumentation (OCI™) and Zilog Debug Interfaces (ZDI)

PS019217-1222
 eZ80F91 MCU
Product Specification

• IEEE 1149.1-compatible JTAG

• 144-pin LQFP and BGA packages
• 3.0 V to 3.6 V supply voltage with 5 V tolerant inputs
• Operating Temperature Range:
– Standard: 0 ºC to +70 ºC
– Extended: –40 ºC to +105 ºC

Note: All signals with an overline are active Low. For example, the signal DCD1 is active when
it is a logical 0 (Low) state.

The power connections conventions are provided in the table below.

Connection Circuit Device

Power VCC VDD
Ground GND VSS

Block Diagram
Figure 1 on page 3 displays a block diagram of the eZ80F91 microcontroller.

PS019217-1222
 eZ80F91 MCU
Product Specification

MII Interface
Signals (18)

Ethernet 8KB
MAC Arbiter SRAM

RTC_VDD Real-Time
Clock and
RTC_XIN
32 KHz
RTC_X OUT Oscillator
BUSACK
BUSREQ
INSTRD
Bus
Controller IORQ
SCL
I2C MREQ
Serial
Interface RD
SDA
WR
ADDR[23:0]

DATA[7:0]

SCK NMI
SPI eZ80
SS Serial CPU
MISO Parallel HALT_SLP
Interface
MOSI

256KB JTAG/ZDI
Flash Debug JTAG/ZDI Signals (5)
Memory Interface
WP
WAIT
CTS0/1 Chip Select
Interrupt CS0
Vector and
DSR0/1 Wait State CS1
(8:0)
DCD0/1 UART 8KB Generator
Universal CS2
SRAM Interrupt
DTR0/1 Asynchronous Controller CS3
RI0/1 Receiver/
Transmitter
RTS0/1 (2)
RxD0/1 DATA[7:0]
TxD0/1
ADDR[23:0]

WDT Internal
GPIO Crystal Watch-Dog RC
IrDA 8-Bit General- Oscillator Programmable
Reload Timer Osc.
Encoder/ Purpose PLL, and
Decoder I/O Port System Clock Timer/Counter
(4) Generator (4) POR/VBO RESET
TxD0/1
TxD0/1

PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]

X
X
PHI
PLL_V
LOOP_FILT

IC0/1/2/3
EC0/1
TOUT0/2
OC0/1/2/3
PWM0/1/2/3
PWM0/1/2/3

Figure 1. eZ80F91 Block Diagram

PS019217-1222
 eZ80F91 MCU
Product Specification

Pin Description
Table 1 lists the pin configuration of the eZ80F91 device in the 144-BGA package.

Table 1. eZ80F91 144-BGA Pin Configuration

12 11 10 9 8 7 6 5 4 3 2 1
A SDA SCL PA0 PA4 PA7 COL TxD0 VDD Rx_DV MDC WPn A0
B VSS PHI PA1 PA3 VDD TxD3 Tx_EN VSS RxD1 MDIO A2 A1
C PB6 PB7 VDD PA5 VSS TxD2 Tx_CLK Rx_ RxD3 A3 VSS VDD
CLK
D PB1 PB3 PB5 VSS CRS TxD1 Rx_ER RxD2 A4 A8 A6 A7
E PC7 VDD PB0 PB4 PA2 Tx_ER RxD0 A5 A11 VSS VDD A10
F PC3 PC4 PC5 VSS PB2 PA6 A9 A17 A15 A14 A13 A12
G VSS PC0 PC1 PC2 PC6 PLL_ VSS A23 A20 VSS VDD A16
VSS
H XOUT XIN PLL_ VDD PD7 TMS VSS D5 VSS A21 A19 A18
VDD
J VSS VDD LOOP PD4 TRIGOUT RTC_ NMIn WRn D2 CS0n VDD A22
FILT_ VDD
OUT
K PD5 PD6 PD3 TDI VSS VDD RESETn RDn VDD D1 CS2n CS1n
L PD1 PD2 TRSTn TCK RTC_ BUSACKn WAITn MREQn D6 D4 D0 CS3n
XOUT
M PD0 VSS TDO HALT RTC_ BUSREQn INSTRDn IORQn D7 D3 VSS VDD
_ XIN
SLPn
Note: Lowercase n suffix indicates an active-low signal in this table only

PS019217-1222
 eZ80F91 MCU
Product Specification

Figure 2 displays the pin layout of the eZ80F91 device in the 144-pin LQFP package.

PA5/PWM1/TOUT2
PA4/PWM0/TOUT0
PA3/PWM3/OC3
PA2/PWM2/OC2
PA1/PWM1/OC1
PA0/PWM0/OC0
120 PA6/PWM2/EC1
PA7/PWM3
Rx_CLK

Tx_CLK
Rx_DV

Rx_ER

Tx_ER

130 Tx_EN
MDIO

RxD3
140 RxD2
RxD1
RxD0

TxD1
TxD2
TxD3
TxD0
MDC

CRS

SDA
COL

110 SCL
VDD

VDD

VDD
VSS

VSS

VSS

PHI
144 WP

108 VSS
A0 1
PB7/MOSI
A1 PB6/MISO
A2
PB5/IC3
A3
PB4/IC2
A4
PB3/SCK
VDD
PB2/SS
VSS
PB1/IC1
A5
100 PB0/IC0/EC0
A6
VSS
A7 10
VDD
A8
PC7/RI1
A9
PC6/DCD1
A10
PC5/DSR1
VDD
PC4/DTR1
VSS
PC3/CTS1
A11
PC2/RTS1
A12
PC1/RxD1
A13 144-Pin LQFP 90 PC0/TxD1
A14
VSS
A15 20
VDD
A16
PLL_VDD
VDD
XIN
VSS
XOUT
A17
PLL_VSS
A18
LOOP_FILT
A19
VSS
A20
VDD
A21
A22 80 PD7/RI0
A23 30 PD6/DCD0
VDD PD5/DSR0
VSS PD4/DTR0
CS0 PD3/CTS0
CS1 PD2/RTS0
CS2 PD1/RxD0/IR_RxD
CS3 36 73 PD0/TxD0/IR_TxD
D1 40

MREQ 50

VSS 60

TDO 70
IORQ

BUSREQ
WAIT
RESET

BUSACK
RD
WR
VSS
D0

D2
D3
D4
D5
D6
D7

VSS

INSTRD
VDD

VDD

VDD

RTC_XIN
NMI

TRIGOUT

TRST
HALT_SLP
TMS
TCK
VSS

TDI

VSS
RTC_VDD
RTC_XOUT

Figure 2. 144-Pin LQFP Configuration of the eZ80F91

PS019217-1222
 eZ80F91 MCU
Product Specification

Pin Characteristics
Table 2 lists the pins and functions of the eZ80F91 MCU’s 144-pin LQFP package and
144-BGA package.

Table 2. Pin Identification on the eZ80F91 Device

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
1 A1 ADDR0 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
2 B1 ADDR1 Address Bus Bidirectional
location in memory or I/O space to be
3 B2 ADDR2 Address Bus Bidirectional read or written. Configured as an input
during bus acknowledge cycles.
4 C3 ADDR3 Address Bus Bidirectional
Drives the Chip Select/Wait State
5 D4 ADDR4 Address Bus Bidirectional Generator block to generate Chip
Selects.
6 C1 VDD Power Supply Power Supply.
7 C2 VSS Ground Ground.
8 E5 ADDR5 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
9 D2 ADDR6 Address Bus Bidirectional
location in memory or I/O space to be
10 D1 ADDR7 Address Bus Bidirectional read or written. Configured as an input
during bus acknowledge cycles.
11 D3 ADDR8 Address Bus Bidirectional
Drives the Chip Select/Wait State
12 F6 ADDR9 Address Bus Bidirectional Generator block to generate Chip
Selects.
13 E1 ADDR10 Address Bus Bidirectional
14 E2 VDD Power Supply Power Supply.
15 E3 VSS Ground Ground.
16 E4 ADDR11 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.

PS019217-1222
 eZ80F91 MCU
Product Specification

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
17 F1 ADDR12 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
18 F2 ADDR13 Address Bus Bidirectional
location in memory or I/O space to be
19 F3 ADDR14 Address Bus Bidirectional read or written. Configured as an input
during bus acknowledge cycles.
20 F4 ADDR15 Address Bus Bidirectional
Drives the Chip Select/Wait State
21 G1 ADDR16 Address Bus Bidirectional Generator block to generate Chip
Selects.
22 G2 VDD Power Supply Power Supply.
23 G3 VSS Ground Ground.
24 F5 ADDR17 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
25 H1 ADDR18 Address Bus Bidirectional
location in memory or I/O space to be
26 H2 ADDR19 Address Bus Bidirectional read or written. Configured as an input
during bus acknowledge cycles.
27 G4 ADDR20 Address Bus Bidirectional
Drives the Chip Select/Wait State
28 H3 ADDR21 Address Bus Bidirectional Generator block to generate Chip
Selects.
29 J1 ADDR22 Address Bus Bidirectional
30 G5 ADDR23 Address Bus Bidirectional
31 J2 VDD Power Supply Power Supply.
32 H4 VSS Ground Ground.
33 J3 CS0 Chip Select 0 Output, Active CS0 Low indicates that an access is
Low occurring in the defined CS0 memory
or I/O address space.
34 K1 CS1 Chip Select 1 Output, Active CS1 Low indicates that an access is
Low occurring in the defined CS1 memory
or I/O address space.
35 K2 CS2 Chip Select 2 Output, Active CS2 Low indicates that an access is
Low occurring in the defined CS2 memory
or I/O address space.
36 L1 CS3 Chip Select 3 Output, Active CS3 Low indicates that an access is
Low occurring in the defined CS3 memory
or I/O address space.
37 M1 VDD Power Supply Power Supply.
38 M2 VSS Ground Ground.

PS019217-1222
 eZ80F91 MCU
Product Specification

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
39 L2 DATA0 Data Bus Bidirectional The data bus transfers data to and
from I/O and memory devices. The
40 K3 DATA1 Data Bus Bidirectional
eZ80F91 drives these lines only
41 J4 DATA2 Data Bus Bidirectional during Write cycles when the
eZ80F91 is the bus master.
42 M3 DATA3 Data Bus Bidirectional
43 L3 DATA4 Data Bus Bidirectional
44 H5 DATA5 Data Bus Bidirectional
45 L4 DATA6 Data Bus Bidirectional
46 M4 DATA7 Data Bus Bidirectional
47 K4 VDD Power Supply Power Supply.
48 G6 VSS Ground Ground.
49 M5 IORQ Input/Output Bidirectional, IORQ indicates that the CPU is
Request Active Low accessing a location in I/O space. RD
and WR indicate the type of access.
The eZ80F91 device does not drive
this line during RESET. It is an input
during bus acknowledge cycles.
50 L5 MREQ Memory Bidirectional, MREQ Low indicates that the CPU is
Request Active Low accessing a location in memory. The
RD, WR, and INSTRD signals indicate
the type of access. The eZ80F91
device does not drive this line during
RESET. It is an input during bus
acknowledge cycles.
51 K5 RD Read Output, RD Low indicates that the eZ80F91
Active Low device is reading from the current
address location. This pin is in a high-
impedance state during bus
acknowledge cycles.
52 J5 WR Write Output, Active WR indicates that the CPU is writing
Low to the current address location. This
pin is in a high-impedance state
during bus acknowledge cycles.

PS019217-1222
 eZ80F91 MCU
Product Specification

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
53 M6 INSTRD Instruction Output, Active INSTRD (with MREQ and RD)
Read Indicator Low indicates the eZ80F91 device is
fetching an instruction from memory.
This pin is in a high-impedance state
during bus acknowledge cycles.
54 L6 WAIT WAIT Request Schmitt-trigger Driving the WAIT pin Low forces the
input, Active Low CPU to wait additional clock cycles for
an external peripheral or external
memory to complete its Read or Write
operation.
55 K6 RESET Reset Bidirectional, This signal is used to initialize the
Active Low eZ80F91, and/or allow the ez80F91 to
Schmitt-trigger signal when it resets. See reset
input or open section for the timing details. This
drain output Schmitt-trigger input allows for RC rise
times.
56 J6 NMI Nonmaskable Schmitt-trigger The NMI input is a higher priority input
Interrupt input, Active Low, than the maskable interrupts. It is
edge-triggered always recognized at the end of an
interrupt instruction, regardless of the state of
the interrupt enable control bits. This
input includes a Schmitt- trigger to
allow for RC rise times.
57 M7 BUSREQ Bus Request Schmitt-trigger External devices request the eZ80F91
input, Active Low device to release the memory
interface bus for their use by driving
this pin Low.
58 L7 BUSACK Bus Output, Active The eZ80F91 device responds to a
Acknowledge Low Low on BUSREQ making the address,
data, and control signals high
impedance, and by driving the
BUSACK line Low. During bus
acknowledge cycles ADDR[23:0],
IORQ, and MREQ are inputs.
59 K7 VDD Power Supply Power Supply.
60 H6 VSS Ground Ground.

PS019217-1222
 eZ80F91 MCU
Product Specification

10

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
61 M8 RTC_XIN Real-Time Input This pin is the input to the low-power
Clock Crystal 32 kHz crystal oscillator for the Real-
Input time clock. If the Real-time clock is
disabled or not used, this input must
be left floating or tied to VSS to
minimize any input current leakage.
62 L8 RTC_XOUT Real-Time Bidirectional This pin is the output from the low-
Clock Crystal power 32 kHz crystal oscillator for the
Output Real-Time Clock. This pin is an input
when the RTC is configured to
operate from 50/60 Hz input clock
signals and the 32 kHz crystal
oscillator is disabled.
63 J7 RTC_VDD Real-Time Power supply for the Real-Time Clock
Clock Power and associated 32 kHz oscillator.
Supply Isolated from the power supply to the
remainder of the chip. A battery is
connected to this pin to supply
constant power to the Real-Time
Clock and 32 kHz oscillator. If the
Real-time clock is disabled or not
used this output must be tied to Vdd.
64 K8 VSS Ground Ground.
65 M9 HALT_SLP HALT and Output, Active A Low on this pin indicates that the
SLEEP Low CPU has entered either HALT or
Indicator SLEEP mode because of execution of
either a HALT or SLP instruction.
66 H7 TMS JTAG Test Input JTAG Mode Select Input.
Mode Select
67 L9 TCK JTAG Test Input JTAG and ZDI clock input.
Clock
68 J8 TRIGOUT JTAG Test Output Active High trigger event indicator.
Trigger Output
69 K9 TDI JTAG Test Bidirectional JTAG data input pin. Functions as ZDI
Data In data I/O pin when JTAG is disabled.
This pin has an internal pull-up
resistor in the pad.

PS019217-1222
 eZ80F91 MCU
Product Specification

11

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
70 M10 TDO JTAG Test Output JTAG data output pin.
Data Out
71 L10 TRST JTAG Reset Schmitt-trigger JTAG reset input pin.
input, Active Low
72 M11 VSS Ground Ground.
73 M12 PD0 GPIO Port D Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
TxD0 UART Output This pin is used by the UART to
Transmit Data transmit asynchronous serial data.
This signal is multiplexed with PD0.
IR_TxD IrDA Transmit Output This pin is used by the IrDA encoder/
Data decoder to transmit serial data. This
signal is multiplexed with PD0.
74 L12 PD1 GPIO Port D Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
RxD0 Receive Data Input This pin is used by the UART to
receive asynchronous serial data.
This signal is multiplexed with PD1.
IR_RxD IrDA Receive Input This pin is used by the IrDA encoder/
Data decoder to receive serial data. This
signal is multiplexed with PD1.

PS019217-1222
 eZ80F91 MCU
Product Specification

12

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
75 L11 PD2 GPIO Port D Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
RTS0 Request to Output, Modem control signal from UART.
Send Active Low This signal is multiplexed with PD2.
76 K10 PD3 GPIO Port D Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
CTS0 Clear to Send Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PD3.
77 J9 PD4 GPIO Port D Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
DTR0 Data Terminal Output, Modem control signal to the UART.
Ready Active Low This signal is multiplexed with PD4.

PS019217-1222
 eZ80F91 MCU
Product Specification

13

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
78 K12 PD5 GPIO Port D Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
DSR0 Data Set Input, Active Low Modem status signal to the UART.
Ready This signal is multiplexed with PD5.
79 K11 PD6 GPIO Port D Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
DCD0 Data Carrier Input, Active Low Modem status signal to the UART.
Detect This signal is multiplexed with PD6.
80 H8 PD7 GPIO Port D Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
RI0 Ring Indicator Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PD7.
81 J11 VDD Power Supply Power Supply.
82 J12 VSS Ground Ground.
83 J10 LOOP_FILT PLL Loop Filter Analog Loop Filter pin for the Analog PLL.
84 G7 PLL_VSS Ground Ground for Analog PLL.
85 H12 XOUT System Clock Output This pin is the output of the onboard
Oscillator crystal oscillator. When used, a crystal
Output must be connected between XIN and
XOUT.

PS019217-1222
 eZ80F91 MCU
Product Specification

14

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
86 H11 XIN System Clock Input This pin is the input to the onboard
Oscillator Input crystal oscillator for the primary
system clock. If an external oscillator
is used, its clock output must be
connected to this pin. When a crystal
is used, it must be connected between
XIN and XOUT.
87 H10 PLL_VDD Power Supply Power Supply for Analog PLL.
88 H9 VDD Power Supply Power Supply.
89 G12 VSS Ground Ground.
90 G11 PC0 GPIO Port C Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port C pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port C is multiplexed
with one UART.
TxD1 Transmit Data Output This pin is used by the UART to
transmit asynchronous serial data.
This signal is multiplexed with PC0.
91 G10 PC1 GPIO Port C Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port C pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port C is multiplexed
with one UART.
RxD1 Receive Data Schmitt-trigger This pin is used by the UART to
input receive asynchronous serial data.
This signal is multiplexed with PC1.

PS019217-1222
 eZ80F91 MCU
Product Specification

15

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
92 G9 PC2 GPIO Port C Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port C pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port C is multiplexed
with one UART.
RTS1 Request to Output, Active Modem control signal from UART.
Send Low This signal is multiplexed with PC2.
93 F12 PC3 GPIO Port C Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port C pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port C is multiplexed
with one UART.
CTS1 Clear to Send Schmitt-trigger Modem status signal to the UART.
input, Active Low This signal is multiplexed with PC3.
94 F11 PC4 GPIO Port C Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port C pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port C is multiplexed
with one UART.
DTR1 Data Terminal Output, Active Modem control signal to the UART.
Ready Low This signal is multiplexed with PC4.

PS019217-1222
 eZ80F91 MCU
Product Specification

16

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
95 F10 PC5 GPIO Port C Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port C pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port C is multiplexed
with one UART.
DSR1 Data Set Schmitt-trigger Modem status signal to the UART.
Ready input, Active Low This signal is multiplexed with PC5.
96 G8 PC6 GPIO Port C Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port C pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port C is multiplexed
with one UART.
DCD1 Data Carrier Schmitt-trigger Modem status signal to the UART.
Detect input, Active Low This signal is multiplexed with PC6.
97 E12 PC7 GPIO Port C Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port C pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port C is multiplexed
with one UART.
RI1 Ring Indicator Schmitt-trigger Modem status signal to the UART.
input, Active Low This signal is multiplexed with PC7.
98 E11 VDD Power Supply Power Supply.
99 F9 VSS Ground Ground.

PS019217-1222
 eZ80F91 MCU
Product Specification

17

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
100 E10 PB0 GPIO Port B Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port B pin,
when programmed as output is
selected to be an open-drain or open-
source output.
IC0 Input Capture Schmitt-trigger Input Capture A Signal to Timer 1.
input This signal is multiplexed with PB0.
EC0 Event Counter Schmitt-trigger Event Counter Signal to Timer 1. This
input signal is multiplexed with PB0.
101 D12 PB1 GPIO Port B Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port B pin,
when programmed as output is
selected to be an open-drain or open-
source output.
IC1 Input Capture Schmitt-trigger Input Capture B Signal to Timer 1.
input This signal is multiplexed with PB1.
102 F8 PB2 GPIO Port B Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port B pin,
when programmed as output is
selected to be an open-drain or open-
source output.
SS SPI Slave Schmitt-trigger The slave select input line is used to
Select input, Active Low select a slave device in SPI mode.
This signal is multiplexed with PB2.

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Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
103 D11 PB3 GPIO Port B Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port B pin,
when programmed as output is
selected to be an open-drain or open-
source output.
SCK SPI Serial Bidirectional with SPI serial clock. This signal is
Clock Schmitt-trigger multiplexed with PB3.
input
104 E9 PB4 GPIO Port B Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port B pin,
when programmed as output is
selected to be an open-drain or open-
source output.
IC2 Input Capture Schmitt-trigger Input Capture A Signal to Timer 3.
input This signal is multiplexed with PB4.
105 D10 PB5 GPIO Port B Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port B pin,
when programmed as output is
selected to be an open-drain or open-
source output.
IC3 Input Capture Schmitt-trigger Input Capture B Signal to Timer 3.
input This signal is multiplexed with PB5.

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Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
106 C12 PB6 GPIO Port B Bidirectional with This pin is be used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port B pin,
when programmed as output is
selected to be an open-drain or open-
source output.
MISO SPI Master-In/ Bidirectional with The MISO line is configured as an
Slave-Out Schmitt-trigger input when the eZ80F91 device is an
input SPI master device and as an output
when eZ80F91 is an SPI slave device.
This signal is multiplexed with PB6.
107 C11 PB7 GPIO Port B Bidirectional with This pin is used for GPIO. It is
Schmitt-trigger individually programmed as input or
input output and is also used individually as
an interrupt input. Each Port B pin,
when programmed as output is
selected to be an open-drain or open-
source output.
MOSI SPI Master Out Bidirectional with The MOSI line is configured as an
Slave In Schmitt-trigger output when the eZ80F91 device is an
input SPI master device and as an input
when the eZ80F91 device is an SPI
slave device. This signal is
multiplexed with PB7.
108 B12 VSS Ground Ground.
109 A12 SDA I2C Serial Data Bidirectional This pin carries the I2C data signal.
110 A11 SCL I2C Serial Bidirectional This pin is used to receive and
Clock transmit the I2C clock.
111 B11 PHI System Clock Output This pin is an output driven by the
internal system clock. It is used by the
system for synchronization with the
eZ80F91 device.
112 C10 VDD Power Supply Power Supply.
113 D9 VSS Ground Ground.

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Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
114 A10 PA0 GPIO Port A Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port A pin,
when programmed as output is
selected to be an open-drain or open-
source output.
PWM0 PWM Output This pin is used by Timer 3 for PWM
Output 0 0. This signal is multiplexed with PA0.
OC0 Output Output This pin is used by Timer 3 for Output
Compare 0 Compare 0. This signal is multiplexed
with PA0.
115 B10 PA1 GPIO Port A Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port A pin,
when programmed as output is
selected to be an open-drain or open-
source output.
PWM1 PWM Output This pin is used by Timer 3 for PWM
Output 1 1. This signal is multiplexed with PA1.
OC1 Output Output This pin is used by Timer 3 for Output
Compare 1 Compare 1. This signal is multiplexed
with PA1.
116 E8 PA2 GPIO Port A Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port A pin,
when programmed as output is
selected to be an open-drain or open-
source output.
PWM2 PWM Output This pin is used by Timer 3 for PWM
Output 2 2. This signal is multiplexed with PA2.
OC2 Output Output This pin is used by Timer 3 for Output
Compare 2 Compare 2. This signal is multiplexed
with PA2.

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Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
117 B9 PA3 GPIO Port A Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port A pin,
when programmed as output is
selected to be an open-drain or open-
source output.
PWM3 PWM Output 3 Output This pin is used by Timer 3 for PWM
3. This signal is multiplexed with PA3.
OC3 Output Output This pin is used by Timer 3 for Output
Compare 3 Compare 3 This signal is multiplexed
with PA3.
118 A9 PA4 GPIO Port A Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port A pin,
when programmed as output is
selected to be an open-drain or open-
source output.
PWM0 PWM Output 0 Output This pin is used by Timer 3 for
Inverted negative PWM 0. This signal is
multiplexed with PA4.
TOUT0 Timer Out Output This pin is used by Timer 0 timer-out
signal. This signal is multiplexed with
PA4.
119 C9 PA5 GPIO Port A Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port A pin,
when programmed as output is
selected to be an open-drain or open-
source output.
PWM1 PWM Output 1 Output This pin is used by Timer 3 for
Inverted negative PWM 1. This signal is
multiplexed with PA5.
TOUT2 Timer Out Output This pin is used by the Timer 2 timer-
out signal. This signal is multiplexed
with PA5.

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Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
120 F7 PA6 GPIO Port A Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port A pin,
when programmed as output is
selected to be an open-drain or open-
source output.
PWM2 PWM Output 2 Output This pin is used by Timer 3 for
Inverted negative PWM 2. This signal is
multiplexed with PA6.
EC1 Event Counter Input Event Counter Signal to Timer 2. This
signal is multiplexed with PA6.
121 A8 PA7 GPIO Port A Bidirectional This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port A pin,
when programmed as output is
selected to be an open-drain or open-
source output.
PWM3 PWM Output 3 Output This pin is used by Timer 3 for
Inverted negative PWM 3. This signal is
multiplexed with PA7.
122 B8 VDD Power Supply Power Supply.
123 C8 VSS Ground Ground.
124 D8 CRS MII Carrier Input This pin is used by the EMAC for the
Sense MII Interface to the PHY (physical
layer). Carrier Sense is an
asynchronous signal.
125 A7 COL MII Collision Input This pin is used by the EMAC for the
Detect MII Interface to the PHY. Collision
Detect is an asynchronous signal.
126 B7 TxD3 MII Transmit Output This pin is used by the EMAC for the
Data MII Interface to the PHY. Transmit
Data is synchronous to the rising-
edge of Tx_CLK.

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Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
127 C7 TxD2 MII Transmit Output This pin is used by the Ethernet MAC
Data for the MII Interface to the PHY.
Transmit Data is synchronous to the
rising-edge of Tx_CLK.
128 D7 TxD1 MII Transmit Output This pin is used by the Ethernet MAC
Data for the MII Interface to the PHY.
Transmit Data is synchronous to the
rising-edge of Tx_CLK.
129 A6 TxD0 MII Transmit Output This pin is used by the Ethernet MAC
Data for the MII Interface to the PHY.
Transmit Data is synchronous to the
rising-edge of Tx_CLK.
130 B6 Tx_EN MII Transmit Output This pin is used by the Ethernet MAC
Enable for the MII Interface to the PHY.
Transmit Enable is synchronous to the
rising-edge of Tx_CLK.
131 C6 Tx_CLK MII Transmit Input This pin is used by the Ethernet MAC
Clock for the MII Interface to the PHY.
Transmit Clock is the Nibble or
Symbol Clock provided by the MII
PHY interface.
132 E7 Tx_ER MII Transmit Output This pin is used by the Ethernet MAC
Error for the MII Interface to the PHY.
Transmit Error is synchronous to the
rising-edge of Tx_CLK.
133 A5 VDD Power Supply Power Supply.
134 B5 VSS Ground Ground.
135 D6 Rx_ER MII Receive Input This pin is used by the Ethernet MAC
Error for the MII Interface to the PHY.
Receive Error is provided by the MII
PHY interface synchronous to the
rising-edge of Rx_CLK.
136 C5 Rx_CLK MII Receive Input This pin is used by the Ethernet MAC
Clock for the MII Interface to the PHY.
Receive Clock is the Nibble or Symbol
Clock provided by the MII PHY
interface.

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Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
137 A4 Rx_DV MII Receive Input This pin is used by the Ethernet MAC
Data Valid for the MII Interface to the PHY.
Receive Data Valid is provided by the
MII PHY interface synchronous to the
rising-edge of Rx_CLK.
138 E6 RxD0 MII Receive Input This pin is used by the Ethernet MAC
Data for the MII Interface to the PHY.
Receive Data is provided by the MII
PHY interface synchronous to the
rising-edge of Rx_CLK.
139 B4 RxD1 MII Receive Input This pin is used by the Ethernet MAC
Data for the MII Interface to the PHY.
Receive Data is provided by the MII
PHY interface synchronous to the
rising-edge of Rx_CLK.
140 D5 RxD2 MII Receive Input This pin is used by the Ethernet MAC
Data for the MII Interface to the PHY.
Receive Data is provided by the MII
PHY interface synchronous to the
rising-edge of Rx_CLK.
141 C4 RxD3 MII Receive Input This pin is used by the Ethernet MAC
Data for the MII Interface to the PHY.
Receive Data is provided by the MII
PHY interface synchronous to the
rising-edge of Rx_CLK.
142 A3 MDC MII Output This pin is used by the Ethernet MAC
Management for the MII Management Interface to
Data Clock the PHY. The Ethernet MAC provides
the MII Management Data Clock to
the MII PHY interface.

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Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA
Pin No Pin No Symbol Function Signal Direction Description
143 B3 MDIO MII Bidirectional This pin is used by the Ethernet MAC
Management for the MII Management Interface to
Data the PHY. The Ethernet MAC sends
and receives the MII Management
Data to and from the MII PHY
interface.
144 A2 WP Write Protect Schmitt-trigger The Write Protect input is used by the
input, Active Low Flash Controller to protect the Boot
Block from Write and ERASE
operations.

System Clock Source Options

The following section describes the system clock source options.

System Clock—The eZ80F91 device’s internal clock, SCLK, is responsible for clocking
all internal logic. The SCLK source can be an external crystal oscillator, an internal PLL,
or an internal 32 kHz RTC oscillator. The SCLK source is selected by PLL Control Regis-
ter 0. RESET default is provided by the external crystal oscillator. For more details on
CLK_MUX values in the PLL Control Register 0, see Table 154 on page 269.

PHI—PHI is a device output driven by SCLK that is used for system synchronization to
the eZ80F91 device. PHI is used as the reference clock for all AC characteristics, see
page 344.

External Crystal Oscillator—An externally-driven oscillator operates in two modes. In

one mode, the XIN pin is driven by a oscillator from DC up to 50 MHz when the XOUT pin
is not connected. In the other mode, the XIN and XOUT pins are driven by a crystal circuit.
Crystals recommended by Zilog® are defined to be a 50 MHz–3 overtone circuit or 1–10
MHz range fundamental for PLL operation. For details, see On-Chip Oscillators on page
335.

Real Time Clock—An internal 32 kHz real-time clock crystal oscillator driven by either
the on-chip 32768 Hz crystal oscillator or a 50/60 Hz power-line frequency input. While
intended for timekeeping, the RTC 32 kHz oscillator is selected as an SCLK. RTC_VDD
and RTC_VSS provides an isolated power supply to ensure RTC operation in the event of
loss of line power when a battery is provided. For more details, see On-Chip Oscillators on
page 335.

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PLL Clock—The eZ80F91 internal PLL driven by external crystals or external crystal
oscillators in the range of 1 MHz to 10 MHz generates an SCLK up to 50 MHz. For more-
details, see Phase-Locked Loop on page 265.

SCLK Source Selection Example

For additional SCLK source selection examples, refer to Crystal Oscillator/Resonator
Guidelines for eZ80® and eZ80Acclaim!® Devices Technical Note (TN0013) available on
www.zilog.com.

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Register Map
All on-chip peripheral registers are accessed in the I/O address space. All I/O operations
employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all
I/O operations (ADDR[23:16] = XX). All I/O operations using 16-bit addresses within the
0000h–00FFh range are routed to the on-chip peripherals. External I/O chip selects are
not generated if the address space programmed for the I/O chip selects overlap the
0000h–00FFh address range.
Registers at unused addresses within the 0000h–00FFh range assigned to on-chip periph-
erals are not implemented. Read access to such addresses returns unpredictable values and
Write access produces no effect. Table 3 lists the register map for the eZ80F91 device.

Table 3. Register Map

Address Reset CPU Page

(hex) Mnemonic Name (hex) Access No

Product ID
0000 ZDI_ID_L eZ80® Product ID Low Byte Register 08 R 252
0001 ZDI_ID_H eZ80 Product ID High Byte Register 00 R 252
0002 ZDI_ID_REV eZ80 Product ID Revision Register XX R 252

Interrupt Priority
0010 INT_P0 Interrupt Priority Register—Byte 0 00 R/W 61
0011 INT_P1 Interrupt Priority Register—Byte 1 00 R/W 61
0012 INT_P2 Interrupt Priority Register—Byte 2 00 R/W 61
0013 INT_P3 Interrupt Priority Register—Byte 3 00 R/W 61
0014 INT_P4 Interrupt Priority Register—Byte 4 00 R/W 61
0015 INT_P5 Interrupt Priority Register—Byte 5 00 R/W 61

Ethernet Media Access Controller

0020 EMAC_TEST EMAC Test Register 00 R/W 298
0021 EMAC_CFG1 EMAC Configuration Register 00 R/W 299
0022 EMAC_CFG2 EMAC Configuration Register 37 R/W 301
0023 EMAC_CFG3 EMAC Configuration Register 0F R/W 302
0024 EMAC_CFG4 EMAC Configuration Register 00 R/W 303
0025 EMAC_STAD_0 EMAC Station Address—Byte 0 00 R/W 304

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Table 3. Register Map (Continued)

Address Reset CPU Page

(hex) Mnemonic Name (hex) Access No
0026 EMAC_STAD_1 EMAC Station Address—Byte 1 00 R/W 304
0027 EMAC_STAD_2 EMAC Station Address—Byte 2 00 R/W 304
0028 EMAC_STAD_3 EMAC Station Address—Byte 3 00 R/W 304
0029 EMAC_STAD_4 EMAC Station Address—Byte 4 00 R/W 304
002A EMAC_STAD_5 EMAC Station Address—Byte 5 00 R/W 304
002B EMAC_TPTV_L EMAC Transmit Pause 00 R/W 305
Timer Value—Low Byte
002C EMAC_TPTV_H EMAC Transmit Pause 00 R/W 305
Timer Value—High Byte
002D EMAC_IPGT EMAC Inter-Packet Gap 15 R/W 306
002E EMAC_IPGR1 EMAC Non-Back-Back IPG 0C R/W 308
002F EMAC_IPGR2 EMAC Non-Back-Back IPG 12 R/W 308
0030 EMAC_MAXF_L EMAC Maximum Frame 00 R/W 309
Length—Low Byte
0031 EMAC_MAXF_H EMAC Maximum Frame 06 R/W 310
Length—High Byte
0032 EMAC_AFR EMAC Address Filter Register 00 R/W 311
0033 EMAC_HTBL_0 EMAC Hash Table—Byte 0 00 R/W 312
0034 EMAC_HTBL_1 EMAC Hash Table—Byte 1 00 R/W 312
0035 EMAC_HTBL_2 EMAC Hash Table—Byte 2 00 R/W 312
0036 EMAC_HTBL_3 EMAC Hash Table—Byte 3 00 R/W 312
0037 EMAC_HTBL_4 EMAC Hash Table—Byte 4 00 R/W 312
0038 EMAC_HTBL_5 EMAC Hash Table—Byte 5 00 R/W 312
0039 EMAC_HTBL_6 EMAC Hash Table—Byte 6 00 R/W 312
003A EMAC_HTBL_7 EMAC Hash Table—Byte 7 00 R/W 312
003B EMAC_MIIMGT EMAC MII Management Register 00 R/W 313
003C EMAC_CTLD_L EMAC PHY Configuration 00 R/W 314
Data—Low Byte
003D EMAC_CTLD_H EMAC PHY Configuration 00 R/W 315
Data—High Byte
003E EMAC_RGAD EMAC PHY Register Address Register 00 R/W 315

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29

Table 3. Register Map (Continued)

Address Reset CPU Page

(hex) Mnemonic Name (hex) Access No
003F EMAC_FIAD EMAC PHY Unit Select Address 00 R/W 316
Register
0040 EMAC_PTMR EMAC Transmit Polling Timer Register 00 R/W 316
0041 EMAC_RST EMAC Reset Control Register 20 R/W 317
0042 EMAC_TLBP_L EMAC Transmit Lower Boundary 00 R/W 318
Pointer—Low Byte
0043 EMAC_TLBP_H EMAC Transmit Lower Boundary 00 R/W 318
Pointer—High Byte
0044 EMAC_BP_L EMAC Boundary Pointer—Low Byte 00 R/W 319
0045 EMAC_BP_H EMAC Boundary Pointer—High Byte C0 R/W 319
0046 EMAC_BP_U EMAC Boundary Pointer—Upper Byte FF R/W 319
0047 EMAC_RHBP_L EMAC Receive High Boundary 00 R/W 320
Pointer—Low Byte
0048 EMAC_RHBP_H EMAC Receive High Boundary 00 R/W 321
Pointer—High Byte
0049 EMAC_RRP_L EMAC Receive Read 00 R/W 321
Pointer—Low Byte
004A EMAC_RRP_H EMAC Receive Read 00 R/W 322
Pointer—High Byte
004B EMAC_BUFSZ EMAC Buffer Size Register 00 R/W 322
004C EMAC_IEN EMAC Interrupt Enable Register 00 R/W 323
004D EMAC_ISTAT EMAC Interrupt Status Register 00 R/W 325
004E EMAC_PRSD_L EMAC PHY Read Status 00 R/W 326
Data—Low Byte
004F EMAC_PRSD_H EMAC PHY Read Status 00 R/W 327
Data—High Byte
0050 EMAC_MIISTAT EMAC MII Status Register 00 R/W 327
0051 EMAC_RWP_L EMAC Receive Write 00 R/W 328
Pointer—Low Byte
0052 EMAC_RWP_H EMAC Receive Write 00 R/W 329
Pointer—High Byte
0053 EMAC_TRP_L EMAC Transmit Read 00 R/W 329
Pointer—Low Byte

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Table 3. Register Map (Continued)

Address Reset CPU Page

(hex) Mnemonic Name (hex) Access No
0054 EMAC_TRP_H EMAC Transmit Read 00 R/W 330
Pointer—High Byte
0055 EMAC_BLKSLFT_L EMAC Receive Blocks Left 20 R/W 330
Register—Low Byte
0056 EMAC_BLKSLFT_H EMAC Receive Blocks Left 00 R/W 331
Register—High Byte
0057 EMAC_FDATA_L EMAC FIFO Data—Low Byte XX R/W 332
0058 EMAC_FDATA_H EMAC FIFO Data—High Byte 0X R/W 332
0059 EMAC_FFLAGS EMAC FIFO Flags Register 33 R/W 333

PLL
005C PLL_DIV_L PLL Divider Register—Low Byte 00 W 268
005D PLL_DIV_H PLL Divider Register—High Byte 00 W 269
005E PLL_CTL0 PLL Control Register 0 00 R/W 269
005F PLL_CTL1 PLL Control Register 1 00 R/W 271

Timers and PWM

0060 TMR0_CTL Timer 0 Control Register 00 R/W 132
0061 TMR0_IER Timer 0 Interrupt Enable Register 00 R/W 133
0062 TMR0_IIR Timer 0 Interrupt Identification Register 00 R/W 135
0063 TMR0_DR_L Timer 0 Data Register—Low Byte XX R 136
TMR0_RR_L Timer 0 Reload Register—Low Byte XX W 138
0064 TMR0_DR_H Timer 0 Data Register—High Byte XX R 137
TMR0_RR_H Timer 0 Reload Register—High Byte XX W 139
0065 TMR1_CTL Timer 1 Control Register 00 R/W 132
0066 TMR1_IER Timer 1 Interrupt Enable Register 00 R/W 133
0067 TMR1_IIR Timer 1 Interrupt Identification Register 00 R/W 135
0068 TMR1_DR_L Timer 1 Data Register—Low Byte XX R 136
TMR1_RR_L Timer 1 Reload Register—Low Byte XX W 138
0069 TMR1_DR_H Timer 1 Data Register—High Byte XX R 137
TMR1_RR_H Timer 1 Reload Register—High Byte XX W 139

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Table 3. Register Map (Continued)

Address Reset CPU Page

(hex) Mnemonic Name (hex) Access No
006A TMR1_CAP_CTL Timer 1 Input Capture Control Register XX R/W 139
006B TMR1_CAPA_L Timer 1 Capture Value A XX R/W 140
Register—Low Byte
006C TMR1_CAPA_H Timer 1 Capture Value A XX R/W 141
Register—High Byte
006D TMR1_CAPB_L Timer 1 Capture Value B XX R/W 141
Register—Low Byte
006E TMR1_CAPB_H Timer 1 Capture Value B XX R/W 142
Register—High Byte
006F TMR2_CTL Timer 2 Control Register 00 R/W 132
0070 TMR2_IER Timer 2 Interrupt Enable Register 00 R/W 133
0071 TMR2_IIR Timer 2 Interrupt Identification Register 00 R/W 135
0072 TMR2_DR_L Timer 2 Data Register—Low Byte XX R 136
TMR2_RR_L Timer 2 Reload Register—Low Byte XX W 138
0073 TMR2_DR_H Timer 2 Data Register—High Byte XX R 137
TMR2_RR_H Timer 2 Reload Register—High Byte XX W 139
0074 TMR3_CTL Timer 3 Control Register 00 R/W 132
0075 TMR3_IER Timer 3 Interrupt Enable Register 00 R/W 133
0076 TMR3_IIR Timer 3 Interrupt Identification Register 00 R/W 135
0077 TMR3_DR_L Timer 3 Data Register—Low Byte XX R 136
TMR3_RR_L Timer 3 Reload Register—Low Byte XX W 138
0078 TMR3_DR_H Timer 3 Data Register—High Byte XX R 137
TMR3_RR_H Timer 3 Reload Register—High Byte XX W 139
0079 PWM_CTL1 PWM Control Register 1 00 R/W 153
007A PWM_CTL2 PWM Control Register 2 00 R/W 154
007B PWM_CTL3 PWM Control Register 3 00 R/W 156
TMR3_CAP_CTL Timer 3 Input Capture Control Register 00 R/W 139
007C PWM0R_L PWM 0 Rising-Edge XX R/W 157
Register—Low Byte
TMR3_CAPA_L Timer 3 Capture Value A XX R/W 140
Register—Low Byte

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Table 3. Register Map (Continued)

Address Reset CPU Page

(hex) Mnemonic Name (hex) Access No
007D PWM0R_H PWM 0 Rising-Edge XX R/W 157
Register—High Byte
TMR3_CAPA_H Timer 3 Capture Value A XX R/W 141
Register—High Byte
007E PWM1R_L PWM 1 Rising-Edge XX R/W 157
Register—Low Byte
TMR3_CAPB_L Timer 3 Capture Value B XX R/W 141
Register—Low Byte
007F PWM1R_H PWM 1 Rising-Edge XX R/W 157
Register—High Byte
TMR3_CAPB_H Timer 3 Capture Value B XX R/W 142
Register—High Byte
0080 PWM2R_L PWM 2 Rising-Edge XX R/W 157
Register—Low Byte
TMR3_OC_CTL1 Timer 3 Output Compare Control 00 R/W 132
Register 1
0081 PWM2R_H PWM 2 Rising-Edge XX R/W 157
Register—High Byte
TMR3_OC_CTL2 Timer 3 Output Compare Control 00 R/W 132
Register 2
0082 PWM3R_L PWM 3 Rising-Edge XX R/W 157
Register—Low Byte
TMR3_OC0_L Timer 3 Output Compare 0 Value XX R/W 144
Register—Low Byte
0083 PWM3R_H PWM 3 Rising-Edge XX R/W 157
Register—High Byte
TMR3_OC0_H Timer 3 Output Compare 0 Value XX R/W 145
Register—High Byte
0084 PWM0F_L PWM 0 Falling-Edge XX R/W 158
Register—Low Byte
TMR3_OC1_L Timer 3 Output Compare 1 Value XX R/W 144
Register—Low Byte

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Table 3. Register Map (Continued)

Address Reset CPU Page

(hex) Mnemonic Name (hex) Access No
0085 PWM0F_H PWM 0 Falling-Edge XX R/W 158
Register—High Byte
TMR3_OC1_H Timer 3 Output Compare 1 Value XX R/W 145
Register—High Byte
0086 PWM1F_L PWM 1 Falling-Edge XX R/W 158
Register—Low Byte
TMR3_OC2_L Timer 3 Output Compare 2 Value XX R/W 144
Register—Low Byte
0087 PWM1F_H PWM 1 Falling-Edge XX R/W 158
Register—High Byte
TMR3_OC2_H Timer 3 Output Compare 2 Value XX R/W 145
Register—High Byte
0088 PWM2F_L PWM 2 Falling-Edge XX R/W 158
Register—Low Byte
TMR3_OC3_L Timer 3 Output Compare 3 Value XX R/W 144
Register—Low Byte
0089 PWM2F_H PWM 2 Falling-Edge XX R/W 158
Register—High Byte
TMR3_OC3_H Timer 3 Output Compare 3 Value XX R/W 145
Register—High Byte
008A PWM3F_L PWM 3 Falling-Edge XX R/W 158
Register—Low Byte
008B PWM3F_H PWM 3 Falling-Edge XX R/W 158
Register—High Byte

Watchdog Timer
0093 WDT_CTL Watchdog Timer Control Register 08/28 R/W 117
0094 WDT_RR Watchdog Timer Reset Register XX W 119

General-Purpose Input/Output Ports

0096 PA_DR Port A Data Register XX R/W 55
0097 PA_DDR Port A Data Direction Register FF R/W 55
0098 PA_ALT1 Port A Alternate Register 1 00 R/W 56
0099 PA_ALT2 Port A Alternate Register 2 00 R/W 56

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Table 3. Register Map (Continued)

Address Reset CPU Page

(hex) Mnemonic Name (hex) Access No
009A PB_DR Port B Data Register XX R/W 55
009B PB_DDR Port B Data Direction Register FF R/W 55
009C PB_ALT1 Port B Alternate Register 1 00 R/W 56
009D PB_ALT2 Port B Alternate Register 2 00 R/W 56
009E PC_DR Port C Data Register XX R/W 55
009F PC_DDR Port C Data Direction Register FF R/W 55
00A0 PC_ALT1 Port C Alternate Register 1 00 R/W 56
00A1 PC_ALT2 Port C Alternate Register 2 00 R/W 56
00A2 PD_DR Port D Data Register XX R/W 55
00A3 PD_DDR Port D Data Direction Register FF R/W 55
00A4 PD_ALT1 Port D Alternate Register 1 00 R/W 56
00A5 PD_ALT2 Port D Alternate Register 2 00 R/W 56
00A6 PA_ALT0 Port A Alternate Register 0 00 W 56
00A7 PB_ALT0 Port B Alternate Register 0 00 W 56

Chip Select/Wait State Generator

00A8 CS0_LBR Chip Select 0 Lower Bound Register 00 R/W 85
00A9 CS0_UBR Chip Select 0 Upper Bound Register FF R/W 86
00AA CS0_CTL Chip Select 0 Control Register E8 R/W 87
00AB CS1_LBR Chip Select 1 Lower Bound Register 00 R/W 85
00AC CS1_UBR Chip Select 1 Upper Bound Register 00 R/W 86
00AD CS1_CTL Chip Select 1 Control Register 00 R/W 87
00AE CS2_LBR Chip Select 2 Lower Bound Register 00 R/W 85
00AF CS2_UBR Chip Select 2 Upper Bound Register 00 R/W 86
00B0 CS2_CTL Chip Select 2 Control Register 00 R/W 87
00B1 CS3_LBR Chip Select 3 Lower Bound Register 00 R/W 85
00B2 CS3_UBR Chip Select 3 Upper Bound Register 00 R/W 86
00B3 CS3_CTL Chip Select 3 Control Register 00 R/W 87

Random Access Memory Control

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Table 3. Register Map (Continued)

Address Reset CPU Page

(hex) Mnemonic Name (hex) Access No
00B4 RAM_CTL RAM Control Register C0 R/W 94
00B5 RAM_ADDR_U RAM Address Upper Byte Register FF R/W 95
00B6 MBIST_GPR General-Purpose RAM MBIST Control 00 R/W 96
00B7 MBIST_EMR Ethernet MAC RAM MBIST Control 00 R/W 96

Serial Peripheral Interface

00B8 SPI_BRG_L SPI Baud Rate Generator 02 R/W 207
Register—Low Byte
00B9 SPI_BRG_H SPI Baud Rate Generator 00 R/W 207
Register—High Byte
00BA SPI_CTL SPI Control Register 04 R/W 208
00BB SPI_SR SPI Status Register 00 R 209
00BC SPI_TSR SPI Transmit Shift Register XX W 210
SPI_RBR SPI Receive Buffer Register XX R 210

Infrared Encoder/Decoder
00BF IR_CTL Infrared Encoder/Decoder Control 00 R/W 199

Universal Asynchronous Receiver/Transmitter 0 (UART0)

00C0 UART0_RBR UART 0 Receive Buffer Register XX R 184
UART0_THR UART 0 Transmit Holding Register XX W 184
UART0_BRG_L UART 0 Baud Rate Generator 02 R/W 182
Register—Low Byte
00C1 UART0_IER UART 0 Interrupt Enable Register 00 R/W 185
UART0_BRG_H UART 0 Baud Rate Generator 00 R/W 183
Register—High Byte
00C2 UART0_IIR UART 0 Interrupt Identification Register 01 R 186
UART0_FCTL UART 0 FIFO Control Register 00 W 187

Universal Asynchronous Receiver/Transmitter 0 (UART0)

00C3 UART0_LCTL UART 0 Line Control Register 00 R/W 188
00C4 UART0_MCTL UART 0 Modem Control Register 00 R/W 190
00C5 UART0_LSR UART 0 Line Status Register 60 R 191
00C6 UART0_MSR UART 0 Modem Status Register XX R 193

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Table 3. Register Map (Continued)

Address Reset CPU Page

(hex) Mnemonic Name (hex) Access No
00C7 UART0_SPR UART 0 Scratch Pad Register 00 R/W 194

I2C
00C8 I2C_SAR I2C Slave Address Register 00 R/W 224
2
00C9 I2C_XSAR I C Extended Slave Address Register 00 R/W 224
00CA I2C_DR I2C Data Register 00 R/W 225
2
00CB I2C_CTL I C Control Register 00 R/W 226
General-Purpose Input/Output Ports
00CE PC_ALT0 Port C Alternate Register 0 00 W 56
00CF PD_ALT0 Port D Alternate Register 0 00 W 56
2
00CC I2C_SR I C Status Register F8 R 227
I2C_CCR I2C Clock Control Register 00 W 229
2
00CD I2C_SRR I C Software Reset Register XX W 230

Universal Asynchronous Receiver/Transmitter 1 (UART1)

00D0 UART1_RBR UART 1 Receive Buffer Register XX R 184
UART1_THR UART 1 Transmit Holding Register XX W 184
UART1_BRG_L UART 1 Baud Rate Generator 02 R/W 182
Register—Low Byte
00D1 UART1_IER UART 1 Interrupt Enable Register 00 R/W 185
UART1_BRG_H UART 1 Baud Rate Generator 00 R/W 183
Register—High Byte
00D2 UART1_IIR UART 1 Interrupt Identification Register 01 R 186
UART1_FCTL UART 1 FIFO Control Register 00 W 187
00D3 UART1_LCTL UART 1 Line Control Register 00 R/W 188

Universal Asynchronous Receiver/Transmitter 0 (UART0)

00D4 UART1_MCTL UART 1 Modem Control Register 00 R/W 190
00D5 UART1_LSR UART 1 Line Status Register 60 R/W 191
00D6 UART1_MSR UART 1 Modem Status Register XX R/W 193
00D7 UART1_SPR UART 1 Scratch Pad Register 00 R/W 194

Low-Power Control

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Table 3. Register Map (Continued)

Address Reset CPU Page

(hex) Mnemonic Name (hex) Access No
00DB CLK_PPD1 Clock Peripheral Power-Down 00 R/W 47
Register 1
00DC CLK_PPD2 Clock Peripheral Power-Down 00 R/W 48
Register 2

Real-Time Clock
00E0 RTC_SEC RTC Seconds Register XX R/W 161
00E1 RTC_MIN RTC Minutes Register XX R/W 162
00E2 RTC_HRS RTC Hours Register XX R/W 163
00E3 RTC_DOW RTC Day-of-the-Week Register 0X R/W 164
00E4 RTC_DOM RTC Day-of-the-Month Register XX R/W 165
00E5 RTC_MON RTC Month Register XX R/W 166
00E6 RTC_YR RTC Year Register XX R/W 167
00E7 RTC_CEN RTC Century Register XX R/W 168
00E8 RTC_ASEC RTC Alarm Seconds Register XX R/W 169
00E9 RTC_AMIN RTC Alarm Minutes Register XX R/W 170
00EA RTC_AHRS RTC Alarm Hours Register XX R/W 171
00EB RTC_ADOW RTC Alarm Day-of-the-Week Register 0X R/W 172
00EC RTC_ACTRL RTC Alarm Control Register 00 R/W 173
00ED RTC_CTRL RTC Control Register x0xxxx00 R/W 174
b/
x0xxxx10
b4

Chip Select Bus Mode Control

00F0 CS0_BMC Chip Select 0 Bus Mode Control 02 R/W 88
Register
00F1 CS1_BMC Chip Select 1 Bus Mode Control 02 R/W 88
Register
00F2 CS2_BMC Chip Select 2 Bus Mode Control 02 R/W 88
Register
00F3 CS3_BMC Chip Select 3 Bus Mode Control 02 R/W 88
Register

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Table 3. Register Map (Continued)

Address Reset CPU Page

(hex) Mnemonic Name (hex) Access No

Flash Memory Control

00F5 FLASH_KEY Flash Key Register 00 W 102
00F6 FLASH_DATA Flash Data Register XX R/W 103
00F7 FLASH_ADDR_U Flash Address Upper Byte Register 00 R/W 104
00F8 FLASH_CTL Flash Control Register 88 R/W 105
00F9 FLASH_FDIV Flash Frequency Divider Register 01 R/W 106
00FA FLASH_PROT Flash Write/Erase Protection Register FF R/W 107
00FB FLASH_IRQ Flash Interrupt Control Register 00 R/W 108
00FC FLASH_PAGE Flash Page Select Register 00 R/W 109
00FD FLASH_ROW Flash Row Select Register 00 R/W 111
00FE FLASH_COL Flash Column Select Register 00 R/W 112
00FF FLASH_PGCTL Flash Program Control Register 00 R/W 112

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eZ80® CPU Core

The eZ80® CPU is the first 8-bit CPU to support 16 MB linear addressing. Each software
module or task under a real-time executive or operating system operates in Z80®
compatible (64 KB) mode or full 24-bit (16 MB) address mode.
The CPU instruction set is a superset of the instruction sets for the Z80 and Z180 CPUs.
Z80 and Z180 programs are executed on an eZ80 CPU with little or no modification.

Features
The features of eZ80 CPU include:
• Code-compatible with Z80 and Z180 products
• 24-bit linear address space
• Single-cycle instruction fetch
• Pipelined fetch, decode, and execute
• Dual Stack Pointers for ADL (24-bit) and Z80 (16-bit) memory modes
• 24-bit CPU registers and Arithmetic Logic Unit (ALU)
• Debug support
• Nonmaskable Interrupt (NMI), plus support for 128 maskable vectored interrupts

New Instructions
The new instructions are listed below:
• Loads/unloads the I register with a 16-bit value. These new instructions are:
– LD I,HL (ED C7)
– LD HL,I (ED D7)
For more information on the CPU, its instruction set, and eZ80 programming, refer to
eZ80 CPU User Manual (UM0077), available on www.zilog.com.

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Reset
The Reset controller within the eZ80F91 device features a consistent reset function for all
types of resets that affects the system. A system reset, referred in this document as RESET,
returns the eZ80F91 to a defined state. All internal registers affected by a RESET return to
their default conditions. RESET configures the GPIO port pins as inputs and clears the
CPU’s Program Counter to 000000h. Program code execution ceases during RESET.
The events that cause a RESET are:
• Power-on reset (POR).
• Low-Voltage Brownout (VBO).
• External RESET pin assertion.
• Watchdog Timer (WDT) time-out when configured to generate a RESET.
• Real-Time Clock alarm with the CPU in low-power SLEEP mode.
• Execution of a Debug RESET command.

During RESET, an internal RESET mode timer holds the system in RESET for 1025
system clock (SCLK) cycles to allow sufficient time for the primary crystal oscillator to
stabilize. For internal RESET sources, the RESET mode timer begins incrementing on the
next rising edge of SCLK following deactivation of the signal that is initiating the RESET
event. For external RESET pin assertion, the RESET mode timer begins on the next rising
edge of SCLK following assertion of the RESET pin for three consecutive SCLK cycles.
Note: The default clock source for SCLK on RESET is the crystal input (XIN). See the CLK_MUX
values in the PLL Control Register 0, (see Table 154 on page 269).

External Reset Input and Indicator

The eZ80F91 RESET pin functions as both open-drain (active Low) RESET mode indica-
tor and active Low RESET input. When a RESET event occurs, the internal circuitry
begins driving the RESET pin Low. The RESET pin is held Low by the internal circuitry
until the internal RESET mode timer times out. If the external reset signal is released prior
to the end of the 1025 count time-out, program execution begins following the RESET
mode time-out. If the external reset signal is released after the end of the 1025 count time-
out, then program execution begins following release of the RESET input (the RESET pin
is High for four consecutive SCLK cycles).

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Power-On Reset
A POR occurs every time the supply voltage to the part rises from below the Voltage
Brownout threshold (VVBO) to above the POR voltage threshold (VPOR). The internal
bandgap-referenced voltage detector sends a continuous RESET signal to the Reset con-
troller until the supply voltage (VCC) exceeds the POR voltage threshold. After VCC rises
above VPOR, an on-chip analog delay element briefly maintains the RESET signal to the
Reset controller. After this analog delay element times out, the Reset controller holds the
eZ80F91 in RESET until the RESET mode timer expires. POR operation is displayed in
Figure 3. The signals in Figure 3 are not drawn to scale but for displaying purposes only.

VCC = 3.3V
VPOR
VVBO

VCC = 0.0V Program Execution

System Clock

Oscillator
Startup
Internal RESET
Signal

T ANA RESET mode timer delay

Figure 3. Power-On Reset Operation

Voltage Brownout Reset

If the supply voltage (VCC) drops below the VVBO after program execution begins, the
eZ80F91 device resets. The VBO protection circuitry detects the low supply voltage and
initiates a RESET via the Reset controller. The eZ80F91 remains in RESET until the sup-
ply voltage again returns above the POR voltage threshold (VPOR) and the Reset controller
releases the internal RESET signal. The VBO circuitry rejects short negative brown-out
pulses to prevent spurious RESET events.
VBO operation is displayed in Figure 4 on page 43. The signals in the figure are not drawn
to scale but for illustration purposes only.

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VCC = 3.3V VCC = 3.3V

VPOR
VVBO

Voltage
Program Execution Brown-out Program Execution

System Clock

Internal RESET
Signal

RESET mode
TANA timer delay

Figure 4. Voltage Brownout Reset Operation

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Low-Power Modes
The eZ80F91 device provides a range of power-saving features. The highest level of
power reduction is provided by SLEEP mode with all peripherals disabled, including
VBO. The next level of power reduction is provided by the HALT instruction. The most
basic level of power reduction is provided by the clock peripheral power-down registers.

SLEEP Mode
Execution of the CPU’s SLP instruction puts the eZ80F91 device into SLEEP mode. In
SLEEP mode, the operating characteristics are:
• The primary crystal oscillator is disabled.
• The system clock is disabled.
• The CPU is idle.
• The Program Counter (PC) stops incrementing.
• The 32 kHz crystal oscillator continues to operate and drives the real-time clock and
WDT (if WDT is configured to operate from the 32 kHz oscillator).

The CPU is brought out of SLEEP mode by any of the following operations:
• A RESET via the external RESET pin driven Low.
• A RESET via a real-time clock alarm.
• A RESET via a WDT time-out (if running out of the 32 kHz oscillator and configured
to generate a RESET on time-out).
• A RESET via execution of a Debug RESET command.
• A RESET via the Low-Voltage Brownout (VBO) detection circuit, if enabled.
After exiting SLEEP mode, the standard RESET delay occurs to allow the primary crystal
oscillator to stabilize. For more information, see Figure 4 on page 43.

HALT Mode
Execution of the CPU’s HALT instruction puts the eZ80F91 device into HALT mode.
In HALT mode, the operating characteristics are:
• The primary crystal oscillator is enabled and continues to operate.
• The system clock is enabled and continues to operate.
• The CPU is idle.

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• The PC stops incrementing.

The CPU is brought out of HALT mode by any of the following operations:
• A nonmaskable interrupt (NMI).
• A maskable interrupt.
• A RESET via the external RESET pin driven Low.
• A Watchdog Timer time-out (if, configured to generate either an NMI or RESET upon
time-out).
• A RESET via execution of a Debug RESET command.
• A RESET via the Low-Voltage Brownout detection circuit, if enabled.

To minimize current in HALT mode, the system clock must be gated-off for all unused
on-chip peripherals via the Clock Peripheral Power-Down Registers.

HALT Mode and the EMAC Function

When the CPU is in HALT mode, the eZ80F91 device’s EMAC block cannot be disabled
as other peripherals can. On receipt of an Ethernet packet, a maskable Receive interrupt is
generated by the EMAC block, just as it would be in a non-halt mode. Accordingly, the
processor wakes up and continues with the user-defined application.

Clock Peripheral Power-Down Registers

To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to
be blocked to unused on-chip peripherals. On RESET, all peripherals are enabled. The
clock to unused peripherals are gated off by setting the appropriate bit in the Clock Periph-
eral Power-Down Registers to 1. When powered down, the peripherals are completely dis-
abled. To re-enable, the bit in the Clock Peripheral Power-Down Registers must be cleared
to 0.
Additionally, the VBO_OFF bit of CLK_PPD2 is used to disable the VBO detection cir-
cuit and thereby significantly reduce DC current consumption (see Table 234 on page 341)
when this function is not required.
Many peripherals features separate enable/disable control bits that must be appropriately
set for operation. These peripheral specific enable/disable bits do not provide the same
level of power reduction as the Clock Peripheral Power-Down Registers. When powered
down, the individual peripheral control register is not accessible for Read or Write access,
(see Table 4 on page 47 and Table 5 on page 48).

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Table 4. Clock Peripheral Power-Down Register 1 (CLK_PPD1 = 00DBh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit Position Value Description

7 1 System clock to GPIO Port D is powered down.
GPIO_D_OFF Port D alternate functions do not operate correctly.
0 System clock to GPIO Port D is powered up.
6 1 System clock to GPIO Port C is powered down.
GPIO_C_OFF Port C alternate functions do not operate correctly.
0 System clock to GPIO Port C is powered up.
5 1 System clock to GPIO Port B is powered down.
GPIO_B_OFF Port B alternate functions do not operate correctly.
0 System clock to GPIO Port B is powered up.
4 1 System clock to GPIO Port A is powered down.
GPIO_A_OFF Port A alternate functions do not operate correctly.
0 System clock to GPIO Port A is powered up.
3 1 System clock to SPI is powered down.
SPI_OFF
0 System clock to SPI is powered up.
2 1 System clock to I2C is powered down.
I2C_OFF
0 System clock to I2C is powered up.
1 1 System clock to UART1 is powered down.
UART1_OFF
0 System clock to UART1 is powered up.
0 1 System clock to UART0 and IrDA endec is powered down.
UART0_OFF
0 System clock to UART0 and IrDA endec is powered up.

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Table 5. Clock Peripheral Power-Down Register 2 (CLK_PPD2 = 00DCh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
CPU Access R/W R/W R R R/W R/W R/W R/W
Note: R = Read Only; R/W = Read/Write.

Bit Position Value Description

7 1 PHI Clock output is disabled (output is high-impedance).
PHI_OFF
0 PHI Clock output is enabled.
6 VBO_OFF 1 Voltage Brownout detection circuit is disabled. This reduces
DC current consumption in situations where VBO detection is
not necessary. Power-On Reset functionality is not affected by
this setting.
0 VBO detection circuit is enabled.
[5:4] 000 Reserved.
3 1 System clock to TIMER3 is powered down.
TIMER3_OFF
0 System clock to TIMER3 is powered up.
2 1 System clock to TIMER2 is powered down.
TIMER2_OFF
0 System clock to TIMER2 is powered up.
1 1 System clock to TIMER1 is powered down.
TIMER1_OFF
0 System clock to TIMER1 is powered up.
0 1 System clock to TIMER0 is powered down.
TIMER0_OFF
0 System clock to TIMER0 is powered up.

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General-Purpose Input/Output
The eZ80F91 device features 32 General-Purpose Input/Output (GPIO) pins. The GPIO
pins are assembled as four 8-bit ports—Port A, Port B, Port C, and Port D. All port signals
are configured as either inputs or outputs. In addition, all the port pins are used as vectored
interrupt sources for the CPU.
The eZ80F91 microcontroller’s GPIO ports are slightly different from its eZ80®
predecessors. Specifically, Port A pins source 8 mA and sink 10 mA. In addition, the
Port B and C inputs now feature Schmitt-trigger input buffers.

GPIO Operation
GPIO operation is the same for all four GPIO ports (Ports A, B, C, and D). Each port
features eight GPIO port pins. The operating mode for each pin is controlled by four bits
that are divided between four 8-bit registers. The GPIO mode control registers are:
• Port x Data Register (Px_DR)
• Port x Data Direction Register (Px_DDR)
• Port x Alternate Register 1 (Px_ALT1)
• Port x Alternate Register 2 (Px_ALT2)
where x can be A, B, C, or D representing any of the four GPIO ports. The mode for each
pin is controlled by setting each register bit pertinent to the pin to be configured. For
example, the operating mode for port B pin 7 (PB7) is set by the values contained in
PB_DR[7], PB_DDR[7], PB_ALT1[7], and PB_ALT2[7].
The combination of the GPIO control register bits allows individual configuration of each
port pin for nine modes. In all modes, reading of the Port x Data register returns the
sampled state or level of the signal on the corresponding pin. Table 6 on page 50 lists the
function of each port signal based on these four register bits. After a RESET event, all
GPIO port pins are configured as standard digital inputs with the interrupts disabled.
In addition to the four mode control registers, each port has an 8-bit register, which is used
for clearing edge triggered interrupts. This register is the Port x Alternate register
0(Px_ALT0) where x can be A, B, C, or D representing the four GPIO ports. When a
GPIO pin is configured as an edge triggered interrupt, writing 1 to the corresponding bit of
the Px_ALT0 register clears the interrupt.

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Table 6. GPIO Mode Selection

GPIO Px_ALT2 Px_ALT1 Px_DDR Px_DR

Mode Bits7:0 Bits7:0 Bits7:0 Bits7:0 Port Mode Output
0 0 0 0 Output 0
1
0 0 0 1 Output 1
0 0 1 0 Input from pin High impedance
2
0 0 1 1 Input from pin High impedance
0 1 0 0 Open-drain output 0
3
0 1 0 1 Open-drain I/O High impedance
0 1 1 0 Open-source I/O High impedance
4
0 1 1 1 Open-source output 1
5 1 0 0 0 Reserved High impedance
6 1 0 0 1 Interrupt—dual edge-triggered High impedance
1 0 1 0 Alternate function controls port I/O.
7
1 0 1 1 Alternate function controls port I/O.
1 1 0 0 Interrupt—active Low High impedance
8
1 1 0 1 Interrupt—active High High impedance
1 1 1 0 Interrupt—falling edge-triggered High impedance
9
1 1 1 1 Interrupt—rising edge-triggered High impedance

Figure 5 on page 53 and Figure 6 on page 53 display the simplified block diagrams of the
GPIO port pin for the various modes.
GPIO Mode 1—Output
The port pin is configured as a standard digital output pin. The value written to the Port x
Data register (Px_DR) is driven on the pin.
GPIO Mode 2—Input
The port pin is configured as a standard digital input pin. The output is high impedance.
The value stored in the Port x Data register produces no effect. As in all modes, a read
from the Port x Data register returns the pin’s value. GPIO mode 2 is the default operating
mode following a RESET.
GPIO Mode 3—Open Drain
The port pin is configured as open-drain Input/Output. The GPIO pins do not feature an
internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN mode,

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an external pull-up resistor must connect the pin to the supply voltage. Writing 0 to the
Port x Data register outputs a Low at the pin. Writing 1 to the Port x Data register results in
high-impedance output.
GPIO Mode 4—Open Source
The port pin is configured as open-source I/O. The GPIO pins do not feature an internal
pull-down to the supply ground. To employ the GPIO pin in OPEN-SOURCE mode, an
external pull-down resistor must connect the pin to the supply ground. Writing 1 to the
Port x Data register outputs a High at the pin. Writing 0 to the Port x Data register results
in a high-impedance output.
GPIO Mode 5—Reserved
This mode produces a high-impedance output.
GPIO Mode 6—Dual Edge Triggered
The port pin is configured for dual edge-triggered interrupt mode. Both a rising and a
falling edge on this pin cause an interrupt request to be sent to the CPU. To select this
mode from the default mode (mode 2), you must:
1. Set Px_DR=1
2. Set Px_ALT2=1
3. Set Px_ALT1=0
4. Set Px_DDR=0
Writing a 1 to the Port x ALT0 register bit position corresponding to the interrupt request
clears the interrupt.
GPIO Mode 7—Alternate Functions
The port pin is configured to pass control over to the alternate (secondary) functions
assigned to the pin. For example, the alternate mode function for PC5 is the DSR1 input
signal to UART1 and the alternate mode function for PB4 is the timer 3 input capture.
When GPIO mode 7 is enabled, the pin output data and pin high-impedance control is
obtained from the alternate function's data output and high-impedance control,
respectively. The value in the Port x Data register produces no effect on operation. Input
signals are sampled by the system clock before being passed to the alternate input
function.
If the alternate function of a pin is an input and alternate function mode for that pin is not
enabled, the input is driven to a default non-asserted value. For example, in alternate mode
function, PC5 drives the DSR1 signal to UART1. As this signal is Low level true, the
DSR1 signal to UART1 is driven to 1 when PC5 is not in alternate mode function.

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GPIO Mode 8—Level Sensitive Interrupt

The port pin is configured for level-sensitive interrupt mode. The value in the Port x Data
register determines if a low or high-level causes an interrupt request. An interrupt request
is generated when the level at the pin is the same as the level stored in the Port x Data
register. The port pin value is sampled by the system clock. The input pin must be held at
the selected interrupt level for a minimum of two system clock periods to initiate an
interrupt. The interrupt request remains active as long as this condition is maintained at the
external source. For example, if a port pin is configured as a low-level-sensitive interrupt,
the interrupt request will be asserted when the pin has been low for two system clocks and
remains active until the pin goes high.
Configuring a pin for mode 8 requires a transition through mode 9 (edge triggered mode).
To avoid the possibility of an unwanted interrupt while transition through mode 9, the
following steps must be taken to select mode 8 when starting from the default mode (mode
2):
1. Disable interrupts
2. Set Px_DR = 0 (low level interrupt) or 1 (high level interrupt)
3. Set Px_ALT2 = 1
4. Set Px_ALT1 =1 (mode 9)
5. Set Px_DDR = 0 (mode 8)
6. Set Px_ALT0 = 1 (to clear possible mode 9 interrupt)
7. Enable interrupts
GPIO Mode 9—Edge Triggered Interrupt
The port pin is configured for single edge triggered interrupt mode. The value in the Port x
Data register determines whether a positive or negative edge causes an interrupt request.
Writing 0 to the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. Writing 1 to the Port x Data register bit sets the selected pin to
generate an interrupt request for rising edges. The interrupt request remains active until 1
is written to the corresponding bit of the Port x Alternate register 0. To select mode 9 from
the default mode (mode 2), you must:
1. Set the Port x Data register
2. Set Px_ALT2 = 1
3. Set Px_ALT1 = 1
4. Set Px_DDR=1

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Simplified GPIO Port Block Diagram for Modes 2, 6, 7(input), 8, and 9

GPIO Port Pin

Mode 2 GPIO Output Buffer

Mode 6
Mode 8
Mode 9 Px_DR*
Mode 7(Input) ENB
Input to chip
D Q D Q
Tristated for
modes 2,6,8,9
and 7(Input) SysClock
Alternate
Function
Input
Default Value

Mode 7(Input)

Clear Interrupt Interrupt Interrupt

Logic

Modes 6,8,9
* Reading from the Px_DR returns
the value stored in this register

Figure 5. GPIO Port Pin Block Diagram for Input and Interrupt Modes

Simplified GPIO Port Block Diagram for Modes 1, 3, 4, and 7 (Output)

VDD

Px_DR* Mode 4 External

Data Pull-up resistor
D Q GPIO Output Buffer required for
System Clock GPIO Port Mode 3
Pin (open drain)
Q ENB
Mode 3

Mode 1
External Pull-down resistor
Mode 7 (Output) required for Mode 4
(Open source)

Alternate Function Output

* Writing to the Px_DR stores

the value in this register

Figure 6. GPIO Port Pin Block Diagram for Output and Input/Output Mode

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GPIO Interrupts
Each port pin is used as an interrupt source. Interrupts are either level- or edge-triggered.

Level-Triggered Interrupts
When the port is configured for level-triggered interrupts (mode 8), the corresponding port
pin is open-drain. An interrupt request is generated when the level at the pin is the same as
the level stored in the Port x Data register. The port pin value is sampled by the system
clock. The input pin must be held at the selected interrupt level for a minimum of two
clock periods to initiate an interrupt. The interrupt request remains active as long as this
condition is maintained at the external source.
For example, if PA3 is programmed for low-level interrupt and the pin is forced Low for
two clock cycles, an interrupt request signal is generated from that port pin and sent to the
CPU. The interrupt request signal remains active until the external device driving PA3
forces the pin high. The CPU must be enabled to respond to interrupts for the interrupt
request signal to be acted upon.

Edge Triggered Interrupts

When the port is configured for edge triggered interrupts, the corresponding port pin is
open-drain. If the pin receives the correct edge from an external device, the port pin
generates an interrupt request signal to the CPU.
When configured for dual-edge triggered interrupt mode (GPIO mode 6), both a rising and
a falling edge on the pin cause an interrupt request to be sent to the CPU. To select mode 6
from the default mode (mode 2), you must:
1. Set Px_DR = 1
2. Set Px_ALT2 =1
3. Set Px_ALT1= 0
4. Set Px_DDR = 0
When configured for single-edge triggered interrupt mode (GPIO mode 9), the value in
the Port x Data register determines whether a positive or negative edge causes an interrupt
request. 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges. To select mode 9 from the default mode (mode 2),
you must:
1. Set Px_DR = 1
2. Set Px_ALT2 = 1
3. Set Px_ALT = 1
4. Set Px_DDR = 1

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Edge triggered interrupts are cleared by writing 1 to the corresponding bit of the Px_ALT0
register. For example, if PD4 has been set up to generate an edge triggered interrupt, the
interrupt is cleared by writing a 1 to Px_ALT0[4].

GPIO Control Registers

Each GPIO port has four registers that controls its operation. The operating mode of each
bit within a port is selected by writing to the corresponding bits of these four registers as
listed in Table 6 on page 50. These four registers are Port Data register (Px_DR), Port Data
Direction register (Px_DDR), Port Alternate register 1 (PX_ALT1), and Port Alternate
register 2 (Px_ALT2). In addition to these four control registers, each port has a Port
Alternate register 0 (Px_ALT0), which is used for clearing edge triggered interrupts.

Port x Data Registers

When the port pins are configured for one of the output modes, the data written to the
Port x Data registers (see Table 7) is driven on the corresponding pins. In all modes,
reading from the Port x Data registers always returns the sampled current value of the
corresponding pins. When the port pins are configured for edge triggered interrupts or
level-sensitive interrupts, the value written to the Port x Data register bit selects the
interrupt edge or interrupt level (for more details on GPIO mode selection, see Table 6 on
page 50).

Table 7. Port x Data Registers

(PA_DR = 0096h, PB_DR = 009Ah, PC_DR = 009Eh, PD_DR = 00A2h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: X = Undefined; R/W = Read/Write.

Port x Data Direction Registers

In conjunction with the other GPIO Control registers, the Port x Data Direction registers
(see Table 8) control the operating modes of the GPIO port pins. For more details on GPIO
mode selection, see Table 6 on page 50.

Table 8. Port x Data Direction Registers

(PA_DDR = 0097h, PB_DDR = 009Bh, PC_DDR = 009Fh, PD_DDR = 00A3h)

Bit 7 6 5 4 3 2 1 0
Reset 1 1 1 1 1 1 1 1

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

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Port x Alternate Register 0

The Port x Alternate register 0 is used to clear edge triggered interrupts. If an edge
triggered interrupt occurs, writing 1 to the corresponding bit of this register will clear it.

Table 9. Port x Alternate Registers 0

(PA_ALT0 = 00A6h, PB_ALT0 = 00A7h, PC_ALT0 = 00CEh, PD_ALT0 = 00CFh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
CPU Access W W W W W W W W
Note: W = Write only

Port x Alternate Register 1

In conjunction with the other GPIO Control registers, the Port x Alternate Register 1 (see
Table 10) controls the operating modes of the GPIO port pins. For more details on GPIO
mode selection, see Table 6 on page 50.

Table 10. Port x Alternate Registers 1

(PA_ALT1 = 0098h, PB_ALT1 = 009Ch, PC_ALT1 = 00A0h, PD_ALT1 = 00A4h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Port x Alternate Register 2

In conjunction with the other GPIO Control registers, the Port x Alternate Register 2 (see
Table 11) controls the operating modes of the GPIO port pins. For more details on GPIO
mode selection, see Table 6 on page 50.

Table 11. Port x Alternate Registers 2

(PA_ALT2 = 0099h, PB_ALT2 = 009Dh, PC_ALT2 = 00A1h, PD_ALT2 = 00A5h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

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Interrupt Controller
The interrupt controller on the eZ80F91 device routes the interrupt request signals from
the internal peripherals, external devices (via the internal port I/O), and the nonmaskable
interrupt (NMI) pin to the CPU.

Maskable Interrupts
On the eZ80F91 device, all maskable interrupts use the CPU’s vectored interrupt function.
The size of I register is modified to 16 bits in the eZ80F91 device differing from the previ-
ous versions of eZ80® CPU, to allow for a 16 MB range of interrupt vector table place-
ment. Additionally, the size of the IVECT register is increased from 8 bits to 9 bits to
provide an interrupt vector table that is expanded and more easily integrated with other
interrupts.
The vectors are 4 bytes (32 bits) apart, even though only 3 bytes (24 bits) are required.
A fourth byte is implemented for both programmability and expansion purposes.
Starting the interrupt vectors at 40h allows for easy implementation of the interrupt con-
troller vectors with the RST vectors. Table 12 lists the interrupt vector sources by priority
for each of the maskable interrupt sources. The maskable interrupt sources are listed in
order of their priority, with vector 40h being the highest-priority interrupt. In ADL mode,
the full 24-bit interrupt vector is located at starting address {I[15:1], IVECT[8:0]}, where
I[15:0] is the CPU’s Interrupt Page Address register.

Table 12. Interrupt Vector Sources by Priority

Priority Vector Source Priority Vector Source

0 040h EMAC Rx 24 0A0h Port B 0
1 044h EMAC Tx 25 0A4h Port B 1
2 048h EMAC SYS 26 0A8h Port B 2
3 04Ch PLL 27 0ACh Port B 3
4 050h Flash 28 0B0h Port B 4
5 054h Timer 0 29 0B4h Port B 5
6 058h Timer 1 30 0B8h Port B 6
7 05Ch Timer 2 31 0BCh Port B 7
8 060h Timer 3 32 0C0h Port C 0
9 064h Unused* 33 0C4h Port C 1
10 068h Unused* 34 0C8h Port C 2

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Table 12. Interrupt Vector Sources by Priority (Continued)

Priority Vector Source Priority Vector Source

11 06Ch RTC 35 0CCh Port C 3
12 070h UART 0 36 0D0h Port C 4
13 074h UART 1 37 0D4h Port C 5
14 078h I2C 38 0D8h Port C 6
15 07Ch SPI 39 0DCh Port C 7
16 080h Port A 0 40 0E0h Port D 0
17 084h Port A 1 41 0E4h Port D 1
18 088h Port A 2 42 0E8h Port D 2
19 08Ch Port A 3 43 0ECh Port D 3
20 090h Port A 4 44 0F0h Port D 4
21 094h Port A 5 45 0F4h Port D 5
22 098h Port A 6 46 0F8h Port D 6
23 09Ch Port A 7 47 0FCh Port D 7
Note: *The vector addresses 064h and 068h are left unused to avoid conflict with the nonmaskable
interrupt (NMI) address 066h. The NMI is prioritized higher than all maskable interrupts.

The program must store the interrupt service routine starting address in the
four-byte interrupt vector locations. For example in ADL mode, the three-byte address for
the SPI interrupt service routine is stored at {I[15:1], 07Ch}, {I[15:1], 07Dh}, and {I[15:1],
07Eh}. In Z80® mode, the two-byte address for the SPI interrupt service routine is stored at
{MBASE[7:0], I[7:1], 07Ch} and {MBASE, I[7:1], 07Dh}. The LSB is stored at the lower
address.
When one or more interrupt requests (IRQs) become active, an interrupt request is
generated by the interrupt controller and sent to the CPU. The corresponding 9-bit
interrupt vector for the highest-priority interrupt is placed on the 9-bit interrupt vector bus,
IVECT[8:0]. The interrupt vector bus is internal to the eZ80F91 device and is therefore
externally not visible. The response time of the CPU to an interrupt request is a function of
the current instruction being executed as well as the number of wait states being asserted.
The interrupt vector, {I[15:1], IVECT[8:0]} is visible on the address bus (ADDR[23:0]),
when the interrupt service routine begins. The response of the CPU to a vectored interrupt
on the eZ80F91 device is listed in Table 13 on page 59. Interrupt sources are required to be
active until the Interrupt Service Routine (ISR) starts.
Note: The lower bit of the I register is replaced with the MSB of the IVECT from the interrupt con-
troller. As a result, the interrupt vector table is required to be placed onto a 512-byte

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boundary. Setting the LSB of the I register produces no effect on the interrupt vector
address.

Table 13. Vectored Interrupt Operation

Memory ADL MADL

Mode Bit Bit Operation
Z80® Mode 0 0 Read the LSB of the interrupt vector placed on the internal vectored interrupt
bus, IVECT [8:0], by the interrupting peripheral.
IEF1 ← 0
IEF2 ← 0
The Starting Program Counter is effective {MBASE, PC[15:0]}.
Push the 2-byte return address PC[15:0] onto the ({MBASE,SPS}) stack.
The ADL mode bit remains cleared to 0.
The interrupt vector address is located at { MBASE, I[7:1], IVECT[8:0] }.
PC[23:0] ← ( { MBASE, I[7:1], IVECT[8:0] } ).
The interrupt service routine must end with RETI.
ADL Mode 1 0 Read the LSB of the interrupt vector placed on the internal vectored interrupt
bus, IVECT [8:0], by the interrupting peripheral.
IEF1 ← 0
IEF2 ← 0
The Starting Program Counter is PC[23:0].
Push the 3-byte return address, PC[23:0], onto the SPL stack.
The ADL mode bit remains set to 1.
The interrupt vector address is located at { I[15:1], IVECT[8:0] }.
PC[23:0] ← ( { I[15:1], IVECT[8:0] } ).
The interrupt service routine must end with RETI.
Z80 Mode 0 1 Read the LSB of the interrupt vector placed on the internal vectored interrupt
bus, IVECT[8:0], bus by the interrupting peripheral.
• IEF1 ← 0
• IEF2 ← 0
• The Starting Program Counter is effective {MBASE, PC[15:0]}.
• Push the 2-byte return address, PC[15:0], onto the SPL stack.
• Push a 00h byte onto the SPL stack to indicate an interrupt from Z80 mode
(because ADL = 0).
• Set the ADL mode bit to 1.
• The interrupt vector address is located at { I[15:1], IVECT[8:0] }.
• PC[23:0] ← ( { I[15:1], IVECT[8:0] } ).
• The interrupt service routine must end with RETI.L

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Table 13. Vectored Interrupt Operation (Continued)

Memory ADL MADL

Mode Bit Bit Operation
ADL Mode 1 1 Read the LSB of the interrupt vector placed on the internal vectored interrupt
bus, IVECT [8:0], by the interrupting peripheral.
• IEF1 ← 0
• IEF2 ← 0
• The Starting Program Counter is PC[23:0].
• Push the 3-byte return address, PC[23:0], onto the SPL stack.
• Push a 01h byte onto the SPL stack to indicate a restart from ADL mode
(because ADL = 1).
• The ADL mode bit remains set to 1.
• The interrupt vector address is located at {I[15:1], IVECT[8:0]}.
• PC[23:0] ← ( { I[15:1], IVECT[8:0] } ).
• The interrupt service routine must end with RETI.L

Interrupt Priority Registers

The eZ80F91 provides two interrupt priority levels for the maskable interrupts. The default
priority (or Level 0) is listed in Table 14 on page 61. The default priority of any maskable
interrupt increases to Level 1 (a higher priority than any Level 0 interrupt) by setting the
appropriate bit in the Interrupt Priority registers as listed in Table 14 on page 61.

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Table 14. Interrupt Priority Registers (INT_P0 = 0010h, INT_P1 = 0011h, INT_P2 = 0012h, INT_P3
= 0013h, INT_P4 = 0014h, INT_P5 = 0015h)

Bit 7 6 5 4 3 2 1 0
INT_P0 Reset 0 0 0 0 0 0 0 0
INT_P1 Reset 0 0 0 0 0 0* 0* 0
INT_P2 Reset 0 0 0 0 0 0 0 0
INT_P3 Reset 0 0 0 0 0 0 0 0
INT_P4 Reset 0 0 0 0 0 0 0 0
INT_P5 Reset 0 0 0 0 0 0 0 0
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: X = Undefined; R/W = Read/Write, *Unused.

Bit
Position Value Description
7 0 Default Interrupt Priority
INT_PX
1 Level One Interrupt Priority
6 0 Default Interrupt Priority
INT_PX
1 Level One Interrupt Priority
5 0 Default Interrupt Priority
INT_PX
1 Level One Interrupt Priority
4 0 Default Interrupt Priority
INT_PX
1 Level One Interrupt Priority
3 0 Default Interrupt Priority
INT_PX
1 Level One Interrupt Priority
2 0 Default Interrupt Priority
INT_PX
1 Level One Interrupt Priority
1 0 Default Interrupt Priority
INT_PX
1 Level One Interrupt Priority
0 0 Default Interrupt Priority
INT_PX
1 Level One Interrupt Priority

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The Interrupt Vector Priority Control bits are listed in Table 15.

Table 15. Interrupt Vector Priority Control Bits

Priority Control Priority Control

Bit Vector Source Bit Vector Source
INT_P0[0] 040h EMAC Rx INT_P3[0] 0A0h Port B 0
INT_P0[1] 044h EMAC Tx INT_P3[1] 0A4h Port B 1
INT_P0[2] 048h EMAC SYS INT_P3[2] 0A8h Port B 2
INT_P0[3] 04Ch PLL INT_P3[3] 0ACh Port B 3
INT_P0[4] 050h Flash INT_P3[4] 0B0h Port B 4
INT_P0[5] 054h Timer 0 INT_P3[5] 0B4h Port B 5
INT_P0[6] 058h Timer 1 INT_P3[6] 0B8h Port B 6
INT_P0[7] 05Ch Timer 2 INT_P3[7] 0BCh Port B 7
INT_P1[0] 060h Timer 3 INT_P4[0] 0C0h Port C 0
INT_P1[1] 064h Unused* INT_P4[1] 0C4h Port C 1
INT_P1[2] 068h Unused* INT_P4[2] 0C8h Port C 2
INT_P1[3] 06Ch RTC INT_P4[3] 0CCh Port C 3
INT_P1[4] 070h UART 0 INT_P4[4] 0D0h Port C 4
INT_P1[5] 074h UART 1 INT_P4[5] 0D4h Port C 5
INT_P1[6] 078h I2C INT_P4[6] 0D8h Port C 6
INT_P1[7] 07Ch SPI INT_P4[7] 0DCh Port C 7
INT_P2[0] 080h Port A 0 INT_P5[0] 0E0h Port D 0
INT_P2[1] 084h Port A 1 INT_P5[1] 0E4h Port D 1
INT_P2[2] 088h Port A 2 INT_P5[2] 0E8h Port D 2
INT_P2[3] 08Ch Port A 3 INT_P5[3] 0ECh Port D 3
INT_P2[4] 090h Port A 4 INT_P5[4] 0F0h Port D 4
INT_P2[5] 094h Port A 5 INT_P5[5] 0F4h Port D 5
INT_P2[6] 098h Port A 6 INT_P5[6] 0F8h Port D 6
INT_P2[7] 09Ch Port A 7 INT_P5[7] 0FCh Port D 7
Note: *The vector addresses 064h and 068h are left unused to avoid conflict with the NMI vector address 066h.

If more than one maskable interrupt is prioritized to a higher level (Level 1), the higher-
priority interrupts follow the priority order as listed in Table 14 on page 61. For example,

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Table 16 lists the maskable interrupts 044h (EMAC Tx), 084h (Port A 1), and 06Ch
(RTC) as elevated to priority Level 1. Table 17 lists the new interrupt priority for the top
ten maskable interrupts.

Table 16. Example: Maskable Interrupt Priority

Priority
Register Setting Description
INT_P0 02h Increase 044h (EMAC Tx) to Priority Level 1
INT_P1 08h Increase 06Ch (RTC) to Priority Level 1
INT_P2 02h Increase 084h (Port A1) to Priority Level 1
INT_P3 00h Default priority
INT_P4 00h Default priority
INT_P5 00h Default priority

Table 17. Example: Priority Levels for Maskable Interrupts

Priority Vector Source

0 044h EMAC Tx
1 06Ch RTC
2 084h Port A 1
3 040h EMAC Rx
4 048h EMAC SYS
5 04Ch PLL
6 050h Flash
7 054h Timer 0
8 058h Timer 1
9 05Ch Timer 2

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GPIO Port Interrupts

All interrupts are latched. In effect, an interrupt is held even if the interrupt occurs while
another interrupt is being serviced and interrupts are disabled, or if the interrupt is of a
lower priority. However, before the latched ISR completes its task or re-enables interrupts,
the ISR must clear the interrupt. For on-chip peripherals, the interrupt is cleared when the
data register is accessed. For GPIO-level interrupts, the interrupt signal must be removed
before the ISR completes its task. For GPIO-edge interrupts (single and dual), the interrupt
is cleared by writing a 1 to the corresponding bit position in the Px_ALT0 register. See
Edge Triggered Interrupts on page 54.
Note: For F91 devices with a ZDI or JTAG revision less than 2, care must be taken using a GPIO
data register when it is configured for interrupts. For edge-interrupt modes (modes 6 and
9) as discussed earlier, writing 1 clears the interrupt. However, 1 in the data register also
conveys a particular configuration. For example, when the data register Px_DR is set first
followed by the Px_ALT2, Px_ALT1, and Px_DDR registers, then the configuration is per-
formed correctly. Writing 1 to the register later to clear interrupts does not change the con-
figuration. For F91 devices with a ZDI or JTAG revision 2 or later, the clearing of
interrupts is accomplished through the new Px_ALT0 registers and the above problem does
not exist.

In mode 9 operation, if the GPIO is already configured for mode 9 and if the trigger edge
must be changed (from falling to rising or from rising to falling), then the configuration
must be changed to another mode, such as Mode 2, and then changed back to mode 9. For
example, enter mode 2 by writing the registers in the sequence PxDR, Px_ALT2, Px_ALT1,
and Px_DDR. Next, change back to mode 9 by writing the registers in the sequence PxDR,
Px_ALT2, Px_ALT1, and Px_DDR.

In Mode 8 operation, if the GPIO is configured for level-sensitive interrupts, a Write value
to Px_DR after configuration must be the same Write value used when configuring the
GPIO.

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Chip Selects and Wait States

The eZ80F91 generates four chip selects for external devices. Each chip select is pro-
grammed to access either the memory space or the I/O space. The memory chip selects are
individually programmed on a 64 KB boundary. Each I/O chip selects choose a 256-byte
section of I/O space. In addition, each chip select is programmed for up to 7 Wait states.

Memory and I/O Chip Selects

Each of the chip selects are enabled either for the memory address space or the I/O address
space, but not both. To select the memory address space for a particular chip select,
CSX_IO (CSx_CTL[4]) must be reset to 0. To select the I/O address space for a particular
chip select, CSX_IO must be set to 1. After RESET, the default is for all chip selects to be
configured for the memory address space. For either the memory address space or the I/O
address space, the individual chip selects must be enabled by setting CSX_EN
(CSx_CTL[3]) to 1.

Memory Chip Select Operation

Operation of each of the memory chip select is controlled by three control registers. To
enable a particular memory chip select, the following conditions must be satisfied:
• The chip select is enabled by setting CSx_EN to 1.
• The chip select is configured for memory by clearing CSX_IO to 0.
• The address is in the associated chip select range:
CSx_LBR[7:0] ≤ ADDR[23:16] ≤ CSx_UBR[7:0].

• On-chip Flash is not configured for the same address space, because on-chip Flash is
prioritized higher than all memory chip selects.
• On-chip RAM is not configured for the same address space, because on-chip RAM is
prioritized higher than Flash and all memory chip selects.
• No higher priority (lower number) chip select meets the above conditions.
• A memory access instruction must be executing.

If all the preceding conditions are satisfied to generate a memory chip select, then the fol-
lowing results occur:
• The appropriate chip select—CS0, CS1, CS2, or CS3 is asserted (driven Low).
• MREQ is asserted (driven Low).
• Depending on the instruction either RD or WR is asserted (driven Low).

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If the upper and lower bounds are set to the same value (CSx_UBR = CSx_LBR), then a
particular chip select is valid for a single 64 KB page.

Memory Chip Select Priority

A lower-numbered chip select is granted priority over a higher-numbered chip select. For
example, if the address space of chip select 0 overlaps the chip select 1 address space, then
chip select 0 is active. If the address range programmed for any chip select signal overlaps
with the address of internal memory, the internal memory is accorded higher priority. If
the particular chip select(s) are configured with an address range that overlaps with an
internal memory address and when the internal memory is accessed, the chip select signal
is not asserted.

Reset States
On RESET, chip select 0 is active for all addresses, because its Lower Bound register
resets to 00h and its Upper Bound register resets to FFh. All the other chip select Lower
and Upper Bound registers reset to 00h.

Memory Chip Select Example

The use of Memory chip selects is displayed in Figure 7 on page 67. The associated con-
trol register values are listed in Table 18 on page 67. In this example, all four chip selects
are enabled and configured for memory addresses. Also, CS1 overlaps with CS0. Because
CS0 is prioritized higher than CS1, CS1 is not active for much of its defined address
space.

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Memory
Location
CS3_UBR = FFh FFFFFFh
CS3 Active
3 MB Address Space
CS3_LBR = D0h D00000h
CS2_UBR = CFh CFFFFFh
CS2 Active
3 MB Address Space
CS2_LBR = A0h A00000h
CS1_UBR = 9Fh 9FFFFFh
CS1 Active
2 MB Address Space
800000h
CS0_UBR = 7Fh 7FFFFFh

CS0 Active
8 MB Address Space

CS0_LBR = CS1_LBR = 00h 000000h

Figure 7. Example: Memory Chip Select

Table 18. Example: Register Values for Figure 7 Memory Chip Select

Chip CSx_CTL[3] CSx_CTL[4]

Select CSx_EN CSx_IO CSx_LBR CSx_UBR Description
CS0 1 0 00h 7Fh CS0 is enabled as a Memory chip
select. Valid addresses range from
000000h–7FFFFFh.
CS1 1 0 00h 9Fh CS1 is enabled as a Memory chip
select. Valid addresses range from
800000h–9FFFFFh.
CS2 1 0 A0h CFh CS2 is enabled as a Memory chip
select. Valid addresses range from
A00000h–CFFFFFh.
CS3 1 0 D0h FFh CS3 is enabled as a Memory chip
select. Valid addresses range from
D00000h–FFFFFFh.

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Input/Output Chip Select Operation

I/O chip selects will be active only when the CPU is performing I/O instructions. Because
the I/O space is separate from the memory space in the eZ80F91 device, a conflict
between I/O and memory addresses never occurs.
The eZ80F91 supports a 16-bit I/O address. The I/O chip select logic decodes the High
byte of the I/O address, ADDR[15:8]. Because the upper byte of the address bus,
ADDR[23:16], is ignored, the I/O devices are always accessed from memory mode (ADL
or Z80®). The MBASE offset value used for setting the Z80 MEMORY mode page is also
always ignored.
Four I/O chip selects are available with the eZ80F91 device. To generate a particular I/O
chip select, the following conditions must be satisfied:
• The chip select is enabled by setting CSx_EN to 1.
• The chip select is configured for I/O by setting CSX_IO to 1.
• An I/O chip select address match occurs—ADDR[15:8] = CSx_LBR[7:0].
• No higher-priority (lower-number) chip select meets the above conditions.
• The I/O address is not within the on-chip peripheral address range 0000h–00FFh.
On-chip peripheral registers assume priority for all addresses where:
0000h ≤ ADDR[15:0] ≤ 00FFh

• An I/O instruction must be executing.

If all of the foregoing conditions are met to generate an I/O chip select, then the following
results occur:
• The appropriate chip select—CS0, CS1, CS2, or CS3 is asserted (driven Low).
• IORQ is asserted (driven Low).
• Depending on the instruction, either RD or WR is asserted (driven Low).

Wait States
For each of the chip selects, programmable Wait states are asserted to provide external
devices with additional clock cycles to complete their Read or Write operations. The
number of wait states for a particular chip select is controlled by the 3-bit field
CSx_WAIT (CSx_CTL[7:5]). The Wait states are independently programmed to provide 0
to 7 Wait states for each chip select. The Wait states idle the CPU for the specified number
of system clock cycles.

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WAIT Input Signal

Similar to the programmable wait states, an external peripheral drives the WAIT input pin
to force the CPU to provide additional clock cycles to complete its Read or Write opera-
tion. Driving the WAIT pin Low stalls the CPU. The CPU resumes operation on the first
rising edge of the internal system clock following deassertion of the WAIT pin.
Caution: If the WAIT pin is to be driven by an external device, the corresponding chip select for
the device must be programmed to provide at least one wait state. Due to input sampling
of the WAIT input pin (see Figure 8), one programmable wait state is required to allow
the external peripheral sufficient time to assert the WAIT pin. It is recommended that the
corresponding chip select for the external device be programmed to provide the maxi-
mum number of wait states (seven).

Wait eZ80
D Q CPU
Pin

System Clock

Figure 8. Wait Input Sampling Block Diagram

An example of wait state operation is illustrated in Figure 9 on page 70. In this example,
the chip select is configured to provide a single wait state. The external peripheral
accessed drives the WAIT pin Low to request assertion of an additional wait state. If the
WAIT pin is asserted for additional system clock cycles, wait states are added until the
WAIT pin is deasserted (active High).

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TCLK TWAIT

SCLK

ADDR[23:0]

DATA[7:0]
(output)

CSx

MREQ

RD

INSTRD

Figure 9. Example: Wait State Read Operation

Chip Selects During Bus Request/Bus Acknowledge Cycles

When the CPU relinquishes the address bus to an external peripheral in response to an
external bus request (BUSREQ), it drives the bus acknowledge pin (BUSACK) Low. The
external peripheral then drives the address bus (and data bus). The CPU continues to gen-
erate chip select signals in response to the address on the bus. External devices cannot
access the internal registers of the eZ80F91.

Bus Mode Controller

The bus mode controller allows the address and data bus timing and signal formats of the
eZ80F91 to be configured to connect with external devices compatible with eZ80®, Z80®,
Intel™ and Motorola microcontrollers. Bus modes for each of the chip selects are config-
ured independently using the Chip Select Bus Mode Control Registers. The number of

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CPU system clock cycles per bus mode state is also independently programmable. For
Intel bus mode, multiplexed address and data are selected in which both the lower byte of
the address and the data byte use the data bus, DATA[7:0]. Each of the bus modes are
explained in the following sections.

eZ80® Bus Mode

Chip selects configured for eZ80 bus mode do not modify the bus signals from the CPU.
The timing diagrams for external Memory and I/O Read and Write operations are shown in
the AC Characteristics on page 344. The default mode for each chip select is eZ80 mode.

Z80® Bus Mode

Chip selects configured for Z80 mode modify the eZ80 bus signals to match the Z80 micro-
processor address and data bus interface signal format and timing. During Read operations,
the Z80 Bus mode employs three states—T1, T2, and T3 as listed in Table 19.

Table 19. Z80 Bus Mode Read States

STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the address bus and
the associated chip select signal is asserted.
STATE T2 During State T2, the RD signal is asserted. Depending on the instruction, either the MREQ
or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU system
clock cycle prior to the end of State T2, additional Wait states (TWAIT) are asserted until the
WAIT pin is driven High.
STATE T3 During State T3, no bus signals are altered. The data is latched by the eZ80F91 at the rising
edge of the CPU system clock at the end of State T3.

During Write operations, Z80 Bus mode employs three states—T1, T2, and T3 as listed in
Table 20.

Table 20. Z80 Bus Mode Write States

STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the address bus, and
the associated chip select signal is asserted.
STATE T2 During State T2, the WR signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU
system clock cycle prior to the end of State T2, additional wait states (TWAIT) are asserted
until the WAIT pin is driven High.
STATE T3 During State T3, no bus signals are altered.

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Z80® bus mode Read and Write timing is displayed in Figure 10 and Figure 11 on page
73. The Z80 bus mode states are configured for 1 to 15 CPU system clock cycles. In the
figures, each Z80 bus mode state is two CPU system clock cycles in duration. The figures
also display the assertion of 1 wait state (TWAIT) by the external peripheral during each
Z80 bus mode cycle.

T1 T2 TCLK T3

System Clock

ADDR[23:0]

DATA[7:0]

CSx

RD

WAIT

WR

MREQ
or IORQ

Figure 10. Example: Z80 Bus Mode Read Timing

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T1 T2 TCLK T3

System Clock

ADDR[23:0]

DATA[7:0]

CSx

RD

WAIT

WR

MREQ
or IORQ

Figure 11. Example: Z80® Bus Mode Write Timing

Intel Bus Mode

Chip selects configured for Intel bus mode modify the CPU bus signals to duplicate a
four-state memory transfer similar to that found on Intel-style microcontrollers. The bus
signals and eZ80F91 pins are mapped as displayed in Figure 12 on page 74. In Intel bus
mode, you select either multiplexed or nonmultiplexed address and data buses. In
nonmultiplexed operation, the address and data buses are separate. In multiplexed
operation, the lower byte of the address, ADDR[7:0], also appears on the data bus,
DATA[7:0], during State T1 of the Intel bus mode cycle.

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Bus Mode
Controller
eZ80 Bus Mode Intel Bus
Signals (Pins) Signal Equvalents

INSTRD ALE

RD RD

WR WR

WAIT READY

MREQ MREQ

IORQ IORQ

ADDR[23:0] ADDR[23:0]
ADDR[7:0]

Multiplexed
DATA[7:0] Bus DATA[7:0]
Controller

Figure 12. Intel Bus Mode Signal and Pin Mapping

Intel™ Bus Mode—Separate Address and Data Buses

During Read operations with separate address and data buses, the Intel bus mode employs
four states—T1, T2, T3, and T4 as listed in Table 21.

Table 21. Intel Bus Mode Read States—Separate Address and Data Buses

STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the address bus and
the associated chip select signal is asserted. The CPU drives the ALE signal High at the
beginning of T1. In the middle of T1, the CPU drives ALE Low to facilitate the latching of the
address.
STATE T2 During State T2, the CPU asserts the RD signal. Depending on the instruction, either the
MREQ or IORQ signal is asserted.

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Table 21. Intel Bus Mode Read States—Separate Address and Data Buses (Continued)

STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(TWAIT) are asserted until the READY pin is driven High.
STATE T4 The CPU latches the Read data at the beginning of State T4. The CPU deasserts the RD
signal and completes the Intel bus mode cycle.

During Write operations with separate address and data buses, the Intel bus mode employs
four states—T1, T2, T3, and T4 as listed in Table 22.

Table 22. Intel Bus Mode Write States—Separate Address and Data Buses

STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the address bus, the
associated chip select signal is asserted, and the data is driven onto the data bus. The CPU
drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives
ALE Low to facilitate the latching of the address.
STATE T2 During State T2, the CPU asserts the WR signal. Depending on the instruction, either the
MREQ or IORQ signal is asserted.
STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(TWAIT) are asserted until the READY pin is driven High.
STATE T4 The CPU deasserts the WR signal at the beginning of State T4. The CPU holds the data
and address buses till the end of T4. The bus cycle is completed at the end of T4.

Intel bus mode timing is displayed for a Read operation in Figure 13 on page 76 and for a
Write operation in Figure 14 on page 77. If the READY signal (external WAIT pin) is
driven Low prior to the beginning of State T3, additional wait states (TWAIT) are asserted
until the READY signal is driven High. The Intel bus mode states are configured for 2 to
15 CPU system clock cycles. In the Figure 13 on page 76 and Figure 14 on page 77, each
Intel bus mode state is 2 CPU system clock cycles in duration. Figure 13 on page 76 and
Figure 14 on page 77 also display the assertion of one Wait state (TWAIT) by the selected
peripheral.

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T1 T2 T3 TWAIT T4

System Clock

ADDR[23:0]

DATA[7:0]

CSx

ALE

RD

READY

WR

MREQ
or IORQ

Figure 13. Example: Intel Bus Mode Read Timing—Separate Address and Data Buses

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T1 T2 T3 TWAIT T4

System Clock

ADDR[23:0]

DATA[7:0]

CSx

ALE

WR

READY

RD

MREQ
or IORQ

Figure 14. Example: Intel Bus Mode Write Timing—Separate Address and Data Buses

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Intel™ Bus Mode—Multiplexed Address and Data Bus

During Read operations with multiplexed address and data, the Intel™ bus mode employs
four states—T1, T2, T3, and T4 as listed in Table 23.

Table 23. Intel Bus Mode Read States—Multiplexed Address and Data Bus

STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the DATA bus and the
associated chip select signal is asserted. The CPU drives the ALE signal High at the
beginning of T1. In the middle of T1, the CPU drives ALE Low to facilitate the latching of the
address.
STATE T2 During State T2, the CPU removes the address from the DATA bus and asserts the RD
signal. Depending upon the instruction, either the MREQ or IORQ signal is asserted.
STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(TWAIT) are asserted until the READY pin is driven High.
STATE T4 The CPU latches the Read data at the beginning of State T4. The CPU deasserts the RD
signal and completes the Intel™ bus mode cycle.

During Write operations with multiplexed address and data, the Intel™ bus mode employs
four states—T1, T2, T3, and T4 as listed in Table 24.

Table 24. Intel Bus Mode Write States—Multiplexed Address and Data Bus

STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the DATA bus and
drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives
ALE Low to facilitate the latching of the address.
STATE T2 During State T2, the CPU removes the address from the DATA bus and drives the Write
data onto the DATA bus. The WR signal is asserted to indicate a Write operation.
STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(TWAIT) are asserted until the READY pin is driven High.
STATE T4 The CPU deasserts the Write signal at the beginning of T4 identifying the end of the Write
operation. The CPU holds the data and address buses through the end of T4. The bus cycle
is completed at the end of T4.

Signal timing for Intel bus mode with multiplexed address and data is displayed for a Read
operation in Figure 15 on page 79 and for a Write operation in Figure 16 on page 80. In
Figure 15 on page 79 and Figure 16 on page 80, each Intel bus mode state is 2 CPU system
clock cycles in duration. Figure 15 on page 79 and Figure 16 on page 80 also display the
assertion of one wait state (TWAIT) by the selected peripheral.

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T1 T2 T3 TWAIT T4

System Clock

ADDR[23:0]

DATA[7:0]

CSx

ALE

RD

READY

WR

MREQ
or IORQ

Figure 15. Example: Intel Bus Mode Read Timing—Multiplexed Address and Data Bus

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T1 T2 T3 TWAIT T4

System Clock

ADDR[23:0]

DATA[7:0]

CSx

ALE

WR

READY

RD

MREQ
or IORQ

Figure 16. Example: Intel Bus Mode Write Timing—Multiplexed Address and Data Bus

Motorola Bus Mode

Chip selects configured for Motorola bus mode modify the CPU bus signals to duplicate
an eight-state memory transfer similar to that on the Motorola-style microcontrollers. The
bus signals (and eZ80F91 I/O pins) are mapped as displayed in Figure 17 on page 81.

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Bus Mode
Controller
eZ80 Bus Mode Motorola Bus
Signals (Pins) Signal Equvalents

INSTRD AS

RD DS

WR R/W

WAIT DTACK

MREQ MREQ

IORQ IORQ

ADDR[23:0] ADDR[23:0]

DATA[7:0] DATA[7:0]

Figure 17. Motorola Bus Mode Signal and Pin Mapping

During Write operations, the Motorola bus mode employs eight states—S0, S1, S2, S3,
S4, S5, S6, and S7 as listed in Table 25.

Table 25. Motorola Bus Mode Read States

STATE S0 The Read cycle starts in state S0. The CPU drives R/W High to identify a Read cycle.
STATE S1 Entering state S1, the CPU drives a valid address on the address bus, ADDR[23:0].
STATE S2 On the rising edge of state S2, the CPU asserts AS and DS.
STATE S3 During state S3, no bus signals are altered.
STATE S4 During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral
signal. If the termination signal is not asserted at least one full CPU clock period prior to the
rising clock edge at the end of S4, the CPU inserts WAIT (TWAIT) states until DTACK is
asserted. Each wait state is a full bus mode cycle.
STATE S5 During state S5, no bus signals are altered.

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Table 25. Motorola Bus Mode Read States (Continued)

STATE S6 During state S6, data from the external peripheral device is driven onto the data bus.
STATE S7 On the rising edge of the clock entering state S7, the CPU latches data from the addressed
peripheral device and deasserts AS and DS. The peripheral device deasserts DTACK at
this time.

The eight states for a Write operation in Motorola bus mode are listed in Table 26.

Table 26. Motorola Bus Mode Write States

STATE S0 The Write cycle starts in S0. The CPU drives R/W High (if a preceding Write cycle leaves R/
W Low).
STATE S1 Entering S1, the CPU drives a valid address on the address bus.
STATE S2 On the rising edge of S2, the CPU asserts AS and drives R/W Low.
STATE S3 During S3, the data bus is driven out of the high-impedance state as the data to be written is
placed on the bus.
STATE S4 At the rising edge of S4, the CPU asserts DS. The CPU waits for a cycle termination signal
DTACK (WAIT). If the termination signal is not asserted at least one full CPU clock period
prior to the rising clock edge at the end of S4, the CPU inserts WAIT (TWAIT) states until
DTACK is asserted. Each wait state is a full bus mode cycle.
STATE S5 During S5, no bus signals are altered.
STATE S6 During S6, no bus signals are altered.
STATE S7 On entering S7, the CPU deasserts AS and DS. As the clock rises at the end of S7, the CPU
drives R/W High. The peripheral device deasserts DTACK at this time.

Signal timing for Motorola bus mode is displayed for a Read operation in Figure 18 on
page 83 and for a Write operation in Figure 19 on page 84. In these two figures, each
Motorola bus mode state is 2 CPU system clock cycles in duration.

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S0 S1 S2 S3 S4 S5 S6 S7

System Clock

ADDR[23:0]

DATA[7:0]

CSx

AS

DS

R/W

DTACK

MREQ
or IORQ

Figure 18. Example: Motorola Bus Mode Read Timing

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S0 S1 S2 S3 S4 S5 S6 S7

System Clock

ADDR[23:0]

DATA[7:0]

CSx

AS

DS

R/W

DTACK

MREQ
or IORQ

Figure 19. Example: Motorola Bus Mode Write Timing

Switching Between Bus Modes

When switching bus modes between Intel™ to Motorola, Motorola to Intel™, eZ80® to
Motorola, or eZ80 to Intel™, there is one extra SCLK cycle added to the bus access. An
extra clock cycle is not required for repeated access in any of the bus modes (for example,
Intel™ to Intel™). An extra clock cycle is not required for Intel™ (or Motorola) to eZ80
bus mode (under normal operation). The extra clock cycle is not shown in the timing
examples. Due to the asynchronous nature of these bus protocols, the extra delay does not
impact peripheral communication.

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Chip Select Registers

Chip Select x Lower Bound Register
For Memory chip selects, the chip select x Lower Bound register (see Table 27) defines
the lower bound of the address range for which the corresponding Memory chip select (if
enabled) is active. For I/O chip selects, the chip select x Lower Bound register defines the
address to which ADDR[15:8] is compared to generate an I/O chip select. All chip select
lower bound registers reset to 00h.

Table 27. Chip Select x Lower Bound Register (CS0_LBR = 00A8h, CS1_LBR = 00ABh,
CS2_LBR = 00AEh, CS3_LBR = 00B1h)

Bit 7 6 5 4 3 2 1 0
CS0_LBR Reset 0 0 0 0 0 0 0 0
CS1_LBR Reset 0 0 0 0 0 0 0 0
CS2_LBR Reset 0 0 0 0 0 0 0 0
CS3_LBR Reset 0 0 0 0 0 0 0 0
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–F For Memory Chip Selects (CSx_IO = 0)
CSX_LBR Fh This byte specifies the lower bound of the chip select address
range. The upper byte of the address bus, ADDR[23:16], is
compared to the values contained in these registers for
determining whether a Memory chip select signal must be
generated.
For I/O Chip Selects (CSx_IO = 1)
This byte specifies the chip select address value. ADDR[15:8] is
compared to the values contained in these registers for
determining whether an I/O chip select signal must be generated.

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Chip Select x Upper Bound Register

For Memory chip selects, the Chip Select x Upper Bound registers, listed in Table 28,
defines the upper bound of the address range for which the corresponding Chip Select (if
enabled) are active. For I/O chip selects, this register produces no effect. The reset state for
the Chip Select 0 Upper Bound register is FFh when the reset state for the other Chip
Select Upper Bound registers is 00h.

Table 28. Chip Select x Upper Bound Register (CS0_UBR = 00A9h, CS1_UBR = 00ACh,
CS2_UBR = 00AFh, CS3_UBR = 00B2h)

Bit 7 6 5 4 3 2 1 0
CS0_UBR Reset 1 1 1 1 1 1 1 1
CS1_UBR Reset 0 0 0 0 0 0 0 0
CS2_UBR Reset 0 0 0 0 0 0 0 0
CS3_UBR Reset 0 0 0 0 0 0 0 0
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–F For Memory Chip Selects (CSx_IO = 0)
CSX_UBR Fh This byte specifies the upper bound of the chip select address
range. The upper byte of the address bus, ADDR[23:16], is
compared to the values contained in these registers for
determining whether a chip select signal must be generated.
For I/O Chip Selects (CSx_IO = 1)
No effect.

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Chip Select x Control Register

The Chip Select x Control register (see Table 29) enables the chip selects, specifies the
type of chip select, and sets the number of wait states. The reset state for the Chip Select 0
Control register is E8h when the reset state for three other Chip Select Control registers is
00h.

Table 29. Chip Select x Control Register (CS0_CTL = 00AAh, CS1_CTL = 00ADh,
CS2_CTL = 00B0h, CS3_CTL = 00B3h)

Bit 7 6 5 4 3 2 1 0
CS0_CTL Reset 1 1 1 0 1 0 0 0
CS1_CTL Reset 0 0 0 0 0 0 0 0
CS2_CTL Reset 0 0 0 0 0 0 0 0
CS3_CTL Reset 0 0 0 0 0 0 0 0
CPU Access R/W R/W R/W R/W R/W R R R
Note: R/W = Read/Write; R = Read Only.

Bit
Position Value Description
[7:5] 000 0 wait states are asserted when this chip select is active.
CSX_WAIT
001 1 wait state is asserted when this chip select is active.
010 2 wait states are asserted when this chip select is active.
011 3 wait states are asserted when this chip select is active.
100 4 wait states are asserted when this chip select is active.
101 5 wait states are asserted when this chip select is active.
110 6 wait states are asserted when this chip select is active.
111 7 wait states are asserted when this chip select is active.
4 0 Chip select is configured as a memory chip select.
CSX_IO
1 Chip select is configured as an I/O chip select.
3 0 Chip select is disabled.
CSX_EN
1 Chip select is enabled.
[2:0] 000 Reserved.

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Chip Select x Bus Mode Control Register

The Chip Select Bus Mode register (see Table 30) configures the chip select for eZ80®,
Z80®, Intel™, or Motorola bus modes. Changing the bus mode allows the eZ80F91 device
to interface to peripherals based on the Z80, Intel™, or Motorola style asynchronous bus
interfaces. When a bus mode other than eZ80 is programmed for a particular chip select,
the CSx_WAIT setting in that Chip Select Control Register is ignored.

Table 30. Chip Select x Bus Mode Control Register (CS0_BMC = 00F0h, CS1_BMC =
00F1h, CS2_BMC = 00F2h, CS3_BMC = 00F3h)

Bit 7 6 5 4 3 2 1 0
CS0_BMC Reset 0 0 0 0 0 0 1 0
CS1_BMC Reset 0 0 0 0 0 0 1 0
CS2_BMC Reset 0 0 0 0 0 0 1 0
CS3_BMC Reset 0 0 0 0 0 0 1 0
CPU Access R/W R/W R/W R R/W R/W R/W R/W
Note: R/W = Read/Write; R = Read Only.

Bit
Position Value Description
[7:6] 00 eZ80 bus mode
BUS_MODE
01 Z80 bus mode
10 Intel™ bus mode
11 Motorola bus mode
5 0 Separate address and data
AD_MUX
1 Multiplexed address and data—appears on data bus
DATA[7:0]
4 0 Reserved

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Bit
Position Value Description
[3:0] 0000 Not valid.
BUS_CYCLE
0001 Each bus mode state is 1 eZ80® clock cycle in duration.1, 2, 3
0010 Each bus mode state is 2 eZ80 clock cycles in duration.
0011 Each bus mode state is 3 eZ80 clock cycles in duration.
0100 Each bus mode state is 4 eZ80 clock cycles in duration.
0101 Each bus mode state is 5 eZ80 clock cycles in duration.
0110 Each bus mode state is 6 eZ80 clock cycles in duration.
0111 Each bus mode state is 7 eZ80 clock cycles in duration.
1000 Each bus mode state is 8 eZ80 clock cycles in duration.
1001 Each bus mode state is 9 eZ80 clock cycles in duration.
1010 Each bus mode state is 10 eZ80 clock cycles in duration.
1011 Each bus mode state is 11 eZ80 clock cycles in duration.
1100 Each bus mode state is 12 eZ80 clock cycles in duration.
1101 Each bus mode state is 13 eZ80 clock cycles in duration.
1110 Each bus mode state is 14 eZ80 clock cycles in duration.
1111 Each bus mode state is 15 eZ80 clock cycles in duration.
Notes
1. Setting the BUS_CYCLE to 1 in Intel bus mode causes the ALE pin to not function properly.
2. Use of the external WAIT input pin in Z80 mode requires that BUS_CYCLE is set to a value
greater than 1.
3. BUS_CYCLE produces no effect in eZ80 mode.

Bus Arbiter
The Bus Arbiter within the eZ80F91 allows external bus masters to gain control of the
CPU memory interface bus. During normal operation, the eZ80F91 device is the bus mas-
ter. External devices request master use of the bus by asserting the BUSREQ pin. The Bus
Arbiter forces the CPU to release the bus after completing the current instruction. When
the CPU releases the bus, the Bus Arbiter asserts the BUSACK pin to notify the external
device that it can master the bus. When an external device assumes control of the memory
interface bus, the bus acknowledge cycle is complete. Table 31 on page 90 lists the status
of the pins on the eZ80F91 device during bus acknowledge cycles.
During a bus acknowledge cycle, the bus interface pins of the eZ80F91 device are used by
an external bus master to control the memory and I/O chip selects.

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Table 31. eZ80F91 Pin Status During Bus Acknowledge Cycles

Pin Symbol Signal Direction Description

ADDR23..ADDR0 Input Allows external bus master to utilize the chip
select logic of the eZ80F91.
CS0 Output Normal operation.
CS1 Output Normal operation.
CS2 Output Normal operation.
CS3 Output Normal operation.
DATA7..0 Tristate Allows external bus master to communicate
with external peripherals.
IORQ Input Allows external bus master to utilize the chip
select logic of the eZ80F91.
MREQ Input Allows external bus master to utilize the chip
select logic of the eZ80F91.
RD Tristate Allows external bus master to communicate
with external peripherals.
WR Tristate Allows external bus master to communicate
with external peripherals.
INSTRD Tristate Allows external bus master to communicate
with external peripherals.

Normal bus operation of the eZ80F91 device using CS0 to communicate to an external
peripheral is displayed in Figure 20 on page 91. Figure 21 on page 91 displays an external
bus master communicating with an external peripheral during bus acknowledge cycles.

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WAIT

RD

External WR External
Master DATA
Peripheral

ADDRESS

IORQ
eZ80F91
MREQ Chip Select
Wait State
CS0
Generator
CS1
CS2
CS3

Figure 20. Memory Interface Bus Operation During CPU Bus Cycles, Normal Operation

WAIT

RD

External WR External
Master DATA
Peripheral

ADDRESS

IORQ
eZ80F91
MREQ Chip Select
Wait State
CS0
Generator
CS1
CS2
CS3

Figure 21. Memory Interface Bus Operation During Bus Acknowledge Cycles

During bus acknowledge cycles, the Memory and I/O chip select logic is controlled by the
external address bus and external IORQ and MREQ signals.

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The following chip select features are not available during bus acknowledge cycles:
• The chip select logic does not insert wait states during bus acknowledge cycles regard-
less of the WAIT configuration for the decoded chip select.
• The bus mode controller does not function during bus acknowledge cycles.
• Internal registers and memory addresses in the eZ80F91 device are not accessible dur-
ing bus acknowledge cycles.

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Random Access Memory

The eZ80F91 device features 8 KB (8192 bytes) of single-port data Random Access
Memory (RAM) for general-purpose use and 8 KB of RAM for the EMAC. RAM is
enabled or disabled, and it is relocated to the top of any 64 KB page in memory. Data is
passed to and from RAM via the 8-bit data bus. On-chip RAM operates with zero wait
states. EMAC RAM is accessed via the bus arbiter and executes with zero or one Wait
states.
General-purpose RAM occupies memory addresses in the RAM Address Upper Byte reg-
ister in the range {RAM_ADDR_U[7:0], E000h} to {RAM_ADDR_U[7:0], FFFFh}.
EMAC RAM occupies memory addresses in the range {RAM_ADDR_U[7:0], C000h}
to {RAM_ADDR_U[7:0], DFFFh}. Following a RESET, RAM is enabled when
RAM_ADDR_U is set to FFh. Figure 22 displays a memory map for on-chip RAM. In
this example, RAM_ADDR_U is set to 7Ah. Figure 22 is not drawn to scale, as RAM
occupies only a very small fraction of the available 16 MB address space.

Memory
Location
FFFFFFh

7AFFFFh
8 KB
General-Purpose
RAM RAM_ADDR_U
7AE000h
7ADFFFh 7Ah
8 KB
EMAC SRAM
7AC000h

000000h

Figure 22. Example: eZ80F91 On-Chip RAM Memory Addressing

When enabled, on-chip RAM assumes priority over on-chip Flash memory and any mem-
ory chip selects that is also enabled in the same address space. If an address is generated in
a range that is covered by both the RAM address space and a particular memory chip

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select address space, the memory chip select is not activated. On-chip RAM is not accessi-
ble to external devices during bus acknowledge cycles.

RAM Control Registers

RAM Control Register
Internal general-purpose RAM is disabled by clearing the GPRAM_EN bit. The default on
RESET is for general-purpose RAM to be enabled. See Table 32.

Table 32. RAM Control Register (RAM_CTL = 00B4h)

Bit 7 6 5 4 3 2 1 0
Reset 1 1 0 0 0 0 0 0

CPU Access R/W R/W R R R R R R

Note: R/W = Read/Write; R = Read Only.

Bit
Position Value Description
7 0 On-chip general-purpose RAM is disabled.
GPRAM_EN
1 On-chip general-purpose RAM is enabled.
6 0 On-chip EMAC RAM is disabled.
ERAM_EN
1 On-chip EMAC RAM is enabled.
[5:0] 000000 Reserved.

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RAM Address Upper Byte Register

The RAM_ADDR_U register defines the upper byte of the address for on-chip RAM.
If enabled, RAM addresses assume priority over all Chip Selects. The external Chip Select
signals are not asserted if the corresponding RAM address is enabled. See Table 33.

Table 33. RAM Address Upper Byte Register (RAM_ADDR_U = 00B5h)

Bit 7 6 5 4 3 2 1 0
Reset 1 1 1 1 1 1 1 1

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–F This byte defines the upper byte of the RAM address. When
RAM_ADDR_U Fh enabled, the general-purpose RAM address space ranges from
{RAM_ADDR_U, E000h} to {RAM_ADDR_U, FFFFh}. When
enabled, the EMAC RAM address space ranges from
{RAM_ADDR_U, C000h} to {RAM_ADDR_U, DFFFh}.

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MBIST Control
There are two Memory Built-In Self-Test (MBIST) controllers for the RAM blocks on the
eZ80F91. MBIST_GPR is for General-Purpose RAM and MBIST_EMR is for EMAC
RAM. Writing a 1 to MBIST_ON starts the MBIST testing. Writing a 0 to MBIST_ON
stops the MBIST testing. On completion of the MBIST testing, MBIST_ON is
automatically reset to 0. If RAM passes MBIST testing, MBIST_PASS is 1. The value in
MBIST_PASS is only valid when MBIST_DONE is High. See Table 34.

Table 34. MBIST Control Register (MBIST_GPR = 00B6h, MBIST_EMR = 00B7h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R R R R R R R

Note: R/W = Read/Write; R = Read Only.

Bit Position Value Description

7 0 MBIST Testing of the RAM is disabled.
MBIST_ON
1 MBIST Testing of the RAM is enabled.
6 0 MBIST Testing has not completed.
MBIST_DONE
1 MBIST Testing has completed.
5 0 MBIST Testing has failed.
MBIST_PASS
1 MBIST Testing has passed.
[4:0] 00000 Reserved.

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Flash Memory
The eZ80F91 device features 256 KB (262,144 bytes) of non-volatile Flash memory with
Read/Write/Erase capability. The main Flash memory array is arranged in 128 pages with
8 rows per page and 256 bytes per row. In addition to main Flash memory, there are two
separately addressable rows which comprise a 512-byte information page.
In eight 32 KB blocks, 256 KB of main storage is protected. Protecting a 32 KB block
prevents Write or Erase operations. The lower 32 KB block (00000h–07FFFh) is pro-
tected using the external WP pin. This portion of memory is called the Boot block because
the CPU always starts executing code from this location at startup. If the application
requires external program memory, then the Boot block must at least contain a jump
instruction to move the Program Counter outside of the Flash memory space.
The Flash memory arrangement is displayed in Figure 23.

16 8
8 2 KB pages 256-byte rows
32 KB blocks per block per page

F
7 7
E
D
6 6
C
B
5 5
A
9
4 4
8
7
3 3
6
5
2 2
4
256
3 single-byte columns
1 1 per row
2
1
0 0 255 254 1 0
0

Figure 23. eZ80F91 Flash Memory Arrangement

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Flash Memory Overview

The eZ80F91 device includes a Flash memory controller that automatically converts
standard CPU Read and Write cycles to the specific protocol required for the Flash
memory array. As such, standard memory Read and Write instructions access the Flash
memory array as if it is internal RAM. The controller also supports I/O access to the Flash
memory array, in effect presenting it as an indirectly addressable bank of I/O registers.
These access methods are also supported via the ZDI and OCI™ interfaces.
In addition, eZ80Acclaim!® Flash Microcontrollers support a Flash Read–While–Write
methodology. In other words, the eZ80® CPU continues to read and execute code from an
area of Flash memory when a nonconflicting area of Flash memory is being programmed.
The Flash memory controller contains a frequency divider, a Flash register interface, and a
Flash control state machine. A simplified block diagram of the Flash controller is
displayed in Figure 24.

System Clock Clock Divider

8-bit downcounter

ADDR 17
eZ80 Core FADDR 17 FDOUT 8
Interface DOUT 8
FDIN 8 Flash
256 KB
FCNTL 9 +
Flash 512 bytes
State MAIN_INFO
Machine
Flash
Control
Registers
CPUD OUT 8

FLASH_IRQ

Figure 24. Flash Memory Block Diagram

Reading Flash Memory

The main Flash memory array is read using both memory and I/O operations. As an auxil-
iary storage area, the information page is only accessible via I/O operations. In all cases,
Wait states are automatically inserted to allow for read access time.

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Memory Read
A memory Read operation uses the address bus and data bus of the eZ80F91 device to
read a single data byte from Flash memory. This Read operation is similar to reads from
RAM. To perform Flash memory reads, the FLASH_CTRL register must be configured to
enable memory access to Flash with the appropriate number of wait states. See Table 38
on page 105.
Only the main area of Flash memory is accessible via memory reads. The information
page must be read using I/O access.

I/O Read
A single-byte I/O Read operation uses I/O registers for setting the column, page, and row
address to be read. A Read of the FLASH_DATA register returns the contents of Flash
memory at the designated address. Each access to the FLASH_DATA register causes an
autoincrement of the Flash address stored in the Flash address registers (FLASH_PAGE,
FLASH_ROW, FLASH_COL). To allow for Flash memory access time, the
FLASH_CTRL register must be configured with the appropriate number of wait states.
See Table 38 on page 105.

Programming Flash Memory

Flash memory is programmed using standard I/O or memory Write operations that the
Flash memory controller automatically translates to the detailed timing and protocol
required for Flash memory. The more efficient multibyte (row) programming mode is only
available via I/O Writes.
Note: To ensure data integrity and device reliability, two main restrictions exist on programming
of Flash memory:

1. The cumulative programming time since the last erase cannot exceed 31 ms for any
given row.
2. The same byte cannot be programmed more than once since the last erase.

Single-Byte I/O Write

A single-byte I/O Write operation uses I/O registers for setting the column, page, and row
address to be written. The FLASH_DATA register stores the data to be written. While the
CPU executes an I/O instruction to load the data into the FLASH_DATA register, the
Flash controller asserts the internal WAIT signal to stall the CPU until the Flash Write
operation is complete. A single-byte Write takes between 66 µs and 85 µs to complete.
Programming an entire row (256 bytes) using single-byte Writes therefore takes no more
than 21.8 ms. This duration of time does not include the time required by the CPU to
transfer data to the registers which is a function of the instructions employed and the
system clock frequency. Each access to the FLASH_DATA register causes an

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autoincrement of the Flash address stored in the Flash Address registers (FLASH_PAGE,
FLASH_ROW, FLASH_COL).
A typical sequence that performs a single-byte I/O Write is shown below. Because the
Write is self-timed, step 2 of the sequence is repeated back-to-back without requiring poll-
ing or interrupts.
1. Write the FLASH_PAGE, FLASH_ROW, and FLASH_COL registers with the
address of the byte to be written.
2. Write the data value to the FLASH_DATA register.

Multibyte I/O Write (Row Programming)

Multibyte I/O Write operations use the same I/O registers as single-byte Writes.
Multibyte I/O Writes allow the programming of full row and are enabled by setting the
ROW_PGM bit of the Flash Program Control Register. For multibyte I/O Writes, the CPU
sets the address registers, enables row programming, and then executes an I/O instruction
(with repeat) to load the block of data into the FLASH_DATA register. For each individual
byte written to the FLASH_DATA register during the block move, the Flash controller
asserts the internal WAIT signal to stall the CPU until the current byte is programmed.
Each access to the FLASH_DATA register causes an autoincrement of the Flash address
stored in the Flash Address registers (FLASH_PAGE, FLASH_ROW, FLASH_COL).
During row programming, the Flash controller continuously asserts the Flash memory’s
high voltage signal until all bytes are programmed (column address < 255). As a result, the
row programs more quickly than if the high-voltage signal is toggled for each byte. The
per-byte programming time during row programming is between 41 µs and 52 µs. As such,
programming 256 bytes of a row in this mode takes not more than 13.4 ms, leaving 17.6
ms for CPU instruction overhead to fetch the 256 bytes.
A typical sequence that performs a multibyte I/O Write is shown below:
1. Check the FLASH_IRQ register to ensure that any previous row program is
completed.
2. Write the FLASH_PAGE, FLASH_ROW, and FLASH_COL registers with the
address of the first byte to be written.
3. Set the ROW_PGM bit in the FLASH_PGCTL register to enable row programming
mode.
4. Write the next data value to the FLASH_DATA register.
5. If the end of the row has not been reached, return to step 4.
During row programming, software must monitor the row time-out error bit either by
enabling this interrupt or via polling. If a row time-out occurs, the Flash controller aborts
the row programming operation, and software must assure that no further Writes are
performed to the row without it first being erased. It is suggested that row programming is
be used one time per row and not in combination with single-byte Writes to the same row

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without first erasing it. Otherwise, the burden is on software to ensure that the 31 ms
maximum cumulative programming time between erases is not exceeded for a row.

Memory Write
A single-byte memory Write operation uses the address bus and data bus of the eZ80F91
device for programming a single data byte to Flash memory. While the CPU executes a
Load instruction, the Flash controller asserts the internal WAIT signal to stall the CPU
until the Write is complete. A single-byte Write takes between 66 µs and 85 µs to
complete. Programming an entire row using memory Writes therefore takes no more than
21.8 ms. This duration of time does not include time required by the CPU to transfer data
to the registers, which is a function of the instructions employed and the system clock
frequency.
The memory Write function does not support multibyte row programming. Because mem-
ory Writes are self-timed, they are performed back-to-back without requiring polling or
interrupts.

Erasing Flash Memory

Erasing bytes in Flash memory returns them to a value of FFh. Both the MASS and PAGE
ERASE operations are self-timed by the Flash controller, leaving the CPU free to execute
other operations in parallel. The DONE status bit in the Flash Interrupt Control Register
are polled by software or used as an interrupt source to signal completion of an Erase oper-
ation. If the CPU attempts to access Flash memory while an erase is in progress, the Flash
controller forces a wait state until the Erase operation is completed.

Mass Erase
Performing a MASS ERASE operation on Flash memory erases all bits contained in the
main Flash memory array. The information page remains unaffected unless the
FLASH_PAGE register bit 7(INFO_EN) is set. This self-timed operation takes
approximately 200 ms to complete.

Page Erase
The smallest erasable unit in Flash memory is a page. The pages to be erased, whether they
are the 128 main Flash memory pages or the information page, are determined by the set-
ting of the FLASH_PAGE register. This self-timed operation takes approximately 10 ms to
complete.

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Information Page Characteristics

As noted earlier, the information page is not accessible using memory access instructions
and must be accessed via the FLASH_DATA I/O register. The Flash Page Select Register
contains a bit which selects the information page for I/O access.
There are two ways to erase the information page. You must set the FLASH_PAGE regis-
ter(0x00FC) bit7(INFO_EN) and then you execute either a MASS ERASE (which also
erases the entire main Flash memory array) operation or a PAGE ERASE operation.

Flash Control Registers

The Flash Control Register interface contains all the registers used in Flash memory. The
definitions in this section describe each register.

Flash Key Register

Writing the two-byte sequence B6h, 49h in immediate succession to this register unlocks
the Flash Divider and Flash Write/Erase Protection registers. If these values are not
written by consecutive CPU I/O Writes (I/O reads and memory Read/Writes have no
effect), the Flash Divider and Flash Write/Erase Protection registers remain locked. This
prevents accidental overwrites of these critical Flash control register settings. Writing a
value to either the Flash Frequency Divider Register or the Flash Write/Erase Protection
Register automatically relocks both of the registers. See Table 35.

Table 35. Flash Key Register (FLASH_KEY = 00F5h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access W W W W W W W W
Note: W = Write Only.

Bit
Position Value Description
[7:0] B6h, Sequential Write operations of the values B6h, 49h to this
FLASH_KEY 49h register will unlock the Flash Frequency Divider and Flash
Write/Erase Protection registers.

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Flash Data Register

The Flash Data register stores the data values to be programmed into Flash memory via
I/O Write operations. An I/O read of the Flash Data register returns data from Flash
memory. The Flash memory address used for I/O access is determined by the contents of
the page, row, and column registers. Each access to the FLASH_DATA register causes an
autoincrement of the Flash address stored in the Flash Address registers (FLASH_PAGE,
FLASH_ROW, FLASH_COL). See Table 36.

Table 36. Flash Data Register (FLASH_DATA = 00F6h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit Position Value Description

[7:0] 00h-FFh Data value to be written to Flash memory during an I/O Write
FLASH_DATA operation, or the data value that is read in Flash memory,
indicated by the Flash Address registers (FLASH_PAGE,
FLASH_ROW, FLASH_COL).

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Flash Address Upper Byte Register

The FLASH_ADDR_U register defines the upper 6 bits of the Flash memory address
space. Changing the value of FLASH_ADDR_U allows on-chip 256 KB Flash memory
to be mapped to any location within the 16 MB linear address space of the eZ80F91
device. If on-chip Flash memory is enabled, the Flash address assumes priority over any
external Chip Selects. The external Chip Select signals are not asserted if the corre-
sponding Flash address is enabled. Internal Flash memory does not hold priority over
internal SRAM. See Table 37.

Table 37. Flash Address Upper Byte Register (FLASH_ADDR_U = 00F7h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R R

Note: R/W = Read/Write; R = Read Only.

Bit Position Value Description

[7:2] 00h–FCh These bits define the upper byte of the Flash address.
FLASH_ADDR_U When on-chip Flash is enabled, the Flash address space
begins at address {FLASH_ADDR_U, 00b, 0000h}. On-chip
Flash has priority over all external Chip Selects.
[1:0] 00 Reserved (enforces alignment on a 256 KB boundary).

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Flash Control Register

The Flash Control register enables or disables memory access to Flash memory. I/O access
to the Flash control registers and to Flash memory is still possible while Flash memory
space access is disabled.
The minimum access time of internal Flash memory is 60 ns. The Flash Control Regis-
ter must be configured to provide the appropriate number of wait states based on the sys-
tem clock frequency of the eZ80F91 device. Because the maximum SCLK frequency is
50 MHz (20 ns), the default on RESET is for four Wait states to be inserted for Flash
memory access (Flash memory access + one eZ80® Bus Cycle = 60 ns + 20 ns = 80 ns;
80 ns ÷ 20 ns = 4 Wait states). See Table 38.

Table 38. Flash Control Register (FLASH_CTRL = 00F8h)

Bit 7 6 5 4 3 2 1 0
Reset 1 0 0 0 1 0 0 0

CPU Access R/W R/W R/W R R/W R R R

Note: R/W = Read/Write, R = Read Only.

Bit Position Value Description

[7:5] 000 0 wait states are inserted when the Flash is active.
FLASH_WAIT
001 1 wait state is inserted when the Flash is active.
010 2 wait states are inserted when the Flash is active.
011 3 wait states are inserted when the Flash is active.
100 4 wait states are inserted when the Flash is active.
101 5 wait states are inserted when the Flash is active.
110 6 wait states are inserted when the Flash is active.
111 7 wait states are inserted when the Flash is active.
[4] 0 Reserved.
[3] 0 Flash memory access is disabled.
FLASH_EN
1 Flash memory access is enabled.
[2:0] 000 Reserved.

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Flash Frequency Divider Register

The 8-bit frequency divider allows the programming of Flash memory over a range of
system clock frequencies. Flash is programmed with system clock frequencies ranging
from 154 kHz to 50 MHz. The Flash controller requires an input clock with a period that
falls within the range of 5.1−6.5 µs. The period of the Flash controller clock is set in the
Flash Frequency Divider Register. Writes to this register is allowed only after it is
unlocked via the FLASH_KEY register. The Flash Frequency Divider Register value
required versus the system clock frequency is listed in Table 39. System clock frequencies
outside of the ranges shown are not supported. Register values for the Flash Frequency
Divider are listed in Table 40.

Table 39. Flash Frequency Divider Values

System Clock Frequency Flash Frequency Divider Value

154–196 kHz 1
308–392 kHz 2
462–588 kHz 3
616 kHz–50 MHz CEILING [System Clock Frequency (MHz) x 5.1 (µs)]*
Note: *The CEILING function rounds fractional values up to the next whole number. For example,
CEILING(3.01) is 4.

Table 40. Flash Frequency Divider Register (FLASH_FDIV = 00F9h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 1

CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W
Note: R/W = Read/Write, R = Read Only. *Key sequence required to enable Writes

Bit Position Value Description

[7:0] 01h–FFh Divider value for generating the required 5.1-6.5 µs Flash
FLASH_FDIV controller clock period.

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Flash Write/Erase Protection Register

The Flash Write/Erase Protection register prevents accidental Write or Erase operations.
The protection is limited to a resolution of eight 32 KB blocks. Setting a bit to 1 protects
that 32 KB block of Flash memory from accidental Writes or Erases. The default upon
RESET is for all Flash memory blocks to be protected.
The WP pin works in conjunction with FLASH_PROT[0] to protect the lowest block (also
called the Boot block) of Flash memory. If either the WP is held asserted or
FLASH_PROT[0] is set, the Boot block is protected from Write and Erase operations.
Note: A protect bit is not available for the information page. The information page is, however,
protected excluded from a MASS ERASE by clearing the FLASH_PAGE register
(0x00FC) bit7(INFO_EN).

Writes to this register is allowed only after it is unlocked via the FLASH_KEY register.
Any attempted Writes to this register while locked will set it to FFh, thereby protecting all
blocks. See Table 41.

Table 41. Flash Write/Erase Protection Register (FLASH_PROT = 00FAh)

Bit 7 6 5 4 3 2 1 0
Reset 1 1 1 1 1 1 1 1

CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: R/W = Read/Write if unlocked, R = Read Only if locked. *Key sequence required to unlock.

Bit Position Value Description

[7] 0 Disable Write/Erase Protect on block 38000h to 3FFFFh.
BLK7_PROT
1 Enable Write/Erase Protect on block 38000h to 3FFFFh.
[6] 0 Disable Write/Erase Protect on block 30000h to 37FFFh.
BLK6_PROT
1 Enable Write/Erase Protect on block 30000h to 37FFFh.
[5] 0 Disable Write/Erase Protect on block 28000h to 2FFFFh.
BLK5_PROT
1 Enable Write/Erase Protect on block 28000h to 2FFFFh.
[4] 0 Disable Write/Erase Protect on block 20000h to 27FFFh.
BLK4_PROT
1 Enable Write/Erase Protect on block 20000h to 27FFFh.
[3] 0 Disable Write/Erase Protect on block 18000h to 1FFFFh.
BLK3_PROT
1 Enable Write/Erase Protect on block 18000h to 1FFFFh.
[2] 0 Disable Write/Erase Protect on block 10000h to 17FFFh.
BLK2_PROT
1 Enable Write/Erase Protect on block 10000h to 17FFFh.

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Bit Position Value Description

[1] 0 Disable Write/Erase Protect on block 08000h to 0FFFFh.
BLK1_PROT
1 Enable Write/Erase Protect on block 08000h to 0FFFFh.
[0] 0 Disable Write/Erase Protect on block 00000h to 07FFFh.
BLK0_PROT
1 Enable Write/Erase Protect on block 00000h to 07FFFh.
Note: The lower 32 KB block (00000h to 07FFFh—BLK0) is called the Boot block and is protected
using the external WP pin.

Flash Interrupt Control Register

There are two sources of interrupts from the Flash controller. These two sources are:
• Page Erase, Mass Erase, or Row Program completed successfully.
• An error condition occurred.
Either or both of these two interrupt sources are enabled by setting the appropriate bits in
the Flash Interrupt Control register.
The Flash Interrupt Control register contains four status bits to indicate the following error
conditions:

Row Program Time-Out—This bit signals a time-out during Row Programming. If the
current row program operation does not complete within 4864 Flash controller clocks,
the Flash controller terminates the row program operation by clearing bit 2 of the Flash
Program Control Register and sets the RP_TM0 error bit to 1.

Write Violation—This bit indicates an attempt to write to a protected block of Flash

memory (the Write was not performed).

Page Erase Violation—This bit indicates an attempt to erase a protected block of Flash
memory (the requested page was not erased).

Mass Erase Violation—This bit indicates an attempt to MASS ERASE when there are
one or more protected blocks in Flash memory (the MASS ERASE was not performed).
If the error condition interrupt is enabled, any of these four error conditions result in an
interrupt request being sent to the eZ80F91device’s interrupt controller. Reading the Flash
Interrupt Control register clears all error condition flags and the DONE flag. See Table 42
on page 109.

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Table 42. Flash Interrupt Control Register (FLASH_IRQ = 00FBh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R R R R R R

Note: R/W = Read/Write, R = Read Only. Read resets bits [5] and [3:0].

Bit Position Value Description

[7] 0 Flash Erase/Row Program Done Interrupt is disabled.
DONE_IEN
1 Flash Erase/Row Program Done Interrupt is enabled.
[6] 0 Error Condition Interrupt is disabled.
ERR_IEN
1 Error Condition Interrupt is enabled.
[5] 0 Erase/Row Program Done Flag is not set.
DONE
1 Erase/Row Program Done Flag is set.
[4] 0 Reserved.
[3] 0 The Write Violation Error Flag is not set.
WR_VIO
1 The Write Violation Error Flag is set.
[2] 0 The Row Program Time-Out Error Flag is not set.
RP_TMO
1 The Row Program Time-Out Error Flag is set.
[1] 0 The Page Erase Violation Error Flag is not set.
PG_VIO
1 The Page Erase Violation Error Flag is set.
[0] 0 The Mass Erase Violation Error Flag is not set.
MASS_VIO
1 The Mass Erase Violation Error Flag is set.
Note: The lower 32 KB block (00000h to 07FFFh) is called the Boot Block and is protected using
the external WP pin. Attempts to page erase BLK0 or mass erase Flash when WP is asserted
result in failure and signal an erase violation.

Flash Page Select Register

The msb of this register is used to select whether I/O Flash access and PAGE ERASE
operations are directed to the 512-byte information page or to the main Flash memory
array, and also whether the information page is included in MASS ERASE operations. The
lower 7 bits are used to select one of the main 128 pages for PAGE ERASE or I/O
operations.
To perform a PAGE ERASE, the software must set the proper page value prior to setting
the page erase bit in the Flash Control Register. In addition, each access to the

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FLASH_DATA register causes an autoincrement of the Flash address stored in the Flash
Address registers (FLASH_PAGE, FLASH_ROW, FLASH_COL). See Table 43.

Table 43. Flash Page Select Register (FLASH_PAGE = 00FCh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write, R = Read Only.

Bit
Position Value Description
[7] 0 Flash I/O access to PAGE ERASE operations are directed to
INFO_EN main Flash memory. Info page is NOT affected by a MASS
ERASE operation.
1 Flash I/O access to PAGE ERASE operations are directed to
the information page. PAGE ERASE operations only affect
the information page. Info page is included during a MASS
ERASE operation.
[6:0] 00h–7Fh Page address of Flash memory to be used during the PAGE
FLASH_PAGE ERASE or I/O access of main Flash memory. When
INFO_EN is set to 1, this field is ignored.

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Flash Row Select Register

The Flash Row Select Register is a 3-bit value used to define one of the 8 rows of Flash
on a single page. This register is used for all I/O access to Flash memory. In addition,
each access to the FLASH_DATA register causes an autoincrement of the Flash address
stored in the Flash Address registers (FLASH_PAGE, FLASH_ROW, FLASH_COL).
See Table 44.

Table 44. Flash Row Select Register (FLASH_ROW = 00FDh)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X 0 0 0

CPU Access R R R R R R/W R/W R/W

Note: R/W = Read/Write, R = Read Only.

Bit
Position Value Description
[7:3] 00h Reserved.
[2:0] 0h–7h Row address of Flash memory to be used during an I/O access
FLASH_ROW of Flash memory. When INFO_EN is 1 in the Flash Page Select
Register, values for this field are restricted to 0h–1h, which
selects between the two rows in the information page.

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Flash Column Select Register

The Flash Column Select Register is an 8-bit value used to define one of the 256 bytes of
Flash memory contained in a single row. This register is used for all I/O access to Flash
memory. In addition, each access to the FLASH_DATA register causes an autoincrement
of the Flash address stored in the Flash Address registers (FLASH_PAGE, FLASH_ROW,
FLASH_COL). See Table 45.

Table 45. Flash Column Select Register (FLASH_COL = 00FEh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write, R = Read Only.

Bit
Position Value Description
[7:0] 00h–FFh Column address of Flash memory to be used during an I/O
FLASH_COL access of Flash memory.

Flash Program Control Register

The Flash Program Control Register is used to perform the functions of MASS ERASE,
PAGE ERASE, and ROW PROGRAM. MASS ERASE and PAGE ERASE are
self-clearing functions.
MASS ERASE requires approximately 200 ms to completely erase the full 256 KB of
main Flash and the 512-byte information page if the FLASH_PAGE register(0x00FC)
bit7(INFO_EN) is set. The 200 ms time is not reduced by excluding the 512 byte
information page from erasing.
PAGE ERASE requires approximately 10 ms to erase a 2 KB page.
On completion of either a MASS ERASE or PAGE ERASE, the value of each
corresponding bit is reset to 0.
When Flash is being erased, any Read or Write access to Flash forces the CPU into a Wait
state until the Erase operation is complete and the Flash is accessed. Reads and Writes to
areas other than Flash memory proceeds as usual while an Erase operation is
underway.
During row programming, any reads of Flash memory force a WAIT condition until the
row programming operation completes or times out. See Table 46 on page 113.

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Table 46. Flash Program Control Register (FLASH_PGCTL = 00FFh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
CPU Access R R R R R R/W R/W R/W
Note: R/W = Read/Write, R = Read Only.

Bit
Position Value Description
[7:3] 00h Reserved.
[2] 0 Row Program Disable or Row Program completed.
ROW_PGM
1 Row Program Enable. This bit automatically resets to 0 when
the row address reaches 256 or when the Row Program
operation times out.
[1] 0 Page Erase Disable (Page Erase completed).
PG_ERASE
1 Page Erase Enable. This bit automatically resets to 0 when the
PAGE ERASE operation is complete.
[0] 0 Mass Erase Disable (Mass Erase completed).
MASS_ERASE
1 Mass Erase Enable. This bit automatically resets to 0 when the
MASS ERASE operation is complete.

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Watchdog Timer
The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power
faults, and other system-level problems which places the CPU into unsuitable operating
states. The eZ80F91 WDT features:
• Four programmable time-out ranges (depending on the WDT clock source). The four
ranges are:
– 03.2–5.20 ms
– 51.2–83.9 ms
– 0.50–0.82 sec
– 2.68–4.00 sec

• Three selectable WDT clock sources:

– Internal RC oscillator
– System clock
– Real-Time Clock source (on-chip 32 kHz crystal oscillator or 50/60 Hz signal)

• A selectable time-out response: a time-out is configured to generate either a RESET or

a nonmaskable interrupt (NMI)
• A WDT time-out RESET indicator flag
Figure 25 displays a block diagram of the Watchdog Timer.

Data[7:0]

Control Register/
Reset Register
WDT_CLK

RTC Clock
28-Bit
System Clock WDT Control Logic
Upcounter

WDT Time-out Compare Logic

Oscillator (WDT_PERIOD)

RESET

NMI to eZ80 CPU

¤

Figure 25. Watchdog Timer Block Diagram

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Watchdog Timer Operation

Enabling and Disabling the Watchdog Timer
The WDT is disabled on a RESET. To enable the WDT, the application program must set
WDT_EN, which is bit 7 of the WDT_CTL register. After WDT_EN is set, no Writes are
allowed to the WDT_CTL register. When enabled, the WDT cannot be disabled except by
a RESET.

Time-Out Period Selection

There are four choices of time-out periods for the WDT. The WDT time-out period is
defined by the WDT_PERIOD WDT_CTL[1:0] field and WDT_CLK WDT_CTL[3:2]
field of the Watchdog Timer control register (WDT_CTL = 0093h). The approximate
time-out period and corresponding clock cycles for three different WDT clock sources are
listed in Table 47.
The WDT time-out period divider is set to one of the four available settings for the
selected frequency of the WDT clock source. Basing the divider settings on the clock
source values provides a time-out range from few seconds to few msecs, regardless of the
frequency setting.

Table 47. WDT Approximate Time-Out Delays for Possible Clock Sources

WDT_CLK[ 00 01 10 11
3:2]
50 MHz system 32.768 kHz RTC Internal RC Reserved
clock clock oscillator (~10
kHz)

WDT_PERI Divider Timeout Divider Timeout Divider Timeout Divider Timeout

OD[1:0]
00 227 2.68 s 217 4.00 s 215 3.28 s - -
01 225 0.67 s 214 0.5 s 213 0.82 s - -
22 11 9
10 2 83.9 ms 2 62.5 ms 2 51.2 ms - -
11 218 5.2 ms 27 3.9 ms 25 3.2 ms - -

RESET or NMI Generation

A WDT time-out causes a RESET or sends a NMI signal to the CPU. The default opera-
tion is for the WDT to cause a RESET.
If the NMI_OUT bit in the WDT_CTL register is set to 0, then on a WDT time-out, the
RST_FLAG bit in the WDT_CTL register is set to 1. The RST_FLAG bit is polled by the
CPU to determine the source of the RESET event.

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If the NMI_OUT bit in the WDT_CTL register is set to 1, then on time-out, the WDT
asserts an NMI for CPU processing. The NMI_FLAG bit is polled by the CPU to deter-
mine the source of the NMI event.

Watchdog Timer Registers

Watchdog Timer Control Register
The Watchdog Timer Control register (see Table 48) is an 8-bit Read/Write register used to
enable the Watchdog Timer, set the time-out period, indicate the source of the most recent
RESET or NMI, and select the required operation on WDT time-out.
The default clock source for the WDT is the WDT oscillator (WDT_CLK = 10b).
To power-down the WDT oscillator, another clock source must be selected. The power-
up sequence of the WDT oscillator takes approximately 20 ms.

Table 48. Watchdog Timer Control Register (WDT_CTL = 0093h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0/1 0 1 0 0 0

CPU Access R/W R/W R R R/W R/W R/W R/W

Note: R = Read only; R/W = Read/Write.

Bit
Position Value Description
7 0 WDT is disabled.
WDT_EN
1 WDT is enabled. When enabled, the WDT cannot be disabled
without a RESET.
6 0 WDT time-out resets the CPU.
NMI_OUT
1 WDT time-out generates a NMI to the CPU.
5 0 RESET caused by external full-chip reset or ZDI reset.
RST_FLAG
1 RESET caused by WDT time-out. This flag is set by the WDT
time-out, only if the NMI_OUT flag is set to 0. The CPU polls
this bit to determine the source of the RESET. This flag is
cleared by a non-WDT generated reset.
4 0 NMI caused by external source.
NMI_FLAG
1 NMI caused by WDT time-out. This flag is set by the WDT time-
out, only if the NMI_OUT flag is set to 1. The CPU polls this bit
to determine the source of the NMI. This flag is cleared by a
non-WDT NMI.

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Bit
Position Value Description
[3:2] 00 WDT clock source is system clock.
WDT_CLK
01 WDT clock source is Real-Time Clock source (32 kHz on-chip
oscillator or 50/60 Hz input as set by RTC_CTRL[4]).
10 WDT clock source is internal RC oscillator (10 kHz typical).
11 Reserved.
[1:0] 00 WDT_CLK = 00 WDT time-out period is 227 clock cycles.
WDT_PERIOD
WDT_CLK = 01 WDT time-out period is 217 clock cycles.
WDT_CLK = 10 WDT time-out period is 215 clock cycles.
WDT_CLK = 11 Reserved.
01 WDT_CLK = 00 WDT time-out period is 225 clock cycles.
WDT_CLK = 01 WDT time-out period is 214 clock cycles.
WDT_CLK = 10 WDT time-out period is 213 clock cycles.
WDT_CLK = 11 Reserved.
10 WDT_CLK = 00 WDT time-out period is 222 clock cycles.
WDT_CLK = 01 WDT time-out period is 211 clock cycles.
WDT_CLK = 10 WDT time-out period is 29 clock cycles.
WDT_CLK = 11 Reserved.
11 WDT_CLK = 00 WDT time-out period is 218 clock cycles.
WDT_CLK = 01 WDT time-out period is 27 clock cycles.
WDT_CLK = 10 WDT time-out period is 25 clock cycles.
WDT_CLK = 11 Reserved.
Note: When the WDT is enabled, no Writes are allowed to the WDT_CTL register.

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Watchdog Timer Reset Register

The WDT Reset register (see Table 49) is an 8-bit Write only register. The WDT is reset
when an A5h value followed by a 5Ah value is written to this register. Any amount of time
occurs between the writing of A5h value and the 5Ah value, so long as the WDT time-out
does not occur prior to completion. Any value other than 5Ah written to the WDT Reset
register after the A5h value requires that the sequence of Writes (A5h,5Ah) be restarted for
the timer to be reset.

Table 49. Watchdog Timer Reset Register (WDT_RR = 0094h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access W W W W W W W W
Note: X = Undefined; W = Write Only.

Bit
Position Value Description
[7:0] A5h The first Write value required to reset the WDT prior to a time-
WDT_RR out.
5Ah The second Write value required to reset the WDT prior to a
time-out. If an A5h, 5Ah sequence is written to WDT_RR, the
WDT timer is reset to its initial count value and counting
resumes.

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Programmable Reload Timers

The eZ80F91 device features four programmable reload timers. The core of each timer is a
16-bit downcounter. In addition, each timer features a selectable clock source, adjustable
prescaling and operates in either SINGLE PASS or CONTINUOUS mode.
In addition to the basic timer functionality, some of the timers support specialty modes
that performs event counting, input capture, output compare, and Pulse-Width Modulation
(PWM) generation functions. PWM mode supports four individually-configurable outputs
and a power trip function.
Each of the four timers available on the eZ80F91 device are controlled individually. They
do not share the same counters, reload registers, control registers, or interrupt signals. A
simplified block diagram of a programmable reload timer is displayed in Figure 26.
Each timer features its own interrupt which is triggered either by the timer reaching zero
or after a successful comparison occurs. As with the other eZ80F91 interrupts, the priority
is fully programmable.

Input Capture
CONTROL ICx
Registers

R
E
L 16-Bit
Comparator OCx
O Down Counter
A 16
D

16

SCLK DIV Output Compare

M Registers
RTC CLK U
X
ECx

PWM PWM
EOC IC OC PWR Trip PWM
Control

IRQ Control

IRQ

Figure 26. Programmable Reload Timer Block Diagram

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Basic Timer Operation

Basic timer operation is controlled by a timer control register and a programmable reload
value. The CPU uses the control register to setup the prescaling, the input clock source,
the end-of-count behavior, and to start the timer. The 16-bit reload value is used to
determine the duration of the timer’s count before either halting or reloading.
After choosing a timer period and writing the appropriate values to the reload registers, the
CPU must set the timer enable bit (TMRx_CTL[TIM_EN]) by allowing the count to
begin. The reload bit (TMRx_CTL[RLD]) must also be asserted so that the timer counts
down from the reload value rather than from 0000h. On the system clock cycle, after the
assertion of the reload bit, the timer loads with the 16-bit reload value and begins counting
down. The reload bit is automatically cleared after the loading operation. The timer is
enabled and reloaded on the same cycle; however, the timer does not require disabling to
reload and reloading is performed at any time. It is also possible to halt the timer by deas-
serting the timer enable bit and resuming the count at a later time from the same point by
reasserting the bit.

Reading the Current Count Value

The CPU reads the current count value when the timer is running. Because the count is a
16-bit value, the hardware latches the value of the upper byte into temporary storage when
the lower byte is read. This value in temporary storage is the value returned when the
upper byte is read. Therefore, the software must read the lower byte first. If it attempts to
read the upper byte first, it does not obtain the current upper byte of the count. Instead, it
obtains the last latched value. This Read operation does not affect timer operation.

Setting Timer Duration

There are three factors to consider while determining Programmable Reload Timer
duration: clock frequency, clock divider ratio, and initial count value. Minimum duration
of the timer is achieved by loading 0001h. Maximum duration is achieved by loading
0000h, because the timer first rolls over to FFFFh and then continues counting down to
0000h before the end-of-count is signaled. Depending on the TMRx_CTL[CLK_SEL]
bits of the control register, the clock is either the system clock, or an on-chip RC oscillator
output or an input from a pin.
The time-out period of the timer is returned by the following equation:

Clock Divider Ratio x Reload Value

Time-Out Period =
System Clock Frequency

To calculate the time-out period with the above equation while using an initial value of
0000h, enter a reload value of 65536 (FFFFh + 1).

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Minimum time-out duration is four times longer than the input clock period and is gener-
ated by setting the clock divider ratio to 1:4 and the reload value to 0001h. Maximum
time-out duration is 224 (16,777,216) times longer than the input clock period and is gen-
erated by setting the clock divider ratio to 1:256 and the reload value to 0000h.

SINGLE PASS Mode

In SINGLE PASS mode when the end-of-count value (0000h) is reached; counting halts,
the timer is disabled, and TMRx_CTL[TIM_EN] bit resets to 0. To re-enable the timer, the
CPU must set the TIM_EN bit to 1. An example of a PRT operating in SINGLE PASS
mode is displayed in Figure 27. Timer register information is listed in Table 50.

System Clock

Clock Enable

TMR3_CTL Write
(Timer Enable)

T3 Count 0 4 3 2 1 0

Interrupt Request

Figure 27. Example: PRT SINGLE PASS Mode Operation

Table 50. Example: PRT SINGLE PASS Mode Parameters

Parameter Control Register(s) Value

Timer Enable TMRx_CTL[TIM_EN] 1
Reload TMRx_CTL[RLD] 1
Prescaler Divider = 4 TMRx_CTL[CLK_DIV] 00b
SINGLE PASS Mode TMRx_CTL[TIM_CONT] 0
End of Count Interrupt Enable TMRx_IER[IRQ_EOC_EN] 1
Timer Reload Value {TMRx_RR_H, TMRx_RR_L} 0004h

CONTINUOUS Mode
In CONTINUOUS mode, when the end-of-count value, 0000h, is reached, the timer
automatically reloads the 16-bit start value from the Timer Reload registers,

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TMRx_RR_H and TMRx_RR_L. Downcounting continues on the next clock edge and
the timer continues to count until disabled. An example of the timer operating in
CONTINUOUS mode is displayed in Figure 28. Timer register information is listed in
Table 51.

System Clock

Clock Enable

TMR3_CTL Write
(Timer Enable)

T3 Count X 4 3 2 1 4 3 2 1

Interrupt
Request

Figure 28. Example: PRT CONTINUOUS Mode Operation

Table 51. Example: PRT CONTINUOUS Mode Parameters

Parameter Control Register(s) Value

Timer Enable TMRx_CTL[TIM_EN] 1
Reload TMRx_CTL[RLD] 1
Prescaler Divider = 4 TMRx_CTL[CLK_DIV] 00b
CONTINUOUS Mode TMRx_CTL[TIM_CONT] 1
End of Count Interrupt Enable TMRx_IER[IRQ_EOC_EN] 1
Timer Reload Value {TMRx_RR_H, TMRx_RR_L} 0004h

Timer Interrupts
The terminal count flag (TMRx_IIR[EOC]) is set to 1 whenever the timer reaches 0000h,
its end-of-count value in SINGLE PASS mode, or when the timer reloads the start value in
CONTINUOUS mode. The terminal count flag is only set when the timer reaches 0000h
(or reloads) from 0001h. The timer interrupt flag is not set to 1 when the timer is loaded
with the value 0000h, which selects the maximum time-out period.
The CPU is programmed to poll the EOC bit for the time-out event. Alternatively, an inter-
rupt service request signal is sent to the CPU by setting the TMRx_IER[EOC] bit to 1.

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And when the end-of-count value (0000h) is reached, the EOC bit is set to 1 and an inter-
rupt service request signal is passed to the CPU. The interrupt service request signal is
deactivated by a CPU read of the timer interrupt identification register, TMRx_IIR.
All bits in that register are reset by the Read.
The response of the CPU to this interrupt service request is a function of the CPU’s inter-
rupt enable flag, IEF1. For more information about this flag, refer to the eZ80® CPU User
Manual (UM0077) available on www.zilog.com.

Timer Input Source Selection

Timers 0–3 features programmable input source selection. By default, the input is taken
from the eZ80F91’s system clock. The timers also use the Real-Time Clock source (50,
60, or 32768 Hz) as their clock sources. The input source for these timers is set using the
timer control register. (TMRx_CTL[CLK_SEL])

Timer Output
The timer count is directed to the GPIO output pins, if required. To enable the Timer
Output feature, the GPIO port pin must be configured as an output and for alternate func-
tions. The GPIO output pin toggles each time the timer reaches its end-of-count value.
In CONTINUOUS mode operation, enabling the Timer Output feature results in a Timer
Output signal period which is twice the timer time-out period. Examples of Timer Output
operation is displayed in Figure 29 on page 126 and listed in Table 52 on page 126. The
initial value for the timer output is zero.
Logic to support timer output exists in all timers; but for the eZ80F91 device, only Timer
0 and 2 route the actual timer output to the pins. Because Timer 3 uses the TOUT pins for
PWMxN signals, the timer outputs are not available when using complementary PWM
outputs. See Table 52 on page 126 for details.

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Break Point Halting

System Clock

Clock Enable

TMR3_CTL Write
(Timer Enable)

T3 Count 0 4 3 2 1 4 3 2 1

Timer Out
(internal)

Timer Out
(at pad)

Figure 29. Example: PRT Timer Output Operation

Table 52. Example: PRT Timer Out Parameters

Parameter Control Register(s) Value

Timer Enable TMRx_CTL[TIM_EN] 1
Reload TMRx_CTL[RLD] 1
Prescaler Divider = 4 TMRx_CTL[CLK_DIV] 00b
CONTINUOUS Mode TMRx_CTL[TIM_CONT] 1
Timer Reload Value {TMRx_RR_H, TMRx_RR_L} 0003h

When the eZ80F91 device is running in DEBUG mode, encountering a break point causes
all CPU functions to halt. However, the timers keep running. This instance makes debug-
ging timer-related software much more difficult. Therefore, the control
register contains a BRK_STP bit. Setting this bit causes the count value to be held during
debug break points.

Specialty Timer Modes

The features described above are common to all timers in the eZ80F91 device. In addition
to these common features, some of the timers have additional functionality.

The following is a list of the special features for each timer:

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• Timer 0
– No special functions

• Timer 1
– One event counter (EC0)
– Two input captures (IC0 and IC1)

• Timer 2
– One event counter (EC1)

• Timer 3
– Two input captures (IC2 and IC3)
– Four output compares (OC0, OC1, OC2, and OC3)
– Four PWM outputs (PWM0, PWM1, PWM2, and PWM3)

Timer 3 consists of three specialty modes. Each of these modes are enabled using bits in
their respective control registers (TMR3_CAP_CTL, TMR3_OC_CTL1,
TMR3_PWM_CTL1). When PWM mode is enabled, the OUTPUT COMPARE and
INPUT CAPTURE modes are not available. This instance is due to address space sharing
requirements. However, INPUT CAPTURE and OUTPUT COMPARE modes run
simultaneously.
Timers with specialty modes offer multiple ways to generate an interrupt. When the inter-
rupt controller services a timer interrupt, the software must read the timers interrupt iden-
tification register (TMRx_IIR) to determine the causes for an interrupt request. This
register is cleared each time it is read, allowing subsequent events to be identified without
interference from prior events.

Event Counter
When a timer is configured to take its input from a port input pin (ECx), it functions as an
event counter. For event counting, the clock prescaler is automatically bypassed and edges
(events) cause the timer to decrement. You must select the rising or the falling edge for
counting. Also, the port pins must be configured as inputs.
Input sampling on the port pins results in the counter being updated on the third rising
edge of the system clock after the edge event occurs at the port pin. Due to sampling, the
frequency of the event input is limited to one-half the system clock frequency under ideal
conditions. In practice, the event frequency must be less than this value due to duty cycle
variation and system clock jitter.
This EVENT COUNT mode is identical to basic timer operation, except for the clock
source. Therefore, interrupts are managed in the same manner.

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RTC Oscillator Input

When the timer clock source is the Real-Time Clock (RTC) signal, the timer functions just
as it does in EVENT COUNT mode, except that it samples the internal RTC clock rather
than the ECx pin.

Input Capture
INPUT CAPTURE mode allows the CPU to determine the timing of specified events on a
set of external pins.
A timer intended for use in INPUT CAPTURE mode is setup the same way as in BASIC
mode, with one exception. The CPU must also write the TMRx_CAP_CTL register to
select the edge on which to capture: rising, falling, or both. When one of these events
occurs on an input capture pin, the current 16 bit timer value is latched into the capture
value register pair (TMRx_CAP_A or TMRx_CAP_B depending on the IC pin exhibiting
the event).
Reading the Low byte of the register pair causes the timer to ignore other capture events
on the associated external pin until the High byte is read. This instance prevents a
subsequent capture event from overwriting the High byte between the two Reads and
generating an invalid capture value. The capture value registers are Read Only.
A capture flag (ICA or ICB) in the TMRx_IIR register is set whenever a capture event
occurs. Setting the interrupt identification register bit TMRx_IER[IRQ_ICx_EN] enables
the capture event to generate a timer interrupt. The port pins must be configured as
alternate functions, see GPIO Mode 7—Alternate Functions on page 51.

Output Compare
The output compare function reverses the input capture function. Rather than store a timer
value when an external event occurs, OUTPUT COMPARE mode waits until the timer
reaches a specified value, then generates an external event. Although the same base timer
is used, up to four separate external pins are driven each with its own compare value.
To use OUTPUT COMPARE mode, the CPU must first configure the basic timer
parameters. Then it must load up to four 16-bit compare values into the four TMR3_OCx
register pairs. Next, it must load the TMR3_ OC_CTL2 register to specify the event that
occurs on comparison. You can select the following events: SET, CLEAR, and TOGGLE.
Finally, the CPU must enable OUTPUT COMPARE mode by asserting
TMR3_OC_CTL1[OC_EN].
The initial value for the OCx pins in OUTPUT COMPARE mode is 0 by default. It is
possible to initialize this value to 1 or force a value at a later time. Setting the
TMR3_OC_CTL2[OCx_MODE] value to 0 forces the OCx pin to the selected state
provided by the TMR3_OC_CTL1[OCx_INIT] bits. Regardless of any compare events,
the pin stays at the forced value until OCx_MODE is changed. After release, it retains the
forced value until modified by an OUTPUT COMPARE event.

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Asserting TMR3_OC_CTL1[MAST_MODE] selects MASTER MODE for all OUTPUT

COMPARE events and sets output 0 as the master. As a result, outputs 1, 2, and 3 are
caused to disregard output-specific configuration and comparison values and instead
mimic the current settings for output 0.
The OCx bits in the TMR3_IIR register are set whenever the corresponding timer com-
pares occur. TMR3_IER[IRQ_OCx_EN] allows the compare event to generate a timer
interrupt.

Timer Port Pin Allocation

The eZ80F91 device timers interface to the outside world via Ports A and B. These
ports are also used for GPIO as well as other assorted functions. Table 53 on page 129
lists the timer pins and their respective functions.

Table 53. GPIO Mode Selection Using Timer Pins

Timer Function
GPIO Port GPIO Port PWM_CTL1 PWM_CTL1
Port Bits Mode MPWM_EN = 0 MPWM_EN = 1
A PA0 7 OC0 PWM0
PA1 7 OC1 PWM1
PA2 7 OC2 PWM2
PA3 7 OC3 PWM3
PWM_CTL1 PWM_CTL1
PAIR_EN = 0 PAIR_EN = 1
PA4 7 TOUT0 PWM0
PA5 7 TOUT2 PWM1
PA6 7 EC1 PWM2
PA7 7 PWM3
B PB0 7 IC0/EC0
PB1 7 IC1
PB4 7 IC2
PB5 7 IC3

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Timer Registers
The CPU monitors and controls the timer using seven 8-bit registers. These registers are
the control register, the interrupt identification register, the interrupt enable register and
the reload register pair (High and Low byte). There are also a pair of data registers used to
read the current timer count value.
The variable x can be 0, 1, 2, or 3 to represent each of the four available timers.

Basic Timer Register Set

Each timer requires a different set of registers for configuration and control. However,
all timers contain the following seven registers, each of which is necessary for basic
operation:
• Timer Control Register (TMRx_CTL)
• Interrupt Identification Register (TMRx_IIR)
• Interrupt Enable Register (TMRx_IER)
• Timer Data Registers (TMRx_DR_H and TMRx_DR_L)
• Timer Reload Registers (TMRx_RR_H and TMRx_RR_L)

The Timer Data Register is Read Only, when the Timer Reload Register is Write Only.
The address space for these two registers is shared.

Register Set for Capture in Timer 1

In addition to the basic register set, Timer 1 uses the following five registers for its INPUT
CAPTURE mode:
• Capture Control Register (TMR1_CAP_CTL)
• Capture Value Registers (TMR1_CAP_B_H, TMR1_CAP_B_L, TMR1_CAP_A_H,
TMR1_CAP_A_L)

Register Set for Capture/Compare/PWM in Timer 3

In addition to the basic register set, Timer 3 uses 19 registers for INPUT CAPTURE,
OUTPUT COMPARE, and PWM modes. PWM and capture/compare functions cannot be
used simultaneously so, their register address space is shared. INPUT CAPTURE and
OUTPUT COMPARE are used concurrently and their address space is not shared.
The INPUT CAPTURE mode registers are equivalent to those used in Timer 1 above
(substitute TMR3 for TMR1).
OUTPUT COMPARE mode uses the following nine registers:
• Output Compare Control Registers
– TMR3_OC_CTL1

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– TMR3_OC_CTL2
• Compare Value Registers
– TMR3_OC3_H
– TMR3_OC3_L
– TMR3_OC2_H
– TMR3_OC2_L
– TMR3_OC1_H
– TMR3_OC1_L
– TMR3_OC0_H
– TMR3_OC0_L

Multiple PWM mode uses the following 19 registers:

• PWM Control Registers
– TMR3_PWM_CTL1
– TMR3_PWM_CTL2
– TMR3_PWM_CTL3

• PWM Rising Edge Values

– TMR3_PWM3R_H
– TMR3_PWM3R_L
– TMR3_PWM2R_H
– TMR3_PWM2R_L
– TMR3_PWM1R_H
– TMRx_PWM1R_L
– TMR3_PWM0R_H
– TMR3_PWM0R_L

• PWM Falling Edge Values

– TMR3_PWM3F_H
– TMRx_PWM3F_L
– TMR3_PWM2F_H
– TMR3_PWM2F_L
– TMR3_PWM1F_H
– TMR3_PWM1F_L
– TMR3_PWM0F_H
– TMR3_PWM0F_L

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Timer Control Register

The Timer x Control Register (see Table 54) is used to control timer operations including
enabling the timer, selecting the clock source, selecting the clock divider, selecting
between CONTINUOUS and SINGLEPASS modes, and enabling the auto-reload
feature.

Table 54. Timer Control Register (TMR0_CTL = 0060h, TMR1_CTL = 0065h,

TMR2_CTL = 006Fh, TMR3_CTL = 0074h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R = Read only; R/W = Read/Write.

Bit
Position Value Description
0 The timer continues to operate during debug break points.
7
BRK_STOP 1 The timer stops operation and holds count value during debug
break points.
00 Timer source is the system clock divided by the prescaler.
01 Timer source is the Real Time Clock Input.
Timer source is the Event Count (ECx) input—falling edge.
[6:5] 10 For Timer 1 this is EC0.
CLK_SEL For Timer 2, this is EC1.
Timer source is the Event Count (ECx) input—rising edge.
11 For Timer 1 this is EC0.
For Timer 2, this is EC1.
00 System clock divider = 4.

[4:3] 01 System clock divider = 16.

CLK_DIV 10 System clock divider = 64.
11 System clock divider = 256.
The timer operates in SINGLE PASS mode. TIM_EN (bit 0) is
0 reset to 0 and counting stops when the end-of-count value is
2 reached.
TIM_CONT The timer operates in CONTINUOUS mode. The timer reload
1 value is written to the counter when the end-of-count value is
reached.

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0 Reload function is not forced.

1
RLD Force reload. When 1 is written to this bit, the values in the
1
reload registers are loaded into the downcounter.

0 0 The programmable reload timer is disabled.

TIM_EN 1 The programmable reload timer is enabled.

Timer Interrupt Enable Register

The Timer x Interrupt Enable Register (see Table 55) is used to control timer interrupt
operations. Only bits related to functions present in a given timer are active.

Table 55. Timer Interrupt Enable (TMR0_IER = 0061h, TMR1_IER = 0066h,

TMR2_IER = 0070h, TMR3_IER = 0075h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R = Read only; R/W = Read/Write.

Bit
Position Value Description
7 0 Unused.
Interrupt requests for OC3 are disabled (valid only in
0
6 OUTPUT COMPARE mode). OC operations occur in Timer 3.
IRQ_OC3_EN Interrupt requests for OC3 are enabled (valid only in OUTPUT
1
COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC2 are disabled (valid only in
0
5 OUTPUT COMPARE mode). OC operations occur in Timer 3.
IRQ_OC2_EN Interrupt requests for OC2 are enabled (valid only in OUTPUT
1
COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC1 are disabled (valid only in
0
4 OUTPUT COMPARE mode). OC operations occur in Timer 3.
IRQ_OC1_EN Interrupt requests for OC1 are enabled (valid only in OUTPUT
1
COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC0 are disabled (valid only in
0
3 OUTPUT COMPARE mode). OC operations occur in Timer 3.
IRQ_OC0_EN Interrupt requests for OC0 are enabled (valid only in OUTPUT
1
COMPARE mode). OC operations occur in Timer 3.

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Interrupt requests for ICx are disabled (valid only in INPUT

CAPTURE mode).
0
Timer 1: the capture pin is IC1.
2 Timer 3: the capture pin is IC3.
IRQ_ICB_EN Interrupt requests for ICx are enabled (valid only in INPUT
CAPTURE mode).
1
For Timer 1: the capture pin is IC1.
For Timer 3: the capture pin is IC3.
Interrupt requests for ICA or PWM power trip are disabled
(valid only in INPUT CAPTURE and PWM modes).
0
For Timer 1: the capture pin is IC0.
1 For Timer 3: the capture pin is IC2.
IRQ_ICA_EN Interrupt requests for ICA or PWM power trip are enabled
(valid only in INPUT CAPTURE and PWM modes).
1
For Timer 1: the capture pin is IC0.
For Timer 3: the capture pin is IC2.

0 0 Interrupt on end-of-count is disabled.

IRQ_EOC_EN 1 Interrupt on end-of-count is enabled.

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Timer Interrupt Identification Register

The TImer x Interrupt Identification Register (see Table 56) is used to flag timer events so
that the CPU determines the cause of a timer interrupt. This register is cleared by a CPU
Read.

Table 56. Timer Interrupt Identification Register (TMR0_IIR = 0062h, TMR1_IIR =

0067h, TMR2_IIR = 0071h, TMR3_IIR = 0076h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read only;

Bit
Position Value Description
7 0 Unused.

6 0 Output compare, OC3, does not occur.

OC3 1 Output compare, OC3, occurs.

5 0 Output compare, OC2, does not occur.

OC2 1 Output compare, OC2, occurs.

4 0 Output compare, OC1, does not occur.

OC1 1 Output compare, OC1, occurs.

3 0 Output compare, OC0, does not occur.

OC0 1 Output compare, OC0, occurs.
Input capture, ICB, does not occur.
0 For Timer 1, the capture pin is IC1.
2 For Timer 3, the capture pin is IC3.
ICB Input capture, ICB, occurs.
1 For Timer 1, the capture pin is IC1.
For Timer 3, the capture pin is IC3.
Input capture, ICA, or PWM power trip does not occur.
0 For Timer 1, the capture pin is IC0.
1 For Timer 3, the capture pin is IC2.
ICA Input capture, ICA, or PWM power trip occurs.
1 For Timer 1, the capture pin is IC0.
For Timer 3, the capture pin is IC2.

0 0 End-of-count does not occur.

EOC 1 End-of-count occurs.

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Timer Data Register—Low Byte

The Timer x Data Register—Low Byte returns the Low byte of the current count value of
the selected timer. The Timer Data Register—Low Byte (see Table 57) is read when the
timer is in operation. Reading the current count value does not affect timer
operation. To read the 16-bit data of the current count value, {TMRx_DR_H[7:0],
TMRx_DR_L[7:0]}, first read the Timer Data Register—Low Byte, followed by the
Timer Data Register—High Byte. The Timer Data Register—High Byte value is latched
into temporary storage when a Read of the Timer Data Register—Low Byte occurs.
This register shares its address with the corresponding timer reload register.

Table 57. Timer Data Register—Low Byte (TMR0_DR_L = 0063h, TMR1_DR_L =

0068h, TMR2_DR_L = 0072h, TMR3_DR_L = 0077h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read only.

Bit
Position Value Description
These bits represent the Low byte of the 2-byte timer data
[7:0] value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 7
00h–FFh
TMR_DR_L of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16-bit
timer data value.

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Timer Data Register—High Byte

The Timer x Data Register—High Byte returns the High byte of the count value of the
selected timer as it existed at the time that the Low byte was read. The Timer Data
Register—High Byte (see Table 58) is read when the timer is in operation. Reading the
current count value does not affect timer operation. To read the 16-bit data of the
current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}, first read the Timer Data
Register—Low Byte followed by the Timer Data Register—High Byte. The Timer Data
Register—High Byte value is latched into temporary storage when a Read of the Timer
Data Register—Low Byte occurs.
This register shares its address with the corresponding timer reload register.

Table 58. Timer Data Register—High Byte (TMR0_DR_H = 0064h, TMR1_DR_H =

0069h, TMR2_DR_H = 0073h, TMR3_DR_H = 0078h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read only.

Bit
Position Value Description
These bits represent the High byte of the 2-byte timer data
[7:0] value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 15
00h–FFh
TMR_DR_H (msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-bit
timer data value.

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Timer Reload Register—Low Byte

The Timer x Reload Register—Low Byte (see Table 59) stores the least-significant byte
(LSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is
reloaded into the timer on end-of-count. When the reload bit (TMRx_CTL[RLD]) is set to
1 forcing the reload function, the timer reload value is written to the timer on the next ris-
ing edge of the clock.
This register shares its address with the corresponding timer data register.

Table 59. Timer Reload Register—Low Byte (TMR0_RR_L = 0063h, TMR1_RR_L

= 0068h, TMR2_RR_L = 0072h, TMR3_RR_L = 0077h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access W W W W W W W W
Note: W = Write Only.

Bit
Position Value Description
These bits represent the Low byte of the 2-byte timer
[7:0] reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7
00h–FFh
TMR_RR_L is bit 7 of the 16-bit timer reload value. Bit 0 is bit 0 (lsb) of
the 16-bit timer reload value.

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Timer Reload Register—High Byte

The Timer x Reload Register—High Byte (see Table 60) stores the most-significant byte
(MSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is
reloaded into the timer upon end-of-count. When the reload bit (TMRx_CTL[RLD]) is set
to 1, it forces the reload function, the timer reload value is written to the timer on the next
rising edge of the clock.
This register shares its address with the corresponding timer data register.

Table 60. Timer Reload Register—High Byte (TMR0_RR_H = 0064h,

TMR1_RR_H = 0069h, TMR2_RR_H = 0073h, TMR3_RR_H = 0078h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access W W W W W W W W
Note: W = Write Only.

Bit
Position Value Description
These bits represent the High byte of the 2-byte timer
[7:0] reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7
00h–FFh
TMR_RR_H is bit 15 (msb) of the 16-bit timer reload value. Bit 0 is bit 8
of the 16-bit timer reload value.

Timer Input Capture Control Register

The Timer x Input Capture Control Register (see Table 61) is used to select the edge or
edges to be captured. For Timer 1, CAP_EDGE_B is used for IC1 and CAP_EDGE_A is
for IC0. For Timer 3, CAP_EDGE_B is for IC3, and CAP_EDGE_A is for IC2.

Table 61. Timer Input Capture Control Register

(TMR1_CAP_CTL = 006Ah, TMR3_CAP_CTL = 007Bh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R = Read only; R/W = Read/Write.

Bit
Position Value Description
[7:4] 0000 Reserved

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00 Disable capture on ICB.

[3:2] 01 Enable capture only on the falling edge of ICB.

CAP_EDGE_B 10 Enable capture only on the rising edge of ICB.
11 Enable capture on both edges of ICB.
00 Disable capture on ICA.

[1:0] 01 Enable capture only on the falling edge of ICA

CAP_EDGE_A 10 Enable capture only on the rising edge of ICA.
11 Enable capture on both edges of ICA.

Timer Input Capture Value A Register—Low Byte

The Timer x Input Capture Value A Register—Low Byte (see Table 62) stores the Low
byte of the capture value for external input A. For Timer 1, the external input is IC0. For
Timer 3, it is IC2.

Table 62. Timer Input Capture Value Register A—Low Byte (TMR1_CAPA_L =
006Bh, TMR3_CAPA_L = 007Ch)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read only.

Bit
Position Value Description
These bits represent the Low byte of the 2-byte capture
[7:0] value, {TMRx_CAPA_H[7:0], TMRx_CAPA_L[7:0]}. Bit 7 is
00h–FFh
TMRx_CAPA_L bit 7 of the 16-bit data value. Bit 0 is bit 0 (lsb) of the 16-bit
timer data value.

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Timer Input Capture Value A Register—High Byte

The Timer x Input Capture Value A Register—High Byte (see Table 63) stores the High
byte of the capture value for external input A. For Timer 1, the external input is IC0. For
Timer 3, it is IC2.

Table 63. Timer Input Capture Value Register A—High Byte (TMR1_CAPA_H
= 006Ch, TMR3_CAPA_H = 007Dh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read only.

Bit
Position Value Description
These bits represent the High byte of the 2-byte capture
[7:0] value, {TMRx_CAPA_H[7:0], TMRx_CAPA_L[7:0]}. Bit 7 is
00h–FFh
TMRx_CAPA_H bit 15 (msb) of the 16-bit data value. Bit 0 is bit 8 of the 16-
bit timer data value.

Timer Input Capture Value B Register—Low Byte

The Timer x Input Capture Value B Register—Low Byte (see Table 64) stores the Low
byte of the capture value for external input B. For Timer 1, the external input is IC1. For
Timer 3, it is IC3.

Table 64. Timer Input Capture Value Register B—Low Byte (TMR1_CAPB_L =
006Dh, TMR3_CAPB_L = 007Eh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read only.

Bit
Position Value Description
These bits represent the Low byte of the 2-byte capture
[7:0] value, {TMRx_CAPB_H[7:0], TMRx_CAPB_L[7:0]}. Bit 7 is
00h–FFh
TMRx_CAPB_L bit 7 of the 16-bit data value. Bit 0 is bit 0 (lsb) of the
16-bit timer data value.

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Timer Input Capture Value B Register—High Byte

The Timer x Input Capture Value B Register—High Byte (see Table 65) stores the High
byte of the capture value for external input B. For Timer 1, the external input is IC0. For
Timer 3, it is IC3.

Table 65. Timer Input Capture Value Register B—High Byte (TMR1_CAPB_H
= 006Eh, TMR3_CAPB_H = 007Fh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read only.

Bit
Position Value Description
These bits represent the High byte of the 2-byte capture
[7:0] value, {TMRx_CAPB_H[7:0], TMRx_CAPB_L[7:0]}. Bit 7 is
00h–FFh
TMRx_CAPB_H bit 15 (msb) of the 16-bit data value. Bit 0 is bit 8 of the 16-
bit timer data value.

Timer Output Compare Control Register 1

The Timer3 Output Compare Control Register 1 (see Table 66) is used to select the Master
Mode and to provide initial values for the OC pins.

Table 66. Timer Output Compare Control Register 1 (TMR3_OC_CTL1 = 0080h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R = Read only; R/W = Read/Write.

Bit
Position Value Description
[7:6] 00 Unused.

5 0 OC pin cleared when initialized.

OC3_INIT 1 OC pin set when initialized.

4 0 OC pin cleared when initialized.

OC2_INIT 1 OC pin set when initialized.

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3 0 OC pin cleared when initialized.

OC1_INIT 1 OC pin set when initialized.

2 0 OC pin cleared when initialized.

OC0_INIT 1 OC pin set when initialized.

1 0 OC pins are independent.

MAST_MODE 1 OC pins all mimic OC0.

0 0 OUTPUT COMPARE mode is disabled.

OC_EN 1 OUTPUT COMPARE mode is enabled.

Timer Output Compare Control Register 2

The Timer3 Output Compare Control Register 2 (see Table 67) is used to select the event
that occurs on the output compare pins when a timer compare happens.

Table 67. Timer Output Compare Control Register 2 (TMR3_OC_CTL2 = 0081h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
Initialize OC pin to value specified in
00
TMR3_OC_CTL1[OC3_INT].
[7:6] 01 OC pin is cleared upon timer compare.
OC3_MODE
10 OC pin is set upon timer compare.
11 OC pin toggles upon timer compare.
Initialize OC pin to value specified in
00
TMR3_OC_CTL1[OC2_INT].
[5:4] 01 OC pin is cleared upon timer compare.
OC2_MODE
10 OC pin is set upon timer compare.
11 OC pin toggles upon timer compare.

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Initialize OC pin to value specified in

00
TMR3_OC_CTL1[OC1_INT].
[3:2] 01 OC pin is cleared upon timer compare.
OC1_MODE
10 OC pin is set upon timer compare.
11 OC pin toggles upon timer compare.
Initialize OC pin to value specified in
00
TMR3_OC_CTL1[OC0_INT].
[1:0] 01 OC pin is cleared upon timer compare.
OC0_MODE
10 OC pin is set upon timer compare.
11 OC pin toggles upon timer compare.

Timer Output Compare Value Register—Low Byte

The Timer3 Output Compare x Value Register—Low Byte (see Table 68) stores the Low
byte of the compare value for OC0–OC3.

Table 68. Compare Value Register—Low Byte (TMR3_OC0_L = 0082h,

TMR3_OC1_L = 0084h, TMR3_OC2_L = 0086h, TMR3_OC3_L = 0088h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
These bits represent the Low byte of the 2-byte compare
[7:0] value, {TMR3_OCx_H[7:0], TMR3_OCx_L[7:0]}. Bit 7 is bit
00h–FFh
TMR3_OCx_L 7 of the 16-bit data value. Bit 0 is bit 0 (lsb) of the 16-bit
timer compare value.

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Timer Output Compare Value Register—High Byte

The Timer3 Output Compare x Value Register—High Byte (see Table 69) stores the High
byte of the compare value for OC0–OC3.

Table 69. Compare Value Register—High Byte (TMR3_OC0_H = 0083h,

TMR3_OC1_H = 0085h, TMR3_OC2_H = 0087h, TMR3_OC3_H = 0089h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
These bits represent the High byte of the 2-byte compare
[7:0] value, {TMR3_OCx_H[7:0], TMR3_OCx_L[7:0]}. Bit 7 is bit
00h–FFh
TMR3_OCx_H 15 (msb) of the 16-bit data value. Bit 0 is bit 8
of the 16-bit timer compare value.

Multi-PWM Mode
The special Multi-PWM mode uses the Timer 3 16-bit counter as the primary timekeeper
to control up to four PWM generators. The 16-bit reload value for Timer 3 sets a common
period for each of the PWM signals. However, the duty cycle and phase for each generator
are independent that is, the High and Low periods for each PWM generator are set inde-
pendently. In addition, each of the four PWM generators are enabled independently.
The eight PWM signals (four PWM output signals and their inverses) are output via Port
A. A functional block diagram of the Multi-PWM is displayed in Figure 30 on page 146.

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16
PWM0 PA0 PWM0 Output
Generator

PA4 PWM0 Output

16
Timer 3 PWM1 PA1 PWM1 Output
16-Bit Binary Generator
Downcounter

16 PA5 PWM1 Output

Timer 3
Count Value
Clock Input

16
PWM2 PA2 PWM2 Output
Generator

PA6 PWM2 Output

16
PWM3 PA3 PWM3 Output
Generator

PA7 PWM3 Output

Figure 30. Multi-PWM Simplified Block Diagram

Setting TMR3_PWM_CTL1[MPWM_EN] to 1 enables Multi-PWM mode. The

TMR3_PWM_CTL1 register bits enable the four individual PWM generators by adjusting
settings according to the list provided in Table 70.

Table 70. Enabling PWM Generators

Enable PWM generator 0 by setting TMR3_PWM_CTL1[PWM0_EN] to 1.

Enable PWM generator 1 by setting TMR3_PWM_CTL1[PWM1_EN] to 1.
Enable PWM generator 2 by setting TMR3_PWM_CTL1[PWM2_EN] to 1.
Enable PWM generator 3 by setting TMR3_PWM_CTL1[PWM3_EN] to 1.

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The inverted PWM outputs PWM0, PWM1, PWM2, and PWM3 are globally enabled by
setting TMR3_PWM_CTL1[PAIR_EN] to 1. The individual PWM generators must be
enabled for the associated inverted PWM signals to be output.
For each of the 4 PWM generators, there is a 16-bit rising edge value
{TMR3_PWMxR_H[PWMxR_H], TMR3_PWMxR_L[PWMxR_L]} and a 16-bit falling
edge value {TMR3_PWMxF_H[PWMxF_H], TMR3_PWMxF_L[PWMxF_L]} for a total
of 16 registers. The rising-edge byte pairs define the timer count at which the PWMx
output transitions from Low to High. Conversely, the falling-edge byte pairs define the
timer count at which the PWMx output transitions from High to Low. On reset, all enabled
PWM outputs begin Low and all PWMx outputs begin High. When the PWMx output is
Low, the logic is looking for a match between the timer count and the rising edge value,
and vice versa. Therefore, in a case in which the rising edge value is the same as the falling
edge value, the PWM output frequency is one-half the rate at which the counter passes
through its entire count cycle (from reload value down to 0000h).
Figure 31and Figure 32 display a simple Multi-PWM output and an expanded view of the
timing, respectively. Associated control values are listed in Table 71 on page 148.

T3 Count 0 C B A 9 8 7 6 5 4 3 2 1 C B A 9 8 7 6 5 4 3 2 1 C B A 9 8 7 6 5 4 3 2 1 C B A

PWM0

PWM0

PWM1

PWM1

Figure 31. Multi-PWM Operation

System Clock

Clock Enable

T3 Count A 9 8 7 6 5 4

Figure 32. Multi-PWM Operation—Expanded View of Timing

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Table 71. Example: Multi-PWM Addressing

Parameter Control Register(s) Value

Timer Reload Value {TMR3_RR_H, TMR3_RR_L} 000Ch
{TMR3_PWM0R_H,
PWM0 rising edge 0008h
TMR3_PWM0R_L}
PWM0 falling edge {TMR3_PWM0F_H, TMR3_PWM0F_L} 0004h
{TMR3_PWM1R_H,
PWM1 rising edge 0006h
TMR3_PWM1R_L}
PWM1 falling edge {TMR3_PWM1F_H, TMR3_PWM1F_L} 0007h
PWM enable TMR3_PWM_CTL1[PAIR_EN] 1
PWM0 enable TMR3_PWM_CTL1[PWM0_EN] 1
PWM1 enable TMR3_PWM_CTL1[PWM1_EN] 1
Multi-PWM enable TMR3_PWM_CTL1[MPWM_EN] 1
Prescaler Divider = 4 TMR3_CTL[CLK_DIV] 00b
PWM nonoverlapping delay = 0 TMR3_PWM_CTL2[PWM_DLY] 0000b

PWM Master Mode

In PWM Master mode, the pair of output signals generated from the PWM0 generator
(PWM0 and PWM0) are directed to all four sets of PWM output pairs. Setting
TMR3_PWM_CTL1[MM_EN] to 1 enables PWM Master mode. Assuming the outputs
are all enabled and no AND/OR gating is used, all four PWM output pairs transition
simultaneously under the direction of PWM0 and PWM0. In PWM Master mode,
the outputs still be gated individually using the AND/OR gating functions described in the
next section. Multi-PWM mode and the individual PWM outputs must be enabled along
with PWM Master mode. It is possible to enable or disable any combination of the four
PWM outputs while running in PWM Master mode.

Modification of Edge Transition Values

Special circuitry is included for the update of the PWM edge transition values. Normal use
requires that these values be updated while the PWM generator is running.
Note: Under certain circumstances, electric motors driven by the PWM logic encounters rough
operation. In other words, cycles are skipped if the PWM waveform edge is not carefully
modified.

Without special consideration, if a PWM generator looks for a particular count to make a
state transition and if the edge transition value changes to a value that already occurred in

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the current counter count-down cycle, then the transition is missed. The PWM generator
holds the current output state until the counter reloads and cycles through to the
appropriate edge transition value again. In effect, an entire cycle of the PWM waveform is
skipped with the signal held at a DC value. The change in PWM waveform duty cycle
from cycle to cycle must be limited to some fraction of a period to avoid rough running.
To avoid unintentional roughness due to timing of the load operation for the register val-
ues in question, the PWM edge transition values are double-buffered and exhibit the
following behavior:
• When the PWM generators are disabled, PWM edge transition values written by the
CPU are immediately loaded into the PWM edge transition registers.
• When the PWM generators are enabled, a PWM edge transition value is loaded into a
buffer register and transferred to its destination register only during a specific transition
event. A rising edge transition value is only loaded upon a falling edge transition event,
and a falling edge transition value is only loaded upon a rising edge transition event.

AND/OR Gating of the PWM Outputs

When in Multi-PWM mode, it is possible for you to turn off PWM propagation to the pins
without disabling the PWM generator. This feature is global and applies to all enabled
PWM generators. The function is implemented by applying digital logic (AND or OR
functions) to combine the corresponding bits in the port output register with the PWM and
PWM outputs.
The AND or OR functions are enabled on all PWM outputs by setting
TMR3_PWM_CTL2[AO_EN] to either a 01b (AND) or 10b (OR). Any other value
disables this feature. Likewise, the AND or OR functions are enabled on all PWM outputs
by setting TMR3_PWM_CTL2[AON_EN] to either a 01b (AND) or 10b (OR). Any
other value disables this feature. A functional block diagram for the AND/OR gating fea-
ture for PWM0 and PWM0 is displayed in Figure 33 on page 150. The functionality for
the other three PWM pairs are identical.

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00

01
PWM0 Signal PADR0 PA0 PWM0 Output
10

11

TMR3_PWM_CTL2[5:4]

00

01
PWM0 Signal PADR4 PA4 PWM0 Output
10

11

TMR3_PWM_CTL2[7:6]

Figure 33. PWM AND/OR Gating Functional Diagram

If you enable the OR function on all PWM outputs and PADR0 is set to 1, then the PWM0
output on PA0 is forced High. Similarly, if you select the AND function on all PWM
outputs and PADR0 is set to a 0, then the PWM0 output on PA0 is forced Low.

PWM Nonoverlapping Output Pair Delays

A delay is added between the falling edge of the PWM (PWM) outputs and the rising edge
of the PWM (PWM) outputs. This delay is set to assure that even with load and output
drive variations there will be no overlap between the falling edge of a PWM (PWM) out-
put and the rising edge of its paired output. The selected delay is global to all four PWM
pairs. The delay duration is software-selectable using the 4-bit field
TMR3_PWM_CTL2[PWM_DLY]. The duration is programmable in units of the system
clock (SCLK), from 0 SCLK periods to 15 SCLK periods. The
TMR3_PWM_CTL2[PWM_DLY] bits are mapped directly to a counter, such that a

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setting of 0000b represents a delay of 0 system clock periods and a setting of 1111b rep-
resents a delay of 15 system clock periods. The PWM delay feature is displayed in
Figure 34 with associated addressing listed in Table 72.
Note: The PWM nonoverlapping delay time must always be defined to be less than the delay
between the rising and falling edges (and the delay between the falling and rising edges)
of all Multi-PWM outputs. In other words, a rising (falling) edge cannot be delayed
beyond the time at which it is subsequently scheduled to fall (rise).

System Clock

Clock Enable

TMR3_Count A 9 8 7 6 5 4 3 2 1 C

PWM0

PWM0

3 x SCLK 3 x SCLK

Figure 34. PWM Nonoverlapping Output Delay

Table 72. PWM Nonoverlapping Output Addressing

Parameter Control Register(s) Value

Timer clock is SCLK ÷ 4 TMR3_CTL[CLK_DIV] 00b
Timer reload value {TMR3_RR_H, TMR3_RR_L} 000Ch
PWM0 rising edge {TMR3_PWM0R_H, TMR3_PWM0R_L} 0008h
PWM0 falling edge {TMR3_PWM0F_H, TMR3_PWM0F_L} 0004h
Prescaler divider = 4 TMR3_CTL[CLK_DIV] 00b
PWM nonoverlapping delay = 3 TMR3_PWM_CTL2[PWM_DLY] 0011b
PWM enable TMR3_PWM_CTL1[PAIR_EN] 1
PWM0 enable TMR3_PWM_CTL1[PWM0_EN] 1
Multi-PWM enable TMR3_PWM_CTL1[MPWN_EN] 1

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Multi-PWM Power-Trip Mode

When enabled, the Multi-PWM power-trip feature forces the enabled PWM outputs to a
predetermined state when an interrupt is generated from an external source via IC0, IC1,
IC2, or IC3. One or multiple external interrupt sources are enabled at any given time. If
multiple sources are enabled, any of the selected external sources trigger an interrupt.
Configuring the PWM_CTL3 register enables or disables interrupt sources. See Table 75
on page 156.
The possible interrupt sources for a Multi-PWM power-trip are:
• IC0—digital input
• IC1—digital input
• IC2—digital input
• IC3—digital input

When the power-trip is detected, TMR3_PWM_CTL3[PTD] is set to 1 to indicate

detection of the power-trip. A value of 0 signifies that no power-trip is detected.
The PWMs are released only after a power-trip when TMR3_PWM_CTL3[PTD] is
written back to 0 by software. As a result, you are allowed to check the conditions of the
motor being controlled before releasing the PWMs. The explicit release also prevents
noise glitches after a power-trip from causing an accidental exit or re-entry of the PWM
power-trip state.
The programmable power-trip states of the PWMs are globally grouped for the PWM out-
puts and the inverting PWM outputs. Upon detection of a power-trip, the PWM outputs
are forced to either a High state, a Low state, or high-impedance. The settings for the
power-trip states are made with power-trip control bits TMR3_PWM_CTL3[PT_LVL],
TMR3_PWM_CTL3[PT_LVL_N], and TMR3_PWM_CTL3[PT_TRI].

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Multi-PWM Control Registers

Pulse-Width Modulation Control Register 1
The PWM Control Register 1 (see Table 73) controls PWM function enables.

Table 73. PWM Control Register 1 (PWM_CTL1 = 0079h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
Global disable of the PWM outputs (PWM outputs enabled
7 0
only).
PAIR_EN
1 Global enable of the PWM and PWM output pairs.

6 0 Disable power-trip feature.

PT_EN 1 Enable power-trip feature.

5 0 Disable Master mode.

MM_EN 1 Enable Master mode.

4 0 Disable PWM generator 3.

pwm3_en 1 Enable PWM generator 3.

3 0 Disable PWM generator 2.

pwm2_en 1 Enable PWM generator 2.

2 0 Disable PWM generator 1.

pwm1_en 1 Enable PWM generator 1.

1 0 Disable PWM generator 0.

PWM0_EN 1 Enable PWM generator 0.

0 0 Disable Multi-PWM mode.

mpwm_en 1 Enable Multi-PWM mode.

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Pulse-Width Modulation Control Register 2

The PWM Control Register 2 (see Table 74) controls pulse-width modulation AND/OR
and edge delay functions.

Table 74. PWM Control Register 2 (PWM_CTL2 = 007Ah)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
00 Disable AND/OR features on PWM

[7:6] 01 Enable AND logic on PWM

AON_EN 10 Enable OR logic on PWM
11 Disable AND/OR features on PWM
00 Disable AND/OR features on PWM

[5:4] 01 Enable AND logic on PWM

AO_EN 10 Enable OR logic on PWM
11 Disable AND/OR features on PWM

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No delay between falling edge of PWM (PWM) and rising

0000
edge of PWM (PWM)
Delay of 1 SCLK periods between falling edge of PWM
0001
(PWM) and rising edge of PWM (PWM)
Delay of 2 SCLK periods between falling edge of PWM
0010
(PWM) and rising edge of PWM (PWM)
Delay of 3 SCLK periods between falling edge of PWM
0011
(PWM) and rising edge of PWM (PWM)
Delay of 4 SCLK periods between falling edge of PWM
0100
(PWM) and rising edge of PWM (PWM)
Delay of 5 SCLK periods between falling edge of PWM
0101
(PWM) and rising edge of PWM (PWM)
Delay of 6 SCLK periods between falling edge of PWM
0110
(PWM) and rising edge of PWM (PWM)
Delay of 7 SCLK periods between falling edge of PWM
0111
[3:0] (PWM) and rising edge of PWM (PWM)
PWM_DLY Delay of 8 SCLK periods between falling edge of PWM
1000
(PWM) and rising edge of PWM (PWM)
Delay of 9 SCLK periods between falling edge of PWM
1001
(PWM) and rising edge of PWM (PWM)
Delay of 10 SCLK periods between falling edge of PWM
1010
(PWM) and rising edge of PWM (PWM)
Delay of 11 SCLK periods between falling edge of PWM
1011
(PWM) and rising edge of PWM (PWM)
Delay of 12 SCLK periods between falling edge of PWM
1100
(PWM) and rising edge of PWM (PWM)
Delay of 13 SCLK periods between falling edge of PWM
1101
(PWM) and rising edge of PWM (PWM)
Delay of 14 SCLK periods between falling edge of PWM
1110
(PWM) and rising edge of PWM (PWM)
Delay of 15 SCLK periods between falling edge of PWM
1111
(PWM) and rising edge of PWM (PWM)

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Pulse-Width Modulation Control Register 3

The PWM Control Register 3 (see Table 75) is used to configure the PWM power trip
functionality.

Table 75. PWM Control Register 3 (PWM_CTL3 = 007Bh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R

Note: R/W = Read/Write; R = Read only.

Bit
Position Value Description

7 0 Power trip disabled on IC3.

PT_IC3_EN 1 Power trip enabled on IC3.

6 0 Power trip disabled on IC2.

PT_IC2_EN 1 Power trip enabled on IC2.

5 0 Power trip disabled on IC1.

PT_IC1_EN 1 Power trip enabled on IC1.

4 0 Power trip disabled on IC0.

PT_IC0_EN 1 Power trip enabled on IC0.

3 0 All PWM trip levels are open-drain.

PT_TRI 1 All PWM trip levels are defined by PT_LVL and PT_LVL_N.

2 0 After power trip, PWMx outputs are set to one.

PT_LVL 1 After power trip, PWMx outputs are set to zero.

1 0 After power trip, PWMx outputs are set to one.

PT_LVL_N 1 After power trip, PWMx outputs are set to zero.

0 0 Power trip has been cleared.

PTD 1 This bit is set after power trip event.

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Pulse-Width Modulation Rising Edge—Low Byte

A parallel 16-bit Write of {TMR3_PWMxR_H[7–0], TMR3_PWMxR_L[7–0]} occurs
when software initiates a Write to TMR3_PWMxR_L. The register is listed in
Table 76.

Table 76. PWMx Rising-Edge Register—Low Byte (TMR3_PWM0R_L = 007Ch,

TMR3_PWM1R_L = 007Eh, TMR3_PWM2R_L = 0080h, TMR3_PWM3R_L = 0082h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
These bits represent the Low byte of the 16-bit value to set the
rising edge COMPARE value for PWMx,
[7:0]
00h–FFh {TMR3_PWMXR_H[7:0], TMR3_PWMXR_L[7:0]}. Bit 7 is bit 7
PWMXR_L
of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the
16-bit timer data value.

Pulse-Width Modulation Rising Edge—High Byte

Writing to TMR3_PWMxR_H stores the value in a temporary holding register. A parallel
16-bit Write of {TMR3_PWMxR_H[7–0], TMR3_PWMxR_L[7–0]} occurs when soft-
ware initiates a Write to TMR3_PWMxR_L. The register is listed in Table 77.

Table 77. PWMx Rising-Edge Register—High Byte (TMR3_PWM0R_H = 007Dh,

TMR3_PWM1R_H = 007Fh, TMR3_PWM2R_H = 0081h, TMR3_PWM3R_H = 0083h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
These bits represent the High byte of the 16-bit value to set the
rising edge COMPARE value for PWMx,
[7:0]
00h–FFh {TMR3_PWMXR_H[7:0], TMR3_PWMXR_L[7:0]}. Bit 7 is bit
PWMXR_H
15 (msb) of the 16-bit timer data value. Bit 0 is bit 8 of the
16-bit timer data value.

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Pulse-Width Modulation Falling Edge—Low Byte

A parallel 16-bit Write of {TMR3_PWMxF_H[7–0], TMR3_PWMxF_L[7–0]} occurs
when software initiates a Write to TMR3_PWMxF_L. The register is listed in Table 78.

Table 78. PWMx Falling-Edge Register—Low Byte (TMR3_PWM0F_L = 0084h,

TMR3_PWM1F_L = 0086h, TMR3_PWM2F_L = 0088h, TMR3_PWM3F_L = 008Ah)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
These bits represent the Low byte of the 16-bit value to set the
falling edge COMPARE value for PWMx,
[7:0]
00h–FFh {TMR3_PWMXF_H[7:0], TMR3_PWMXF_L[7:0]}. Bit 7 is bit 7
PWMXF_L
of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the
16-bit timer data value.

Pulse-Width Modulation Falling Edge—High Byte

Writing to TMR3_PWMxF_H stores the value in a temporary holding register. A parallel
16-bit Write of {TMR3_PWMxF_H[7–0], TMR3_PWMxF_L[7–0]} occurs when
software initiates a Write to TMR3_PWMxF_L. The register is listed in Table 79.

Table 79. PWMx Falling-Edge Register—High Byte (TMR3_PWM0F_H = 0085h,

TMR3_PWM1F_H = 0087h, TMR3_PWM2F_H = 0089h, TMR3_PWM3F_H = 008Bh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
These bits represent the High byte of the 16-bit value to set the
falling edge COMPARE value for PWMx,
[7:0]
00h–FFh {TMR3_PWMXF_H[7:0], TMR3_PWMXF_L[7:0]}. Bit 7 is bit 15
PWMXF_H
(msb) of the 16-bit timer data value. Bit 0 is bit 8 of the
16-bit timer data value.

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Real-Time Clock
Real-Time Clock Overview
The Real-Time Clock (RTC) maintains time by keeping count of seconds, minutes, hours,
day-of-the-week, day-of-the-month, year, and century. The current time is kept in 24-hour
format. The format for all count and alarm registers is selectable between binary and
binary-coded-decimal (BCD) operations. The calendar operation maintains the correct
day-of-the-month and automatically compensates for leap year only when binary-coded-
decimal operation is enabled. A simplified block diagram of the RTC and the associated
on-chip, low-power, 32 kHz oscillator is displayed in Figure 35. Connections to an
external battery supply and 32 kHz crystal network is also displayed in Figure 35.
Note: For users NOT using the RTC the following RTC signal pins must be connected as follows
to avoid a 10 uA leakage within the RTC circuit block. RTC_Xin (pin 61) must be left float-
ing or connected to ground.

RTC_VDD

VDD Battery
IRQ
to eZ80 CPU

Real-Time Clock
ADDR[15:0]

DATA[7:0]
R1
RTC Clock RTC_XOUT

C
System Clock Low-Power
32 KHz Oscillator
VDD 32 KHz
Crystal

Enable

CLK_SEL
(RTC_CTRL[4])
RTC_XIN

Figure 35. Real-Time Clock and 32 kHz Oscillator Block Diagram

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Real-Time Clock Alarm

The clock is programmed to generate an alarm condition when the current count matches
the alarm set-point registers. Alarm registers are available for seconds, minutes, hours, and
day-of-the-week. Each alarm is independently enabled. To generate an alarm condition,
the current time must match all enabled alarm values. For example, if the day-of-the-week
and hour alarms are both enabled, the alarm only occurs at a specified hour on a specified
day. The alarm triggers an interrupt if the interrupt enable bit, INT_EN, is set to 1. The
alarm flag, ALARM, and corresponding interrupt to the CPU are cleared by reading the
RTC_CTRL register.
Alarm value registers and alarm control registers are written at any time. Alarm conditions
are generated when the count value matches the alarm value. The comparison of alarm and
count values occurs whenever the RTC count increments (one time every second). The
RTC is also forced to perform a comparison at any time by writing a 0 to the
RTC_UNLOCK bit (the RTC_UNLOCK bit is not required to be changed to a 1 first).

Real-Time Clock Oscillator and Source Selection

The RTC count is driven by either the on-chip 32 kHz RTC oscillator or an external
50/60 Hz CMOS-level clock signal (typically derived from the AC power line frequency).
The on-chip oscillator requires an external 32 kHz crystal connected to RTC_XIN and
RTC_XOUT as displayed in Figure 35 on page 159. If an external 50/60 Hz clock signal is
used, connect it to RTC_XOUT.
The clock source and power-line frequencies are selected in the RTC_CTRL register.
Writing to the RTC_CTRL register resets the clock divider.

Real-Time Clock Battery Backup

The power supply pin (RTC_VDD) for the RTC and associated low-power 32 kHz
oscillator is isolated from the other power supply pins on the eZ80F91 device. To ensure
that the RTC continues to keep time in the event of loss of line power to the application, a
battery is used to supply power to the RTC and the oscillator via the RTC_VDD pin. All
VSS (ground) pins must be connected together on the printed circuit assembly.

Real-Time Clock Recommended Operation

Following a initial system reset from a power-down condition of VDD and VDD_RTC, the
counter values of the RTC are undefined and all alarms are disabled. The following proce-
dure is recommended to initialize the Real-Time Clock:
• Write to RTC_CTRL to set RTC_UNLOCK and disable the RTC counter; this action
also clears the clock divider

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• Write values to the RTC count registers to set the current time
• Write values to the RTC alarm registers to set the appropriate alarm conditions
• Write to RTC_CTRL to clear RTC_UNLOCK; clearing the RTC_UNLOCK bit resets
and enables the clock divider

Real-Time Clock Registers

The RTC registers are accessed via the address and data buses using I/O instructions. The
RTC_UNLOCK control bit controls access to the RTC count registers. When unlocked
(RTC_UNLOCK = 1), the RTC count is disabled and the count registers are Read/Write.
When locked (RTC_UNLOCK = 0), the RTC count is enabled and the count registers are
Read Only. The default at RESET is for the RTC to be locked.

Real-Time Clock Seconds Register

This register contains the current seconds count. The value in the RTC_SEC register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values
in this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1).
Access to this register is Read Only if the RTC is locked, and Read/Write if the RTC is
unlocked. See Table 80.

Table 80. Real-Time Clock Seconds Register (RTC_SEC = 00E0h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit Position Value Description

[7:4] 0–5 The tens digit of the current seconds count.
TEN_SEC
[3:0] 0–9 The ones digit of the current seconds count.
SEC

Binary Operation (BCD_EN = 0)

Bit Position Value Description

[7:0] 00h–3Bh The current seconds count.
SEC

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Real-Time Clock Minutes Register

This register contains the current minutes count. The value in the RTC_MIN register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values
in this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1).
Access to this register is Read Only if the RTC is locked, and Read/Write if the RTC is
unlocked. See Table 81.

Table 81. Real-Time Clock Minutes Register (RTC_MIN = 00E1h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded Decimal Operation (BCD_EN = 1)

Bit Position Value Description

[7:4] 0–5 The tens digit of the current minutes count.
TEN_MIN
[3:0] 0–9 The ones digit of the current minutes count.
MIN

Binary Operation (BCD_EN = 0)

Bit Position Value Description

[7:0] 00h–3Bh The current minutes count.
MIN

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Real-Time Clock Hours Register

This register contains the current hours count. The value in the RTC_HRS register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values
in this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1).
Access to this register is Read Only if the RTC is locked, and Read/Write if the RTC is
unlocked. See Table 82.

Table 82. Real-Time Clock Hours Register (RTC_HRS = 00E2h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded Decimal Operation (BCD_EN = 1)

Bit Position Value Description

[7:4] 0–2 The tens digit of the current hours count.
TEN_HRS
[3:0] 0–9 The ones digit of the current hours count.
HRS

Binary Operation (BCD_EN = 0)

Bit Position Value Description

[7:0] 00h–17h The current hours count.
HRS

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Real-Time Clock Day-of-the-Week Register

This register contains the current day-of-the-week count. The RTC_DOW register begins
counting at 01h. The value in the RTC_DOW register is unchanged by a RESET. The
current setting of BCD_EN determines whether the value in this register is binary
(BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to this register is Read
Only if the RTC is locked and Read/Write if the RTC is unlocked. See Table 83.

Table 83. Real-Time Clock Day-of-the-Week Register (RTC_DOW = 00E3h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 X X X X

CPU Access R R R R R/W* R/W* R/W* R/W*

Note: X = Unchanged by RESET; R = Read Only; R/W* = Read Only if RTC locked, Read/Write
if RTC unlocked.

Binary-Coded Decimal Operation (BCD_EN = 1)

Bit Position Value Description

[7:4] 0000 Reserved.
[3:0] 1–7 The current day-of-the-week.count.
DOW

Binary Operation (BCD_EN = 0)

Bit Position Value Description

[7:4] 0000 Reserved.
[3:0] 01h–07h The current day-of-the-week count.
DOW

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Real-Time Clock Day-of-the-Month Register

This register contains the current day-of-the-month count. The RTC_DOM register begins
counting at 01h. The value in the RTC_DOM register is unchanged by a RESET. The
current setting of BCD_EN determines whether the values in this register are binary
(BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to this register is Read
Only if the RTC is locked, and Read/Write if the RTC is unlocked. See Table 84.

Table 84. Real-Time Clock Day-of-the-Month Register (RTC_DOM = 00E4h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded Decimal Operation (BCD_EN = 1)

Bit Position Value Description

[7:4] 0–3 The tens digit of the current day-of-the-month count.
TENS_DOM
[3:0] 0–9 The ones digit of the current day-of-the-month count.
DOM

Binary Operation (BCD_EN = 0)

Bit Position Value Description

[7:0] 01h–1Fh The current day-of-the-month count.
DOM

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Real-Time Clock Month Register

This register contains the current month count. The RTC_MON register begins counting at
01h. The value in the RTC_MON register is unchanged by a RESET. The current setting
of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) or
binary-coded decimal (BCD_EN = 1). Access to this register is Read Only if the RTC is
locked, and Read/Write if the RTC is unlocked. See Table 85.

Table 85. Real-Time Clock Month Register (RTC_MON = 00E5h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded Decimal Operation (BCD_EN = 1)

Bit Position Value Description

[7:4] 0–1 The tens digit of the current month count.
TENS_MON
[3:0] 0–9 The ones digit of the current month count.
MON

Binary Operation (BCD_EN = 0)

Bit Position Value Description

[7:0] 01h–0Ch The current month count.
MON

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Real-Time Clock Year Register

This register contains the current year count. The value in the RTC_YR register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values
in this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1).
Access to this register is Read Only if the RTC is locked, and Read/Write if the RTC is
unlocked. See Table 86.

Table 86. Real-Time Clock Year Register (RTC_YR = 00E6h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded Decimal Operation (BCD_EN = 1)

Bit Position Value Description

[7:4] 0–9 The tens digit of the current year count.
TENS_YR
[3:0] 0–9 The ones digit of the current year count.
YR

Binary Operation (BCD_EN = 0)

Bit Position Value Description

[7:0] 00h–63h The current year count.
YR

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Real-Time Clock Century Register

This register contains the current century count. The value in the RTC_CEN register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values
in this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1).
Access to this register is Read Only if the RTC is locked, and Read/Write if the RTC is
unlocked. See Table 87.

Table 87. Real-Time Clock Century Register (RTC_CEN = 00E7h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit Position Value Description

[7:4] 0–9 The tens digit of the current century count.
TENS_CEN
[3:0] 0–9 The ones digit of the current century count.
CEN

Binary Operation (BCD_EN = 0)

Bit Position Value Description

[7:0] 00h–63h The current century count.
CEN

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Real-Time Clock Alarm Seconds Register

This register contains the alarm seconds value. The value in the RTC_ASEC register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values
in this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). See
Table 88.

Table 88. Real-Time Clock Alarm Seconds Register (RTC_ASEC = 00E8h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: X = Unchanged by RESET; R/W = Read/Write.

Binary-Coded Decimal Operation (BCD_EN = 1)

Bit Position Value Description

[7:4] 0–5 The tens digit of the alarm seconds value.
ATEN_SEC
[3:0] 0–9 The ones digit of the alarm seconds value.
ASEC

Binary Operation (BCD_EN = 0)

Bit Position Value Description

[7:0] 00h–3Bh The alarm seconds value.
ASEC

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Real-Time Clock Alarm Minutes Register

This register contains the alarm minutes value. The value in the RTC_AMIN register is
unchanged by a RESET. The current setting of BCD_EN determines whether the
values in this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1).
See Table 89.

Table 89. Real-Time Clock Alarm Minutes Register (RTC_AMIN = 00E9h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: X = Unchanged by RESET; R/W = Read/Write.

Binary-Coded Decimal Operation (BCD_EN = 1)

Bit Position Value Description

[7:4] 0–5 The tens digit of the alarm minutes value.
ATEN_MIN
[3:0] 0–9 The ones digit of the alarm minutes value.
AMIN

Binary Operation (BCD_EN = 0)

Bit Position Value Description

[7:0] 00h–3Bh The alarm minutes value.
AMIN

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Real-Time Clock Alarm Hours Register

This register contains the alarm hours value. The value in the RTC_AHRS register is
unchanged by a RESET. The current setting of BCD_EN determines whether the
values in this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN =
1). See Table 90.

Table 90. Real-Time Clock Alarm Hours Register (RTC_AHRS = 00EAh)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: X = Unchanged by RESET; R/W = Read/Write.

Binary-Coded Decimal Operation (BCD_EN = 1)

Bit Position Value Description

[7:4] 0–2 The tens digit of the alarm hours value.
ATEN_HRS
[3:0] 0–9 The ones digit of the alarm hours value.
AHRS

Binary Operation (BCD_EN = 0)

Bit Position Value Description

[7:0] 00h–17h The alarm hours value.
AHRS

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Real-Time Clock Alarm Day-of-the-Week Register

This register contains the alarm day-of-the-week value. The value in the RTC_ADOW
register is unchanged by a RESET. The current setting of BCD_EN determines whether
the value in this register is binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1).
See Table 91.

Table 91. Real-Time Clock Alarm Day-of-the-Week Register (RTC_ADOW = 00EBh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 X X X X

CPU Access R R R R R/W* R/W* R/W* R/W*

Note: X = Unchanged by RESET; R = Read Only; R/W* = Read Only if RTC locked, Read/Write if
RTC unlocked.

Binary-Coded Decimal Operation (BCD_EN = 1)

Bit Position Value Description

[7:4] 0000 Reserved.
[3:0] 1–7 The alarm day-of-the-week value.
ADOW

Binary Operation (BCD_EN = 0)

Bit Position Value Description

[7:4] 0000 Reserved.
[3:0] 01h–07h The alarm day-of-the-week value.
ADOW

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Real-Time Clock Alarm Control Register

This register contains control bits for the Real-Time Clock. The RTC_ACTRL register is
cleared by a RESET. See Table 92.

Table 92. Real-Time Clock Alarm Control Register (RTC_ACTRL = 00ECh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R/W R/W R/W R/W

Note: X = Unchanged by RESET; R = Read Only; R/W = Read/Write

Bit Position Value Description

[7:4] 0000 Reserved.
3 0 The day-of-the-week alarm is disabled.
ADOW_EN
1 The day-of-the-week alarm is enabled.
2 0 The hours alarm is disabled.
AHRS_EN
1 The hours alarm is enabled.
1 0 The minutes alarm is disabled.
AMIN_EN
1 The minutes alarm is enabled.
0 0 The seconds alarm is disabled.
ASEC_EN
1 The seconds alarm is enabled.

Real-Time Clock Control Register

This register contains control and status bits for the Real-Time Clock. Some bits in the
RTC_CTRL register are cleared by a RESET. The ALARM bit flag and associated inter-
rupt (if INT_EN is enabled) are cleared by reading this register. The ALARM bit flag is
updated by clearing (locking) the RTC_UNLOCK bit or by an increment of the RTC
count. Writing to the RTC_CTRL register also resets the RTC count prescaler allowing the
RTC to be synchronized to another time source.
SLP_WAKE indicates if an RTC alarm condition initiated the CPU recovery from SLEEP
mode. This bit is checked after RESET to determine if a sleep-mode recovery is caused by
the RTC. SLP_WAKE is cleared by a Read of the RTC_CTRL register.
Setting the BCD_EN bit causes the RTC to use binary-coded decimal (BCD) counting in
all registers including the alarm set points.
The CLK_SEL and FREQ_SEL bits select the RTC clock source. If the 32 KHz crystal
option is selected, the oscillator is enabled and the internal prescaler is set to divide by

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32768. If the power-line frequency option is selected, the prescale value is set by the
FREQ_SEL bit, and the 32 kHz oscillator is disabled. See Table 93.

Table 93. Real-Time Clock Control Register (RTC_CTRL = 00EDh)

Bit 7 6 5 4 3 2 1 0
Reset X 0 X X X X 0/1 0

CPU Access R R/W R/W R/W R/W R/W R R/W

Note: X = Unchanged by RESET; R = Read Only; R/W = Read/Write.

Bit Position Value Description

7 0 Alarm interrupt is inactive.
ALARM
1 Alarm interrupt is active.
6 0 Interrupt on alarm condition is disabled.
INT_EN
1 Interrupt on alarm condition is enabled.
5 0 RTC count and alarm value registers are binary.
BCD_EN
1 RTC count and alarm value registers are BCD.
4 0 RTC clock source is crystal oscillator output (32768 Hz).
CLK_SEL On-chip 32768Hz oscillator is enabled.
1 RTC clock source is power-line frequency input.
On-chip 32768 Hz oscillator is disabled.
3 0 Power-line frequency is 60 Hz.
FREQ_SEL
1 Power-line frequency is 50 Hz.
2 0 Suggested value for Daylight Savings Time not selected.
DAY_SAV
1 Suggested value for Daylight Savings Time selected.
This register bit has been allocated as a storage location only
for software applications that use DST. No action is performed
in the eZ80F91 when setting or clearing this bit.
1 0 RTC did not generate a sleep-mode recovery reset.
SLP_WAKE
1 RTC Alarm generated a sleep-mode recovery reset.
0 0 RTC count registers are locked to prevent write access.
RTC_UNLOCK RTC counter is enabled.
1 RTC count registers are unlocked to allow write access.
RTC counter is disabled.

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Universal Asynchronous
Receiver/Transmitter
The UART module implements all of the logic required to support the asynchronous com-
munications protocol. The module also implements two separate 16-byte-deep FIFOs for
both transmission and reception. A block diagram of the UART is displayed in Figure 36.

UART Control Interface and Baud Rate Generator

System Clock
Receive RxD0/RxD1
to eZ80 CPU

Buffer
I/O Address
¤

Transmit TxD0/TxD1
Data Buffer

Interrupt Signal
CTS0/CTS1
RTS0/RTS1
Modem
Control DSR0/DSR1
Logic DTR0/DTR1
DCD0/DCD1
RI0/RI1

Figure 36. UART Block Diagram

The UART module provides the following asynchronous communications protocol-

related features and functions:
• 5-, 6-, 7-, 8- or 9-bit data transmission.
• Even/odd, space/mark, address/data, or no parity bit generation and detection.
• Start and stop bit generation and detection (supports up to two stop bits).
• Line break detection and generation.
• Receiver overrun and framing errors detection.
• Logic and associated I/O to provide modem handshake capability.

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UART Functional Description

The UART Baud Rate Generator (BRG) creates the clock for the serial transmit and
receive functions. The UART module supports all of the various options in the asynchro-
nous transmission and reception protocol including:
• 5- to 9-bit transmit/receive
• Start bit generation and detection
• Parity generation and detection
• Stop bit generation and detection
• Break generation and detection
The UART contains 16-byte-deep FIFOs in each direction. The FIFOs are enabled or dis-
abled by the application. The receive FIFO features trigger-level detection logic, which
enables the CPU to block-transfer data bytes from the receive FIFO.

UART Functions
The UART function implements:
• The transmitter and associated control logic
• The receiver and associated control logic
• The modem interface and associated logic

UART Transmitter
The transmitter block controls the data transmitted on the TxD output. It implements the
FIFO, access via the UARTx_THR register, the transmit shift register, the parity generator,
and control logic for the transmitter to control parameters for the asynchronous communi-
cations protocol.
The UARTx_THR is a Write Only register. The CPU writes the data byte to be transmitted
into this register. In FIFO mode, up to 16 data bytes are written via the UARTx_THR reg-
ister. The data byte from the FIFO is transferred to the transmit shift register at the appro-
priate time and transmitted via TxD output. After SYNC_RESET, the UARTx_THR
register is empty. Therefore, the Transmit Holding Register Empty (THRE) bit (bit 5 of
the UARTx_LSR register) is 1. An interrupt is sent to the CPU if interrupts are enabled.
The CPU resets this interrupt by loading data into the UARTx_THR register, which clears
the transmitter interrupt.
The transmit shift register places the byte to be transmitted on the TxD signal serially. The
LSb of the byte to be transmitted is shifted out first and the MSb is shifted out last. The
control logic within the block adds the asynchronous communications protocol bits to the
data byte being transmitted. The transmitter block obtains the parameters for the protocol

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from the bits programmed via the UARTx_LCTL register. When enabled, an interrupt is
generated after the final protocol bit is transmitted which the CPU resets by loading data
into the UARTx_THR register. The TxD output is set to 1 if the transmitter is idle (that is,
the transmitter does not contain any data to be transmitted).
The transmitter operates with the BRG clock. The data bits are placed on the TxD output
one time every 16 BRG clock cycles. The transmitter block also implements a parity gen-
erator that attaches the parity bit to the byte, if programmed. For 9-bit data, the host CPU
programs the parity bit generator so that it marks the byte as either address (mark parity)
or data (space parity).

UART Receiver
The receiver block controls the data reception from the RxD signal. The receiver block
implements a receiver shift register, receiver line error condition monitoring logic and
receiver data ready logic. It also implements the parity checker.
The UARTx_RBR is a Read Only register of the module. The CPU reads received data
from this register. The condition of the UARTx_RBR register is monitored by the DR bit
(bit 0 of the UARTx_LSR register). The DR bit is 1 when a data byte is received and trans-
ferred to the UARTx_RBR register from the receiver shift register. The DR bit is reset
only when the CPU reads all of the received data bytes. If the number of bits received is
less than eight, the unused MSb of the data byte Read are 0.
For 9-bit data, the receiver checks incoming bytes for space parity. A line status interrupt
is generated when an address byte is received, because address bytes maintain high parity
bits. The CPU clears the interrupt by determining if the address matches its own, then con-
figures the receiver to either accept the subsequent data bytes if the address matches, or
ignore the data if the address does not match.
The receiver uses the clock from the BRG for receiving the data. This clock must operate
at 16 times the appropriate baud rate. The receiver synchronizes the shift clock on the fall-
ing edge of the RxD input start bit. It then receives a complete byte according to the set
parameters. The receiver also implements logic to detect framing errors, parity errors,
overrun errors, and break signals.

UART Modem Control

The modem control logic provides two outputs and four inputs for handshaking with the
modem. Any change in the modem status inputs, except RI, is detected and an interrupt is
generated. For RI, an interrupt is generated only when the trailing edge of the RI is
detected. The module also provides LOOP mode for self-diagnostics.

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UART Interrupts
There are six different sources of interrupts from the UART. The six sources of interrupts
are:
• Transmitter (two different interrupts)
• Receiver (three different interrupts)
• Modem status

UART Transmitter Interrupt

A Transmitter Hold Register Empty interrupt is generated if there is no data available in
the hold register. By the same token, a transmission complete interrupt is generated after
the data in the shift register is sent. Both interrupts are disabled using individual interrupt
enable bits, or cleared by writing data into the UARTx_THR register.

UART Receiver Interrupts

A receiver interrupt is generated by three possible events. The first event, a receiver data
ready interrupt event, indicates that one or more data bytes are received and are ready to
be read. Next, this interrupt is generated if the number of bytes in the receiver FIFO is
greater than or equal to the trigger level. If the FIFO is not enabled, the interrupt is gener-
ated if the receive buffer contains a data byte. This interrupt is cleared by reading the
UARTx_RBR.
The second interrupt source is the receiver time-out. A receiver time-out interrupt is gen-
erated when there are fewer data bytes in the receiver FIFO than the trigger level and there
are no Reads and Writes to or from the receiver FIFO for four consecutive byte times.
When the receiver time-out interrupt is generated, it is cleared only after emptying the
entire receive FIFO.
The first two interrupt sources from the receiver (data ready and time-out) share an inter-
rupt enable bit. The third source of a receiver interrupt is a line status error, indicating an
error in byte reception. This error results from:
• Incorrect received parity.

Note: For 9-bit data, incorrect parity indicates detection of an address byte.

• Incorrect framing (that is, the stop bit) is not detected by receiver at the end of the byte.
• Receiver overrun condition.
• A BREAK condition being detected on the receive data input.

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An interrupt due to one of the above conditions is cleared when the UARTx_LSR register
is read. In case of FIFO mode, a line status interrupt is generated only after the received
byte with an error reaches the top of the FIFO and is ready to be read.
A line status interrupt is activated (provided this interrupt is enabled) as long as the Read
pointer of the receiver FIFO points to the location of the FIFO that contains a byte with the
error. The interrupt is immediately cleared when the UARTx_LSR register is read. The
ERR bit of the UARTx_LSR register is active as long as an erroneous byte is present in the
receiver FIFO.

UART Modem Status Interrupt

The modem status interrupt is generated if there is any change in state of the modem status
inputs to the UART. This interrupt is cleared when the CPU reads the UARTx_MSR regis-
ter.

UART Recommended Usage

The following standard sequence of events occurs in the UART block of the eZ80F91
device. A description of each follows.
• Module Reset
• Control Transfers to Configure UART Operation
• Data Transfers

Module Reset
Upon reset, all internal registers are set to their default values. All command status regis-
ters are programmed with their default values, and the FIFOs are flushed.

Control Transfers to Configure UART Operation

Based on the requirements of the application, the data transfer baud rate is determined and
the BRG is configured to generate a 16X clock frequency. Interrupts are disabled and the
communication control parameters are programmed in the UARTx_LCTL register. The
FIFO configuration is determined and the receive trigger levels are set in the
UARTx_FCTL register. The status registers, UARTx_LSR and UARTx_MSR, are read to
ensure that none of the interrupt sources are active. The interrupts are enabled (except for
the transmit interrupt) and the application is ready to use the module for transmission/
reception.

Data Transfers

Transmit—To transmit data, the application enables the transmit interrupt. An interrupt is
immediately expected in response. The application reads the UARTx_IIR register and
determines whether the interrupt occurs due to either an empty UARTx_THR register or a

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completed transmission. When the application makes this determination, it writes the
transmit data bytes to the UARTx_THR register. The number of bytes that the application
writes depends on whether or not the FIFO is enabled. If the FIFO is enabled, the applica-
tion writes 16 bytes at a time. If not, the application writes one byte at a time. As a result
of the first Write, the interrupt is deactivated. The CPU then waits for the next interrupt.
When the interrupt is raised by the UART module, the CPU repeats the same process until
it exhausts all of the data for transmission.
To control and check the modem status, the application sets up the modem by writing to
the UARTx_MCTL register and reading the UARTx_MCTL register before starting the
process described above.

In RS485 multidrop mode, the first byte of the message is the station address and the rest
of the message contains the data for that station. You must set the Even Parity Select (EPS
bit 4) and Parity Enable (PEN bit 3) in the UARTx_LCTL before sending the station
address. We recommend that in your UART initialization routine set up the
UARTx_LCTL register for your data transfer format and set the Parity Enable (PEN bit 3)
bit. Each time you want to send a new message you must perform these three steps:
1. Since the UART automatically clears the Even Parity Select (EPS bit 4) bit in the
UARTx_LCTL after a byte is sent, before starting a new message you have to wait for
the transmitter to go idle. The Transmit Empty (TEMT bit 6) of the UARTx_LSR will
be set. If you set the EPS bit of the UARTx_LCTL before the last byte of the previous
message is transmitted, the EPS bit will be cleared and the new station address will be
sent as data instead of being used as an address.
2. Set the Even Parity Select (EPS bit 4) bit in the UARTx_LCTL register being careful
not to alter the other bits in the register sets the address mark. Write station address to
the UARTx_THR. The UART will automatically clear the EPS bit after the station
address byte is transmitted.
3. Send the rest of the message. Write data to the UART Transmit Holding Register
UARTx_THR whenever the Transmit Holding Register Empty (THRE bit 5) in the
UARTx_LSR is set.
In multidrop mode, during receiving start address marks, you will see a receive line inter-
rupt (INSTS bits[3:1]) in the IIR register. Read the LSR and check for receive errors only
and ignore any parity errors. The parity is only used for address marks in this multidrop
mode.

Receive—The receiver is always enabled, and it continually checks for the start bit on the
RxD input signal. When an interrupt is raised by the UART module, the application reads
the UARTx_IIR register and determines the cause for the interrupt. If the cause is a line
status interrupt, the application reads the UARTx_LSR register, reads the data byte and
then discards the byte or take other appropriate action. If the interrupt is caused by a
receive-data-ready condition, the application alternately reads the UARTx_LSR and
UARTx_RBR registers and removes all of the received data bytes. It reads the

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UARTx_LSR register before reading the UARTx_RBR register to determine that there is
no error in the received data.
To control and check modem status, the application sets up the modem by writing to the
UARTx_MCTL register and reading the UARTx_MSR register before starting the process
described above.

Poll Mode Transfers—When interrupts are disabled, all data transfers are referred to as
poll mode transfers. In poll mode transfers, the application must continually poll the
UARTx_LSR register to transmit or receive data without enabling the interrupts. The
same holds true for the UARTx_MSR register. If the interrupts are not enabled, the data in
the UARTx_IIR register cannot be used to determine the cause of interrupt.

Baud Rate Generator

The Baud Rate Generator consists of a 16-bit downcounter, two registers, and associated
decoding logic. The initial value of the Baud Rate Generator is defined by the two BRG
Divisor Latch registers, {UARTx_BRG_H, UARTx_BRG_L}. At the rising edge of each
system clock, the BRG decrements until it reaches the value 0001h. On the next system
clock rising edge, the BRG reloads the initial value from {UARTx_BRG_H,
UARTx_BRG_L) and outputs a pulse to indicate the end-of-count.
Calculate the UART data rate with the following equation:

System Clock Frequency

UART Data Rate (bits/s) =
16 X UART Baud Rate Generator Divisor

Upon RESET, the 16-bit BRG divisor value resets to the smallest allowable value of
0002h. Therefore, the minimum BRG clock divisor ratio is 2. A software Write to either
the Low- or High-byte registers for the BRG Divisor Latch causes both the Low and High
bytes to load into the BRG counter, and causes the count to restart.
The divisor registers are accessed only if bit 7 of the UART Line Control register
(UARTx_LCTL) is set to 1. After reset, this bit is reset to 0.

Recommended Use of the Baud Rate Generator

The following is the normal sequence of operations that must occur after the eZ80F91 is
powered on to configure the BRG:
1. Assert and deassert RESET.
2. Set UARTx_LCTL[7] to 1 to enable access of the BRG divisor registers.
3. Program the UARTx_BRG_L and UARTx_BRG_H registers.
4. Clear UARTx_LCTL[7] to 0 to disable access of the BRG divisor registers.

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BRG Control Registers

UART Baud Rate Generator Register—Low and High Bytes
The registers hold the Low and High bytes of the 16-bit divisor count loaded by the CPU
for UART baud rate generation. The 16-bit clock divisor value is returned by
{UARTx_BRG_H, UARTx_BRG_L}, where x is either 0 or 1 to identify the two available
UART devices. Upon RESET, the 16-bit BRG divisor value resets to 0002h. The initial
16-bit divisor value must be between 0002h and FFFFh, because the values 0000h and
0001h are invalid and proper operation is not guaranteed at these two values. As a result,
the minimum BRG clock divisor ratio is 2.
A Write to either the Low- or High-byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter. The count is then restarted.
Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to 1 to
access this register. See Table 94 and Table 95 on page 183. For more information, see
UART Line Control Register on page 188.
Note: The UARTx_BRG_L registers share the same address space with the UARTx_RBR and
UARTx_THR registers. The UARTx_BRG_H registers share the same address space with
the UARTx_IER registers. Bit 7 of the associated UART Line Control register
(UARTx_LCTL) must be set to 1 to enable access to the BRG registers.

Table 94. UART Baud Rate Generator Register—Low Bytes (UART0_BRG_L = 00C0h,
UART1_BRG_L = 00D0h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 1 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R = Read only; R/W = Read/Write.

Bit
Position Value Description
These bits represent the Low byte of the 16-bit BRG divider value. The
[7:0]
00h–FFh complete BRG divisor value is returned by {UART_BRG_H,
UART_BRG_L
UART_BRG_L}.

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Table 95. UART Baud Rate Generator Register—High Bytes (UART0_BRG_H = 00C1h,
UART1_BRG_H = 00D1h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R = Read only; R/W = Read/Write.

Bit
Position Value Description
These bits represent the High byte of the 16-bit BRG divider value. The
[7:0]
00h–FFh complete BRG divisor value is returned by {UART_BRG_H,
UART_BRG_H
UART_BRG_L}.

UART Registers
After a system reset, all UART registers are set to their default values. Any Writes to unused
registers or register bits are ignored and reads return a value of 0. For compatibility with
future revisions, unused bits within a register must always be written with a value of 0.
Read/Write attributes, reset conditions, and bit descriptions of all of the UART registers are
provided in this section.

UART Transmit Holding Register

If less than eight bits are programmed for transmission, the lower bits of the byte written
to this register are selected for transmission. The Transmit FIFO is mapped at this address.
You can write up to 16 bytes for transmission at one time to this address if the FIFO is
enabled by the application. If the FIFO is disabled, this buffer is only one byte deep.
These registers share the same address space as the UARTx_RBR and UARTx_BRG_L
registers. See Table 96 on page 184.

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Table 96. UART Transmit Holding Registers (UART0_THR = 00C0h, UART1_THR = 00D0h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access W W W W W W W W
Note: W = Write Only.

Bit
Position Value Description
[7:0]
00h–FFh Transmit data byte.
TxD

UART Receive Buffer Register

The bits in this register reflect the data received. If less than eight bits are programmed
for reception, the lower bits of the byte reflect the bits received, whereas upper unused
bits are 0. The Receive FIFO is mapped at this address. If the FIFO is disabled, this buf-
fer is only one byte deep.
These registers share the same address space as the UARTx_THR and UARTx_BRG_L
registers. See Table 97.

Table 97. UART Receive Buffer Registers (UART0_RBR = 00C0h, UART1_RBR = 00 D0h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R R R R R R R R
Note: R = Read only.

Bit
Position Value Description
[7:0]
00h–FFh Receive data byte.
RxD

UART Interrupt Enable Register

The UARTx_IER register is used to enable and disable the UART interrupts. The
UARTx_IER registers share the same I/O addresses as the UARTx_BRG_H registers. See
Table 98 on page 185.

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Table 98. UART Interrupt Enable Registers (UART0_IER = 00C1h, UART1_IER = 00D1h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:5] 000 Reserved.
0 Transmission complete interrupt is disabled.
4
TCIE Transmission complete interrupt is generated when both the transmit hold
1
register and the transmit shift register are empty.

3 0 Modem interrupt on edge detect of status inputs is disabled.

MIIE 1 Modem interrupt on edge detect of status inputs is enabled.
0 Line status interrupt is disabled.
2
LSIE Line status interrupt is enabled for receive data errors: incorrect parity bit
1
received, framing error, overrun error, or break detection.
0 Transmit interrupt is disabled.
1
TIE Transmit interrupt is enabled. Interrupt is generated when the transmit
1
FIFO/buffer is empty indicating no more bytes available for transmission.
0 Receive interrupt is disabled.
0 Receive interrupt and receiver time-out interrupt are enabled. Interrupt is
RIE 1 generated if the FIFO/buffer contains data ready to be read or if the
receiver times out.

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UART Interrupt Identification Register

The Read Only UARTx_IIR register allows you to check whether the FIFO is enabled and
the status of interrupts. These registers share the same I/O addresses as the UARTx_FCTL
registers. See Table 99 and Table 100.

Table 99. UART Interrupt Identification Registers (UART0_IIR = 00C2h, UART1_IIR = 00D2h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 1

CPU Access R R R R R R R R
Note: R = Read only.

Bit
Position Value Description

[7] 0 FIFO is disabled.

FSTS 1 FIFO is enabled.
[6:4] 000 Reserved.
Interrupt Status Code.
The code indicated in these three bits is valid only if INTBIT is
1. If two internal interrupt sources are active and their
[3:1] 000–11
respective enable bits are High, only the higher priority
INSTS 0
interrupt is seen by the application. The lower-priority interrupt
code is indicated only after the higher-priority interrupt is
serviced. Table 100 lists the interrupt status codes.

0 0 There is an active interrupt source within the UART.

INTBIT 1 There is not an active interrupt source within the UART.

Table 100. UART Interrupt Status Codes

INSTS
Value Priority Interrupt Type
011 Highest Receiver Line Status
010 Second Receive Data Ready or Trigger Level
110 Third Character Time-out
101 Fourth Transmission Complete
001 Fifth Transmit Buffer Empty
000 Lowest Modem Status

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UART FIFO Control Register

This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable
the FIFO. The UARTx_FCTL registers share the same I/O addresses as the UARTx_IIR
registers. See Table 101.

Table 101. UART FIFO Control Registers (UART0_FCTL = 00C2h, UART1_FCTL = 00D2h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access W W W W W W W W
Note: W = Write Only.

Bit
Position Value Description
Receive FIFO trigger level set to 1. Receive data interrupt is
00 generated when there is 1 byte in the FIFO. Valid only if FIFO
is enabled.
Receive FIFO trigger level set to 4. Receive data interrupt is
01 generated when there are 4bytes in the FIFO. Valid only if
[7:6] FIFO is enabled.
TRIG Receive FIFO trigger level set to 8. Receive data interrupt is
10 generated when there are 8 bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 14. Receive data interrupt is
11 generated when there are 14 bytes in the FIFO. Valid only if
FIFO is enabled.
[5:3] 000b Reserved—must be 000b.
Transmit Disable. This register bit works differently than the
standard 16550 UART. This bit must be set to transmit data.
When it is reset the transmit FIFO logic is reset along with the
2 0
associated transmit logic to keep them in sync. This bit is now
CLRTxF persistent–it does not self clear and it must remain at 1 to
transmit data.
1 Transmit Enable.
Receive Disable. This register bit works differently than the
standard 16550 UART. This bit must be set to receive data.
When it is reset the receive FIFO logic is reset along with the
1 0
associated receive logic to keep them in sync and avoid the
CLRRxF previous version’s lookup problem. This bit is now persistent–it
does not self clear and it must remain at 1 to receive data.
1 Receive Enable.

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Bit
Position Value Description
0 FIFOs are not used.

0 Receive and transmit FIFOs are used–You must clear the

FIFOEN FIFO logic using bits 1 and 2. First enable the FIFOs by setting
1
bit 0 to 1 then enable the receiver and transmitter by setting
bits 1 and 2.

UART Line Control Register

This register is used to control the communication control parameters. See Table 102 and
Table 103 on page 189.

Table 102. UART Line Control Registers (UART0_LCTL = 00C3h, UART1_LCTL = 00D3h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
0 Access to the UART registers at I/O addresses C0h, C1h, D0h and D1h is enabled.
7
DLAB Access to the Baud Rate Generator registers at I/O addresses C0h, C1h, D0h and
1
D1h is enabled.
0 Do not send a BREAK signal.
Send Break.
UART sends continuous zeroes on the transmit output from the next bit boundary.
6 The transmit data in the transmit shift register is ignored. After forcing this bit High,
SB the TxD output is 0 only after the bit boundary is reached. Just before forcing TxD to
1
0, the transmit FIFO is cleared. Any new data written to the transmit FIFO during a
break must be written only after the THRE bit of UARTx_LSR register goes High.
This new data is transmitted after the UART recovers from the break. After the break
is removed, the UART recovers from the break for the next BRG edge.
0 Do not force a parity error.
5
FPE Force a parity error. When this bit and the parity enable bit (pen) are both 1, an
1
incorrect parity bit is transmitted with the data byte.

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Bit
Position Value Description
Even Parity Select.
Use odd parity for transmit and receive. The total number of 1 bits in the transmit
0 data plus parity bit is odd. Used as SPACE bit in Multidrop Mode. See Table 104 on
4 page 189 for parity select definitions. Note: Receive Parity is set to SPACE in
EPS multidrop mode.
Use even parity for transmit and receive. The total number of 1 bits in the transmit
1 data plus parity bit is even. Used as MARK bit in Multidrop Mode. See Table 104 on
page 189 for parity select definitions.
0 Parity bit transmit and receive is disabled.

3 Parity bit transmit and receive is enabled. For transmit, a parity bit is generated and
PEN transmitted with every data character. For receive, the parity is checked for every
1
incoming data character. In Multidrop Mode, receive parity is checked for space
parity.
[2:0] UART Character Parameter Selection.
000–111
CHAR See Table 103 on page 189 for a description of the values.

Table 103. UART Character Parameter Definition

CHAR[2:0] Character Length (Tx/Rx Data Bits) Stop Bits (Tx Stop Bits)
000 5 1
001 6 1
010 7 1
011 8 1
100 5 2
101 6 2
110 7 2
111 8 2

Table 104. Parity Select Definition for Multidrop Communications

Multidrop Mode Even Parity Select Parity Type

0 0 odd
0 1 even

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Table 104. Parity Select Definition for Multidrop Communications

(Continued)

Multidrop Mode Even Parity Select Parity Type

1 0 space
1 1* mark
Note: *In Multidrop Mode, EPS resets to 0 after the first character is sent.

UART Modem Control Register

This register is used to control and check the modem status. See Table 105.

Table 105. UART Modem Control Registers (UART0_MCTL = 00C4h, UART1_MCTL = 00D4h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R/W R/W R/W R/W R/W R/W R/W

Note: R = Read Only; R/W = Read/Write.

Bit
Position Value Description
7 0 Reserved.

6 0 TxD and RxD signals—Normal Polarity.

POLARITY 1 Invert Polarity of TxD and RxD signals.
0 Multidrop Mode disabled.
5
MDM Multidrop Mode enabled. See Table 104 on page 189 for parity select
1
definitions.
0 LOOP BACK mode is not enabled.
LOOP BACK mode is enabled.
The UART operates in internal LOOP BACK mode. The transmit data output
4 port is disconnected from the internal transmit data output and set to 1. The
LOOP 1 receive data input port is disconnected and internal receive data is connected to
internal transmit data. The modem status input ports are disconnected and the
four bits of the modem control register are connected as modem status inputs.
The two modem control output ports (OUT1&2) are set to their inactive state.
No function in normal operation.
3
0–1 In LOOP BACK mode, this bit is connected to the DCD bit in the UART Status
OUT2
Register.

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Bit
Position Value Description
No function in normal operation.
2
0–1 In LOOP BACK mode, this bit is connected to the RI bit in the UART Status
OUT1
Register.
Request to Send.
1
0–1 In normal operation, the RTS output port is the inverse of this bit. In LOOP
RTS
BACK mode, this bit is connected to the CTS bit in the UART Status Register.
Data Terminal Ready.
0
0–1 In normal operation, the DTR output port is the inverse of this bit. In LOOP
DTR
BACK mode, this bit is connected to the DSR bit in the UART Status Register.

UART Line Status Register

This register is used to show the status of UART interrupts and registers. See Table 106.

Table 106. UART Line Status Registers (UART0_LSR = 00C5h, UART1_LSR = 00 D5h)

Bit 7 6 5 4 3 2 1 0
Reset 0 1 1 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read only.

Bit
Position Value Description
Always 0 when operating in with the FIFO disabled. With the
0 FIFO enabled, this bit is reset when the UARTx_LSR register is
7 read and there are no more bytes with error status in the FIFO.
ERR
Error detected in the FIFO. There is at least 1 parity, framing or
1
break indication error in the FIFO.
Transmit holding register/FIFO is not empty or transmit shift
0
register is not empty or transmitter is not idle.
6 Transmit holding register/FIFO and transmit shift register are
TEMT empty; and the transmitter is idle. This bit cannot be set to 1
1
during the BREAK condition. This bit only becomes 1 after the
BREAK command is removed.
0 Transmit holding register/FIFO is not empty.
5 Transmit holding register/FIFO. This bit cannot be set to 1
THRE 1 during the BREAK condition. This bit only becomes 1 after the
BREAK command is removed.

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Bit
Position Value Description
Receiver does not detect a BREAK condition. This bit is reset
0
to 0 when the UARTx_LSR register is read.
Receiver detects a BREAK condition on the receive input line.
This bit is 1 if the duration of BREAK condition on the receive
4 data is longer than one character transmission time, the time
BI depends on the programming of the UARTx_LSR register. In
1
case of FIFO only one null character is loaded into the receiver
FIFO with the framing error. The framing error is revealed to
the eZ80® whenever that particular data is read from the
receiver FIFO.
No framing error detected for character at the top of the FIFO.
0
This bit is reset to 0 when the UARTx_LSR register is read.
3
FE Framing error detected for the character at the top of the FIFO.
1 This bit is set to 1 when the stop bit following the data/parity bit
is logic 0.
The received character at the top of the FIFO does not contain
a parity error. In multidrop mode, this indicates that the
0
received character is a data byte. This bit is reset to 0 when the
2 UARTx_LSR register is read.
PE
The received character at the top of the FIFO contains a parity
1 error. In multidrop mode, this indicates that the received
character is an address byte.
The received character at the top of the FIFO does not contain
0 an overrun error. This bit is reset to 0 when the UARTx_LSR
register is read.
Overrun error is detected. If the FIFO is not enabled, this
1 indicates that the data in the receive buffer register was not
OE read before the next character was transferred into the receiver
1 buffer register. If the FIFO is enabled, this indicates the FIFO
was already full when an additional character was received by
the receiver shift register. The character in the receiver shift
register is not put into the receiver FIFO.
This bit is reset to 0 when the UARTx_RBR register is read or
0
all bytes are read from the receiver FIFO.

0 Data ready. If the FIFO is not enabled, this bit is set to 1 when
DR a complete incoming character is transferred into the receiver
1 buffer register from the receiver shift register. If the FIFO is
enabled, this bit is set to 1 when a character is received and
transferred to the receiver FIFO.

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UART Modem Status Register

This register is used to show the status of the UART signals. See Table 107.

Table 107. UART Modem Status Registers (UART0_MSR = 00C6h, UART1_MSR = 00 D6h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R R R R R R R R
Note: R = Read only.

Bit
Position Value Description
Data Carrier Detect
7 In NORMAL mode, this bit reflects the inverted state of the
0–1
DCD DCDx input pin. In LOOP BACK mode, this bit reflects the
value of the UARTx_MCTL[3] = out2.
Ring Indicator
6 In NORMAL mode, this bit reflects the inverted state of the RIx
0–1
RI input pin. In LOOP BACK mode, this bit reflects the value of the
UARTx_MCTL[2] = out1.
Data Set Ready
5 In NORMAL mode, this bit reflects the inverted state of the
0–1
DSR DSRx input pin. In LOOP BACK mode, this bit reflects the
value of the UARTx_MCTL[0] = DTR.
Clear to Send
4 In NORMAL mode, this bit reflects the inverted state of the
0–1
CTS CTSx input pin. In LOOP BACK mode, this bit reflects the value
of the UARTx_MCTL[1] = RTS.
Delta Status Change of DCD.
3
0–1 This bit is set to 1 whenever the DCDx pin changes state. This
DDCD
bit is reset to 0 when the UARTx_MSR register is read.
Trailing Edge Change on RI.
2 This bit is set to 1 whenever a falling edge is detected on the
0–1
TERI RIx pin. This bit is reset to 0 when the UARTx_MSR register is
read.
Delta Status Change of DSR.
1
0–1 This bit is set to 1 whenever the DSRx pin changes state. This
DDSR
bit is reset to 0 when the UARTx_MSR register is read.
Delta Status Change of CTS.
0
0–1 This bit is set to 1 whenever the CTSx pin changes state.
DCTS
This bit is reset to 0 when the UARTx_MSRs register is read.

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UART Scratch Pad Register

The UARTx_SPR register is used by the system as a general-purpose Read/Write register.
See Table 108.

Table 108. UART Scratch Pad Registers (UART0_SPR = 00C7h, UART1_SPR = 00D7h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
UART scratch pad register is available for use as a general-
[7:0]
00h–FFh purpose Read/Write register. In multi-drop 9 bit mode, this
SPR
register is used to store the address value.

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Infrared Encoder/Decoder
The eZ80F91 device contains a UART to an infrared encoder/decoder (endec). The endec
is integrated with the on-chip UART0 to allow easy communication between the CPU and
IrDA Physical Layer Specification Version 1.4-compatible infrared transceivers, as dis-
played in Figure 37. Infrared communication provides secure, reliable, high-speed, low-
cost, point-to-point communication between PCs, PDAs, mobile telephones, printers, and
other infrared-enabled devices.

eZ80F91

System Infrared
Clock Transceiver

RxD IR_RxD
RxD
TxD IR_TxD
Infrared TxD
UART0
Baud Rate Encoder/Decoder
Clock

Interrupt I/O Data I/O Data

Signal Address Address

¤
To eZ80 CPU

Figure 37. Infrared System Block Diagram

Functional Description
When the endec is enabled, the transmit data from the on-chip UART is encoded as digital
signals in accordance with the IrDA standard and output to the infrared transceiver. Like-
wise, data received from the infrared transceiver is decoded by the endec and passed to the
UART. Communication is half-duplex, meaning that simultaneous data transmission and
reception is not allowed.
The baud rate is set by the UART Baud Rate Generator (BRG), which supports IrDA stan-
dard baud rates from 9600 bps to 115.2 kbps. Higher baud rates are possible, but do not meet

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IrDA specifications. The UART must be enabled to use the endec. For more information on
the UART and its BRG, see Universal Asynchronous Receiver/Transmitter on page 175.

Transmit
The data to be transmitted via the IR transceiver is the data sent to UART0. The UART
transmit signal, TxD, and Baud Rate Clock are used by the endec to generate the
modulation signal, IR_TxD, that drives the infrared transceiver. Each UART bit is 16
clocks wide. If the data to be transmitted is a logical 1 (High), the IR_TxD signal remains
Low (0) for the full 16-clock period. If the data to be transmitted is a logical 0, a 3-clock
High (1) pulse is output following a 7-clock Low (0) period. Following the 3-clock High
pulse, a 6-clock Low pulse completes the full 16-clock data period. Data transmission is
displayed in Figure 38. During data transmission, the IR receive function must be disabled
by clearing the IR_RxEN bit in the IR_CTL reg to 0 to prevent transmitter-to-receiver
crosstalk.

16-clock
period

Baud Rate
Clock

UART_TxD Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
3-clock
pulse

IR_TxD

7-clock
delay

Figure 38. Infrared Data Transmission

Receive
Data received from the IR transceiver via the IR_RxD signal is decoded by the endec and
passed to the UART. The IR_RxEN bit in the IR_CTL register must be set to enable the
receiver decoder. The IrDA serial infrared (SIR) data format uses half duplex communica-
tion. Therefore, the UART must not be allowed to transmit while the receiver decoder is
enabled. The UART Baud Rate Clock is used by the endec to generate the demodulated
signal, RxD, that drives the UART. Each UART bit is 16 clocks wide. If the data to be
received is a logical 1 (High), the IR_RxD signal remains High (1) for the full 16-clock

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period. If the data to be received is a logical 0, a delayed Low (0) pulse is output on RxD.
Data transmission is displayed in Figure 39.

16-clock
period

Baud Rate
Clock

Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
IR_RxD

UART_RxD

16-clock 16-clock 16-clock 16-clock

8-clock period period period period
delay

Figure 39. Infrared Data Reception

The IrDA endec is designed to ignore pulses on IR_RxD which do not comply with IrDA
pulse width specifications. Input pulses wider than five baud clocks (that is, 5/16 of a bit
period) are always ignored, as this would be a violation of the maximum pulse width spec-
ified for any standard baud rate up to 115.2 kbps. The check for minimum pulse widths is
optional, since using a slow system clock frequency limits the ability to accurately mea-
sure narrow pulse widths near the IrDA specification minimum of 1.41 us for the
2.4–115.2 kbps rate range.
To enable checks of minimum input pulse width on IR_RxD, a non-zero value must be
programmed into the MIN_PULSE field of IR_CTL (bits [7:4]). This field forms the
most-significant four bits of the 6-bit down-counter used to determine if an input pulse
will be ignored because it is too narrow. The lower two counter bits are hard-coded to load
with 0x3, resulting in a total down-count equal to ((MIN_PULSE* 4) + 3). To be accepted,
input pulses must have a width greater than or equal to the down-count value times the
system clock period.
The following equation is used to determine an appropriate setting for MIN_PULSE:
MIN_PULSE = INT( ((Fsys*Wmin) - 3) / 4 )
Where,
Fsys is the frequency of the system clock, and,
Wmin is the minimum width of recognized input pulses.

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If this equation results in a value less than one, MIN_PULSE must be set to 0x0h which
enables edge detection and ensures that valid pulses wider than Wmin are accepted. The
field's maximum setting of 0xFh supports a Wmin of 1.25 us when Fsys is 50 MHz.

Jitter
Due to the inherent sampling of the received IR_RxD signal by the Bit Rate Clock, some
jitter is expected on the first bit in any sequence of data. However, all subsequent bits in
the received data stream are a fixed 16 clock periods wide.

Infrared Encoder/Decoder Signal Pins

The endec signal pins, IR_TxD and IR_RxD, are multiplexed with General-Purpose
Input/Output (GPIO) pins. These GPIO pins must be configured for alternate function
operation for the endec to operate.
The remaining six UART0 pins, CTS0, DCD0, DSR0, DTR0, RTS, and RI0, are not
required for use with the endec. The UART0 modem status interrupt must be disabled to
prevent unwanted interrupts from these pins. The GPIO pins corresponding to these six
unused UART0 pins are used for inputs, outputs, or interrupt sources. Recommended
GPIO Port D control register settings are listed in Table 109. See General-Purpose Input/
Output on page 49 for additional information on setting the GPIO Port modes.

Table 109. GPIO Mode Selection when using the IrDA Encoder/Decoder

GPIO Port D Allowable GPIO

Bits Port Mode Allowable Port Mode Functions
PD0 7 Alternate Function
PD1 7 Alternate Function
PD2–PD7 Any other than GPIO Mode 7 Output, Input, Open-Drain, Open-Source, Level-
(1, 2, 3, 4, 5, 6, 8, or 9) sensitive Interrupt Input, or Edge-Triggered Interrupt
Input

Loopback Testing
Both internal and external loopback testing is accomplished with the endec on the eZ80F91
device. Internal loopback testing is enabled by setting the LOOP_BACK bit to 1. During
internal loopback, the IR_TxD output signal is inverted and connected on-chip to the
IR_RxD input. External loopback testing of the off-chip IrDA transceiver is accomplished
by transmitting data from the UART while the receiver is enabled (IR_RxEN set to 1).

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Infrared Encoder/Decoder Register

After a RESET, the Infrared Encoder/Decoder Register is set to its default value. Any
Writes to unused register bits are ignored and reads return a value of 0. The IR_CTL regis-
ter is listed in Table 110.

Table 110. Infrared Encoder/Decoder Control Registers (IR_CTL = 00BFh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R R/W R/W R/W

Note: R = Read only; R/W = Read/Write.

Bit
Position Value Description
[7:4] 0000 Minimum receive pulse width control. When this field is equal to
MIN_PULSE 0x0, the IrDA decoder uses edge detection to accept arbitrarily
narrow (that is, short) input pulses.
1h-Fh When not equal to 0x0, this field forms the most-significant four
bits of the 6-bit down-counter used to determine if an input
pulse will be ignored because it is too narrow. The lower two
counter bits are hard-coded to load with 0x3, resulting in a total
down-count equal to ((IR_CTL[4:0]MIN_PULSE * 4) + 3). To be
accepted, input pulses must have a width greater than or equal
to the down-count value times the system clock period.
3 0 Reserved.
2 0 Internal LOOP BACK mode is disabled.
LOOP_BACK
1 Internal LOOP BACK mode is enabled.
IR_TxD output is inverted and connected to IR_RxD input for
internal loop back testing.
1 0 IR_RxD data is ignored.
IR_RxEN
1 IR_RxD data is passed to UART0 RxD.
0 0 Endec is disabled.
IR_EN
1 Endec is enabled.

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Serial Peripheral Interface

The Serial Peripheral Interface (SPI) is a synchronous interface allowing several SPI-type
devices to be interconnected. The SPI is a full-duplex, synchronous, character-oriented
communication channel that employs a four-wire interface. The SPI block consists of a
transmitter, receiver, baud rate generator, and control unit. During an SPI transfer, data is
sent and received simultaneously by both the master and the slave SPI devices.
In a serial peripheral interface, separate signals are required for data and clock. The SPI is
configured either as a master or as a slave. The connection of two SPI devices (one master
and one slave) and the direction of data transfer is displayed in Figure 40 and Figure 41.

MASTER
SS

DATAIN MISO Bit 0 Bit 7 MOSI DATAOUT

8-Bit Shift Register SCK CLKOUT

Baud Rate
Generator

Figure 40. SPI Master Device

SLAVE
ENABLE SS

DATAIN MOSI Bit 0 Bit 7 MISO DATAOUT

CLKIN 8-Bit Shift Register

SCK

Figure 41. SPI Slave Device

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SPI Signals
The four basic SPI signals are:
• MISO (Master In, Slave Out)
• MOSI (Master Out, Slave In)
• SCK (SPI Serial Clock)
• SS (Slave Select)
These SPI signals are discussed in the following paragraphs. Each signal is described in
both MASTER and SLAVE modes.

Master In, Slave Out

The Master In, Slave Out (MISO) pin is configured as an input in a master device and as
an output in a slave device. It is one of the two lines that transfer serial data, with the most-
significant bit (msb) sent first. The MISO pin of a slave device is placed in a high-imped-
ance state if the slave is not selected. When the SPI is not enabled, this signal is in a high-
impedance state.

Master Out, Slave In

The Master Out, Slave In (MOSI) pin is configured as an output in a master device and as
an input in a slave device. It is one of the two lines that transfer serial data, with the msb
sent first. When the SPI is not enabled, this signal is in a high-impedance state.

Slave Select
The active Low Slave Select (SS) input signal is used to select the SPI as a slave device. It
must be Low prior to all data communication and must stay Low for the duration of the
data transfer.
The SS input signal must be High for the SPI to operate as a master device. If the SS signal
goes Low in Master mode, a Mode Fault error flag (MODF) is set in the SPI_SR register.
For more information, see SPI Status Register on page 209.
When the clock phase (CPHA) is set to 0, the shift clock is the logical OR of SS with
SCK. In this clock phase mode, SS must go High between successive characters in an
SPI message. When CPHA is set to 1, SS remains Low for several SPI characters. In
cases where there is only one SPI slave, its SS line could be tied Low as long as CPHA
is set to 1. For more information on CPHA, see SPI Control Register on page 208.

Serial Clock
The Serial Clock (SCK) is used to synchronize data movement both in and out of the
device via its MOSI and MISO pins. The master and slave are each capable of exchanging
a byte of data during a sequence of eight clock cycles. Because SCK is generated by the
master, the SCK pin becomes an input on a slave device. The SPI contains an internal

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divide-by-two clock divider. In MASTER mode, the SPI serial clock is one-half the fre-
quency of the clock signal created by the SPI’s Baud Rate Generator.
As displayed in Figure 42 and Table 111, four possible timing relations are chosen by
using the clock polarity (CPOL) and clock phase CPHA control bits in the SPI Control
register. See SPI Control Register on page 208. Both the master and slave must operate
with the identical timing, CPOL, and CPHA. The master device always places data on the
MOSI line a half-cycle before the clock edge (SCK signal), for the slave device to latch
the data.

Number of Cycles on the SCK Signal

1 2 3 4 5 6 7 8

SCK (CPOL bit = 0)

SCK (CPOL bit = 1)

Sample Input MSB 6 5 4 3 2 1 LSB

(CPHA bit = 0) Data Out

Sample Input MSB 6 5 4 3 2 1 LSB

(CPHA bit = 1) Data Out

ENABLE (To Slave)

Figure 42. SPI Timing

Table 111. SPI Clock Phase and Clock Polarity Operation

SS High
SCK SCK SCK
Transmit Receive Idle Between
CPHA CPOL Edge Edge State Characters?
0 0 Falling Rising Low Yes
0 1 Rising Falling High Yes
1 0 Rising Falling Low No
1 1 Falling Rising High No

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SPI Functional Description

When a master transmits to a slave device via the MOSI signal, the slave device responds
by sending data to the master via the master's MISO signal. The result is a full-duplex
transmission, with both data out and data in synchronized with the same clock signal. The
byte transmitted is replaced by the byte received, eliminating the need for separate trans-
mit-empty and receive-full status bits. A single status bit, SPIF, is used to signify that the
I/O operation is complete. See SPI Status Register on page 209.
The SPI is double-buffered during reads, but not during Writes. If a Write is performed
during data transfer, the transfer occurs uninterrupted, and the Write is unsuccessful. This
condition causes the write collision (WCOL) status bit in the SPI_SR register to be set.
After a data byte is shifted, the SPI flag of the SPI_SR register is set to 1.
In SPI MASTER mode, the SCK pin functions as an output. It idles High or Low depend-
ing on the CPOL bit in the SPI_CTL register until data is written to the shift register. Data
transfer is initiated by writing to the transmit shift register, SPI_TSR. Eight clocks are then
generated to shift the eight bits of transmit data out via the MOSI pin while shifting in
eight bits of data via the MISO pin. After transfer, the SCK signal becomes idle.
In SPI SLAVE mode, the start logic receives a logic Low from the SS pin and a clock
input at the SCK pin; as a result, the slave is synchronized to the master. Data from the
master is received serially from the slave MOSI signal and is loaded into the 8-bit shift
register. After the 8-bit shift register is loaded, its data is parallel-transferred to the Read
buffer. During a Write cycle, data is written into the shift register. Next, the slave waits for
the SPI master to initiate a data transfer, supply a clock signal, and shift the data out on the
slave's MISO signal.
If the CPHA bit in the SPI_CTL register is 0, a transfer begins when the SS pin signal goes
Low. The transfer ends when SS goes High after eight clock cycles on SCK. When the
CPHA bit is set to 1, a transfer begins the first time SCK becomes active while SS is Low.
The transfer ends when the SPI flag is set to 1.

SPI Flags
Mode Fault
The Mode Fault flag (MODF) indicates that there is a multimaster conflict in the system
control. The MODF bit is normally cleared to 0 and is only set to 1 when the master
device’s SS pin is pulled Low. When a mode fault is detected, the following sequence
occurs:
1. The MODF flag (SPI_SR[4]) is set to 1.
2. The SPI device is disabled by clearing the SPI_EN bit (SPI_CTL[5]) to 0.
3. The MASTER_EN bit (SPI_CTL[4]) is cleared to 0, forcing the device into SLAVE
mode.

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4. If the SPI interrupt is enabled by setting IRQ_EN (SPI_CTL[7]) High, an SPI inter-
rupt is generated.
Clearing the Mode Fault flag is performed by reading the SPI Status register. The other
SPI control bits (SPI_EN and MASTER_EN) must be restored to their original states by
user software after the Mode Fault Flag is cleared to 0.

Write Collision
The write collision flag, WCOL (SPI_SR[5]), is set to 1 when an attempt is made to write
to the SPI Transmit Shift register (SPI_TSR) while data transfer occurs. Clearing the
WCOL bit is performed by reading SPI_SR with the WCOL bit set to 1.

SPI Baud Rate Generator

The SPI’s Baud Rate Generator (BRG) creates a lower frequency clock from the high-fre-
quency system clock. The BRG output is used as the clock source by the SPI.

Baud Rate Generator Functional Description

The SPI’s BRG consists of a 16-bit downcounter, two 8-bit registers, and associated
decoding logic. The BRG’s initial value is defined by the two BRG Divisor Latch registers
{SPI_BRG_H, SPI_BRG_L}. At the rising edge of each system clock, the BRG decre-
ments until it reaches the value 0001h. On the next system clock rising edge, the BRG
reloads the initial value from {SPI_BRG_H, SPI_BRG_L) and outputs a pulse to indicate
the end of the count.
The SPI Data Rate is calculated using the following equation:

System Clock Frequency

SPI Data Rate (bits/s) =
2 X SPI Baud Rate Generator Divisor

Upon RESET, the 16-bit BRG divisor value resets to 0002h. When the SPI is operating as
a Master, the BRG divisor value must be set to a value of 0003h or greater. When the SPI
is operating as a Slave, the BRG divisor value must be set to a value of 0004h or greater.
A software Write to either the Low- or High-byte registers for the BRG Divisor Latch
causes both the Low and High bytes to load into the BRG counter, and causes the count to
restart.

Data Transfer Procedure with SPI Configured as a Master

The following list describes the procedure for transferring data from a master SPI device
to a slave SPI device.

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1. Load the SPI BRG Registers, SPI_BRG_H and SPI_BRG_L. The external device
must deassert the SS pin if currently asserted.
2. Load the SPI Control Register, SPI_CTL.
3. Assert the ENABLE pin of the slave device using a GPIO pin.
4. Load the SPI Transmit Shift Register, SPI_TSR.
5. When the SPI data transfer is complete, deassert the ENABLE pin of the slave device.

Data Transfer Procedure with SPI Configured as a Slave

The following list describes the procedure for transferring data from a slave SPI device to
a master SPI device.
1. Load the SPI BRG Registers, SPI_BRG_H and SPI_BRG_L.
2. Load the SPI Transmit Shift Register, SPI_TSR. This load cannot occur while the SPI
slave is currently receiving data.
3. Wait for the external SPI Master device to initiate the data transfer by asserting SS.

SPI Registers
There are six registers in the Serial Peripheral Interface that provide control, status, and
data storage functions. The SPI registers are described in the following paragraphs.

SPI Baud Rate Generator Registers—Low Byte and High Byte

These registers hold the Low and High bytes of the 16-bit divisor count loaded by the CPU
for baud rate generation. The 16-bit clock divisor value is returned by {SPI_BRG_H,
SPI_BRG_L}. Upon RESET, the 16-bit BRG divisor value resets to 0002h. When config-
ured as a Master, the 16-bit divisor value must be between 0003h and FFFFh, inclusive.
When configured as a Slave, the 16-bit divisor value must be between 0004h and FFFFh,
inclusive.
A Write to either the Low- or High-byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter and a restart of the count. See Table 112 on page
207 and Table 113 on page 207.

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Table 112. SPI Baud Rate Generator Register—Low Byte (SPI_BRG_L = 00B8h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 1 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
These bits represent the Low byte of the 16-bit BRG divider
[7:0] 00h–FF
value. The complete BRG divisor value is returned by
SPI_BRG_L h
{SPI_BRG_H, SPI_BRG_L}.

Table 113. SPI Baud Rate Generator Register—High Byte (SPI_BRG_H = 00B9h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
These bits represent the High byte of the 16-bit BRG divider
[7:0]
00h–FFh value. The complete BRG divisor value is returned by
SPI_BRG_H
{SPI_BRG_H, SPI_BRG_L}.

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SPI Control Register

This register is used to control and setup the serial peripheral interface. The SPI must be
disabled prior to making any changes to CPHA or CPOL. See Table 114.

Table 114. SPI Control Register (SPI_CTL = 00BAh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 1 0 0

CPU Access R/W R R/W R/W R/W R/W R R

Note: R = Read Only; R/W = Read/Write.

Bit
Position Value Description

7 0 SPI system interrupt is disabled.

IRQ_EN 1 SPI system interrupt is enabled.
6 0 Reserved.

5 0 SPI is disabled.
SPI_EN 1 SPI is enabled.

4 0 When enabled, the SPI operates as a slave.

MASTER_EN 1 When enabled, the SPI operates as a master.

3 0 Master SCK pin idles in a Low (0) state.

CPOL 1 Master SCK pin idles in a High (1) state.

2 0 SS must go High after transfer of every byte of data.

CPHA 1 SS remains Low to transfer any number of data bytes.
[1:0] 00 Reserved.

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SPI Status Register

The SPI Status Read Only register returns the status of data transmitted using the serial
peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to a logical 0.
See Table 115.

Table 115. SPI Status Register (SPI_SR = 00BBh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
0 SPI data transfer is not finished.
7 SPI data transfer is finished. If enabled, an interrupt is
SPIF 1 generated. This bit flag is cleared to 0 by a Read of the
SPI_SR register.
0 An SPI write collision is not detected.
6
WCOL An SPI write collision is detected. This bit Flag is cleared to 0
1
by a Read of the SPI_SR registers.
5 0 Reserved.
0 A mode fault (multimaster conflict) is not detected.
4
MODF A mode fault (multimaster conflict) is detected. This bit Flag is
1
cleared to 0 by a Read of the SPI_SR register.
[3:0] 0000 Reserved.

SPI Transmit Shift Register

The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit data over
SPI serial bus to the slave device. A Write to the SPI_TSR register places data directly into
the shift register for transmission. A Write to this register within an SPI device configured
as a master initiates transmission of the byte of the data loaded into the register. At the
completion of transmitting a byte of data, the SPI Flag (SPI_SR[7]) is set to 1 in both the
master and slave devices.
The SPI Transmit Shift Write Only register shares the same address space as the SPI
Receive Buffer Read Only register. See Table 116 on page 210.

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Table 116. SPI Transmit Shift Register (SPI_TSR = 00BCh)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X
CPU Access W W W W W W W W
Note: W = Write Only.

Bit
Position Value Description
[7:0]
00h–FFh SPI transmit data.
TX_DATA

SPI Receive Buffer Register

The SPI Receive Buffer register (SPI_RBR) is used by the SPI slave to receive data from
the serial bus. The SPIF bit must be cleared prior to a second transfer of data from the shift
register; otherwise, an overrun condition exists. In the event of an overrun, the byte that
causes the overrun is lost.
The SPI Receive Buffer Read Only register shares the same address space as the SPI
Transmit Shift Write Only register. See Table 117.

Table 117. SPI Receive Buffer Register (SPI_RBR = 00BCh)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0]
00h–FFh SPI received data.
RX_DATA

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I2C Serial I/O Interface

I2C General Characteristics
The Inter-Integrated Circuit (I2C) serial I/O bus is a two-wire communication interface
that operates in four modes:
• MASTER TRANSMIT
• MASTER RECEIVE
• SLAVE TRANSMIT
• SLAVE RECEIVE
The I2C interface consists of a Serial Clock (SCL) and Serial Data (SDA). Both SCL and
SDA are bidirectional lines connected to a positive supply voltage via an external pull-up
resistor. When the bus is free, both lines are High. The output stages of devices connected
to the bus must be configured as open-drain outputs. Data on the I2C bus are transferred at
a rate of up to 100 kbps in STANDARD mode, or up to 400 kbps in FAST mode. One
clock pulse is generated for each data bit transferred.

Clocking Overview
If another device on the I2C bus drives the clock line when the I2C is in MASTER mode,
the I2C synchronizes its clock to the I2C bus clock. The High period of the clock is
determined by the device that generates the shortest High clock period. The Low period of
the clock is determined by the device that generates the longest Low clock period.
The Low period of the clock is stretched by a slave to slow down the bus master. The Low
period is also stretched for handshaking purposes. This result is accomplished after each
bit transfer or each byte transfer. The I2C stretches the clock after each byte transfer until
the IFLG bit in the I2C_CTL register is cleared to 0.

Bus Arbitration Overview

In MASTER mode, the I2C checks that each transmitted logic 1 appears on the I2C bus as
a logic 1. If another device on the bus overrules and pulls the SDA signal Low, arbitration
is lost. If arbitration is lost during the transmission of a data byte or a Not Acknowledge
(NACK) bit, the I2C returns to an idle state. If arbitration is lost during the transmission of
an address, the I2C switches to SLAVE mode so that it recognizes its own slave address or
the general call address.

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Data Validity
The data on the SDA line must be stable during the High period of the clock. The High or
Low state of the data line changes only when the clock signal on the SCL line is Low, as
displayed in Figure 43.

SDA Signal

SCL Signal

Data Line Change of

Stable Data Allowed
Data Valid

Figure 43. I2C Clock and Data Relationship

START and STOP Conditions

Within the I2C bus protocol, unique situations arise which are defined as START and
STOP conditions. Figure 44 displays a High-to-Low transition on the SDA line while SCL
is High, indicating a START condition. A Low-to-High transition on the SDA line while
SCL is High defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to
be busy after a START condition. The bus is considered to be free for a defined time after
a STOP condition.

SDA Signal

SCL Signal
S P

START Condition STOP Condition

Figure 44. START and STOP Conditions In I2C Protocol

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Transferring Data
Byte Format
Every character transferred on the SDA line must be a single 8-bit byte. The number of
bytes that is transmitted per transfer is unrestricted. Each byte must be followed by an
Acknowledge (ACK). Data is transferred with the most-significant bit (msb) first.
Figure 45 displays a receiver that holds the SCL line Low to force the transmitter into a
Wait state. Data transfer then continues when the receiver is ready for another byte of data
and releases SCL.

SDA Signal
MSB Acknowledge from Acknowledge from
Receiver Receiver

SCL Signal 1 2 8 9 1 9
S P
ACK
START Condition STOP Condition
Clock Line Held Low By Receiver
2
Figure 45. I C Frame Structure

Acknowledge
Data transfer with an ACK function is obligatory. The ACK-related clock pulse is gen-
erated by the master. The transmitter releases the SDA line (High) during the ACK
clock pulse. The receiver must pull down the SDA line during the ACK clock pulse so
that it remains stable (Low) during the High period of this clock pulse. See Figure 46
on page 214.
A receiver that is addressed is obliged to generate an ACK after each byte is received.
When a slave receiver does not acknowledge the slave address (for example, unable to
receive because it is performing some real-time function), the data line must be left High
by the slave. The master then generates a STOP condition to abort the transfer.
If a slave receiver acknowledges the slave address, but cannot receive any more data
bytes, the master must abort the transfer. The abort is indicated by the slave generating the
Not Acknowledge (NACK) on the first byte to follow. The slave leaves the data line High
and the master generates the STOP condition.
If a master receiver is involved in a transfer, it must signal the end of the data stream to the
slave transmitter by not generating an ACK on the final byte that is clocked out of the
slave. The slave transmitter must release the data line to allow the master to generate a
STOP or a repeated START condition.

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Data Output
by Transmitter
MSB

Data Output
1
by Receiver S
SCL Signal
1 2 8 9
from Master
START Condition
Clock Pulse for Acknowledge

Figure 46. I2C Acknowledge

Clock Synchronization
All masters generate their own clocks on the SCL line to transfer messages on the I2C bus.
Data is only valid during the High period of each clock.
Clock synchronization is performed using the wired AND connection of the I2C interfaces
to the SCL line, meaning that a High-to-Low transition on the SCL line causes the relevant
devices to start counting from their Low period. When a device clock goes Low, it holds
the SCL line in that state until the clock High state is reached. See Figure 47 on page 215.
The Low-to-High transition of this clock, however, cannot change the state of the SCL
line if another clock is still within its Low period. The SCL line is held Low by the device
with the longest Low period. Devices with shorter Low periods enter a High wait state
during this time.
When all devices count off the Low period, the clock line is released and goes High. There
is no difference between the device clocks and the state of the SCL line; all of the devices
start counting the High periods. The first device to complete its High period again pulls
the SCL line Low. In this way, a synchronized SCL clock is generated with its Low period
determined by the device with the longest clock Low period, and its High period
determined by the device with the shortest clock High period.

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Wait Start Counting

State High Period

CLK1 Signal

Counter
Reset

CLK2 Signal

SCL Signal

Figure 47. Clock Synchronization In I2C Protocol

Arbitration
Any master initiates a transfer if the bus is free. As a result, multiple masters each gener-
ates a START condition if the bus is free within a minimum period. If multiple masters
generate a START condition, a START is defined for the bus. However, arbitration defines
which MASTER controls the bus. Arbitration takes place on the SDA line. As mentioned,
START conditions are initiated only while the SCL line is held High. If during this period,
a master (M1) initiates a High-to-Low transition—that is, a START condition—while a
second master (M2) transmits a Low signal on the line, then the first master, M1, cannot
take control of the bus. As a result, the data output stage for M1 is disabled.
Arbitration continues for many bits. Its first stage is comparison of the address bits. If the
masters are each trying to address the same device, arbitration continues with a compari-
son of the data. Because address and data information on the I2C bus is used for arbitra-
tion, no information is lost during this process. A master that loses the arbitration
generates clock pulses until the end of the byte in which it loses the arbitration.
If a master also incorporates a slave function and it loses arbitration during the addressing
stage, it is possible that the winning master is trying to address it. The losing master must
switch over immediately to its slave receiver mode. Figure 47 displays the arbitration pro-
cedure for two masters. Of course, more masters can be involved, depending on how many
masters are connected to the bus. The moment there is a difference between the internal
data level of the master generating DATA 1 and the actual level on the SDA line, its data
output is switched off, which means that a High output level is then connected to the bus.
As a result, the data transfer initiated by the winning master is not affected. Because con-
trol of the I2C bus is decided solely on the address and data sent by competing masters,
there is no central master, nor any order of priority on the bus.
Special attention must be paid if, during a serial transfer, the arbitration procedure is still
in progress at the moment when a repeated START condition or a STOP condition is trans-
mitted to the I2C bus. If it is possible for such a situation to occur, the masters involved

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must send this repeated START condition or STOP condition at the same position in the
format frame. In other words, arbitration is not allowed between:
• A repeated START condition and a data bit.
• A STOP condition and a data bit.
• A repeated START condition and a STOP condition.

Clock Synchronization for Handshake

The clock-synchronizing mechanism functions as a handshake, enabling receivers to cope
with fast data transfers, on either a byte or a bit level. The byte level allows a device to
receive a byte of data at a fast rate, but allows the device more time to store the received
byte or to prepare another byte for transmission. Slaves hold the SCL line Low after recep-
tion and acknowledge the byte, forcing the master into a Wait state until the slave is ready
for the next byte transfer in a handshake procedure.

Operating Modes
Master Transmit
In MASTER TRANSMIT mode, the I2C transmits a number of bytes to a slave receiver.
Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL register to 1.
The I2C then tests the I2C bus and transmits a START condition when the bus is free.
When a START condition is transmitted, the IFLG bit is 1 and the status code in the
I2C_SR register is 08h. Before this interrupt is serviced, the I2C_DR register must be
loaded with either a 7-bit slave address or the first part of a 10-bit slave address, with the
lsb cleared to 0 to specify TRANSMIT mode. The IFLG bit must now be cleared to 0 to
prompt the transfer to continue.
After the 7-bit slave address (or the first part of a 10-bit address) plus the Write bit are
transmitted, the IFLG is set again. A number of status codes are possible in the I2C_SR
register. See Table 118 on page 217.

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Table 118. I2C Master Transmit Status Codes

Code I2C State Microcontroller Response Next I2C Action

18h Addr+W transmitted For a 7-bit address: write byte to DATA, Transmit data byte,
ACK received1 clear IFLG receive ACK
Or set STA, clear IFLG Transmit repeated
START
Or set STP, clear IFLG Transmit STOP
Or set STA & STP, clear IFLG Transmit STOP then
START
For a 10-bit address: write extended Transmit extended
address byte to data, clear IFLG address byte
20h Addr+W transmitted, Same as code 18h Same as code 18h
ACK not received
38h Arbitration lost Clear IFLG Return to idle
Or set STA, clear IFLG Transmit START when
bus is free
68h Arbitration lost, Clear IFLG, AAK = 02 Receive data byte,
+W received, transmit NACK
ACK transmitted
Or clear IFLG, AAK = 1 Receive data byte,
transmit ACK
78h Arbitration lost, Same as code 68h Same as code 68h
General call address
received, ACK
transmitted
B0h Arbitration lost, Write byte to DATA, clear IFLG, clear AAK Transmit last byte,
SLA+R received, =0 receive ACK
ACK transmitted3
Or write byte to DATA, clear IFLG, set AAK Transmit data byte,
=1 receive ACK
Notes
1. W is defined as the Write bit; that is, the lsb is cleared to 0.
2. AAK is an I2C control bit that identifies which ACK signal to transmit.
3. R is defined as the Read bit; that is, the lsb is set to 1.

If 10-bit addressing is used, the status code is 18h or 20h after the first part of a 10-bit
address, plus the Write bit, are successfully transmitted.
After this interrupt is serviced and the second part of the 10-bit address is transmitted, the
I2C_SR register contains one of the codes listed in Table 119.

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Table 119. I2C 10-Bit Master Transmit Status Codes

Code I2C State Microcontroller Response Next I2C Action

38h Arbitration lost Clear IFLG Return to idle
Or set STA, clear IFLG Transmit START when bus free
68h Arbitration lost, Clear IFLG, clear AAK = 02 Receive data byte, transmit NACK
SLA+W received,
Or clear IFLG, set AAK = 1 Receive data byte, transmit ACK
ACK transmitted1
B0h Arbitration lost, Write byte to DATA, Transmit last byte,
SLA+R received, clear IFLG, clear AAK = 0 receive ACK
ACK transmitted3
Or write byte to DATA, Transmit data byte,
clear IFLG, set AAK = 1 receive ACK
D0h Second address byte Write byte to data, Transmit data byte,
+ W transmitted, clear IFLG receive ACK
ACK received
Or set STA, clear IFLG Transmit repeated START
Or set STP, clear IFLG Transmit STOP
Or set STA & STP, Transmit STOP then
clear IFLG START
D8h Second address byte Same as code D0h Same as code D0h
+ W transmitted,
ACK not received
Notes
1. W is defined as the Write bit; that is, the lsb is cleared to 0.
2. AAK is an I2C control bit that identifies which ACK signal to transmit.
3. R is defined as the Read bit; that is, the lsb is set to 1.

If a repeated START condition is transmitted, the status code is 10h instead of 08h. After
each data byte is transmitted, the IFLG is set to 1 and one of the status codes listed in
Table 120 is loaded into the I2C_SR register.

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Table 120. I2C Master Transmit Status Codes For Data Bytes

Code I2C State Microcontroller Response Next I2C Action

28h Data byte transmitted, Write byte to data, Transmit data byte,
ACK received clear IFLG receive ACK
Or set STA, clear IFLG Transmit repeated START
Or set STP, clear IFLG Transmit STOP
Or set STA & STP, Transmit START then STOP
clear IFLG
30h Data byte transmitted, Same as code 28h Same as code 28h
ACK not received
38h Arbitration lost Clear IFLG Return to idle
Or set STA, clear IFLG Transmit START when bus free

When all bytes are transmitted, the microcontroller must write a 1 to the STP bit in the
I2C_CTL register. The I2C then transmits a STOP condition, clears the STP bit and returns
to an idle state.

Master Receive
In MASTER RECEIVE mode, the I2C receives a number of bytes from a slave
transmitter.
After the START condition is transmitted, the IFLG bit is 1 and the status code 08h is
loaded into the I2C_SR register. The I2C_DR register must be loaded with the slave
address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a Read.
The IFLG bit must be cleared to 0 as a prompt for the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit are
transmitted, the IFLG bit is set and one of the status codes listed in Table 121 on page 220
is loaded into the I2C_SR register.

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Table 121. I2C Master Receive Status Codes

Code I2C State Microcontroller Response Next I2C Action

40h Addr + R transmitted, For a 7-bit address, Receive data byte,
ACK received clear IFLG, AAK = 01 transmit NACK
Or clear IFLG, AAK = 1 Receive data byte,
transmit ACK
For a 10-bit address Transmit extended address byte
Write extended address
byte to data, clear IFLG
48h Addr + R transmitted, For a 7-bit address: Transmit repeated START
ACK not received2 Set STA, clear IFLG
Or set STP, clear IFLG Transmit STOP
Or set STA & STP, Transmit STOP then START
clear IFLG
For a 10-bit address: Transmit extended address byte
Write extended address byte to data,
clear IFLG
38h Arbitration lost Clear IFLG Return to idle
Or set STA, clear IFLG Transmit START when bus is free
68h Arbitration lost, Clear IFLG, clear AAK = 0 Receive data byte,
SLA+W received, transmit NACK
ACK transmitted3
Or clear IFLG, set AAK = 1 Receive data byte,
transmit ACK
78h Arbitration lost, Same as code 68h Same as code 68h
General call addr
received, ACK
transmitted
B0h Arbitration lost, Write byte to DATA, Transmit last byte,
SLA+R received, clear IFLG, clear AAK = 0 receive ACK
ACK transmitted
Or write byte to DATA, Transmit data byte,
clear IFLG, set AAK = 1 receive ACK
Notes
1. AAK is an I2C control bit that identifies which ACK signal to transmit.
2. R is defined as the Read bit; that is, the lsb is set to 1.
3. W is defined as the Write bit; that is, the lsb is cleared to 0.

If 10-bit addressing is being used, the slave is first addressed using the full 10-bit address,
plus the Write bit. The master then issues a restart followed by the first part of the 10-bit

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address again, this time with the Read bit. The status code then becomes 40h or 48h. It is
the responsibility of the slave to remember that it had been selected prior to the restart.
If a repeated START condition is received, the status code is 10h instead of 08h.
After each data byte is received, the IFLG is set to 1 and one of the status codes listed in
Table 122 is loaded into the I2C_SR register.

Table 122. I2C Master Receive Status Codes For Data Bytes

Code I2C State Microcontroller Response Next I2C Action

50h Data byte received, Read data, clear IFLG, Receive data byte,
ACK transmitted clear AAK = 0* transmit NACK
Or read data, clear IFLG, Receive data byte,
set AAK = 1 transmit ACK
58h Data byte received, Read data, set STA, Transmit repeated
NACK transmitted clear IFLG START
Or read data, set STP, Transmit STOP
clear IFLG
Or read data, set Transmit STOP then
STA & STP, clear IFLG START
38h Arbitration lost in Same as master transmit Same as master
NACK bit transmit
Note: AAK is an I2C control bit that identifies which ACK signal to transmit.

When all bytes are received, a NACK must be sent, then the microcontroller must write 1
to the STP bit in the I2C_CTL register. The I2C then transmits a STOP condition, clears
the STP bit and returns to an idle state.

Slave Transmit
In SLAVE TRANSMIT mode, a number of bytes are transmitted to a master receiver.
The I2C enters SLAVE TRANSMIT mode when it receives its own slave address and a
Read bit after a START condition. The I2C then transmits an ACK bit (if the AAK bit is
set to 1); it then sets the IFLG bit in the I2C_CTL register. As a result, the I2C_SR register
contains the status code A8h.
Note: When I2C contains a 10-bit slave address (signified by the address range F0h–F7h in the
I2C_SAR register), it transmits an ACK when the first address byte is received after a
restart. An interrupt is generated and IFLG is set to 1; however, the status does not
change. No second address byte is sent by the master. It is up to the slave to remember it
had been selected prior to the restart.

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I2C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is lost dur-
ing the transmission of an address, and the slave address and Read bit are received. This
action is represented by the status code B0h in the I2C_SR register.
The data byte to be transmitted is loaded into the I2C_DR register and the IFLG bit is
cleared to 0. After the I2C transmits the byte and receives an ACK, the IFLG bit is set to 1
and the I2C_SR register contains B8h. When the final byte to be transmitted is loaded into
the I2C_DR register, the AAK bit is cleared when the IFLG is cleared to 0. After the final
byte is transmitted, the IFLG is set and the I2C_SR register contains C8h and the I2C
returns to an idle state. The AAK bit must be set to 1 before reentering SLAVE mode.
If no ACK is received after transmitting a byte, the IFLG is set and the I2C_SR register
contains C0h. The I2C then returns to an idle state. If a STOP condition is detected after an
ACK bit, the I2C returns to an idle state.

Slave Receive
In SLAVE RECEIVE mode, a number of data bytes are received from a master transmit-
ter. The I2C enters SLAVE RECEIVE mode when it receives its own slave address and a
Write bit (lsb = 0) after a START condition. The I2C transmits an ACK bit and sets the
IFLG bit in the I2C_CTL register and the I2C_SR register contains the status code 60h.
The I2C also enters SLAVE RECEIVE mode when it receives the general call address 00h
(if the GCE bit in the I2C_SAR register is set). The status code is then 70h.
Note: When the I2C contains a 10-bit slave address (signified by F0h–F7h in the I2C_SAR regis-
ter), it transmits an acknowledge after the first address byte is received but no interrupt is
generated. IFLG is not set and the status does not change. The I2C generates an interrupt
only after the second address byte is received. The I2C sets the IFLG bit and loads the sta-
tus code as described above.

I2C goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost during
the transmission of an address, and the slave address and Write bit (or the general call
address if the CGE bit in the I2C_SAR register is set to 1) are received. The status code in
the I2C_SR register is 68h if the slave address is received or 78h if the general call
address is received. The IFLG bit must be cleared to 0 to allow data transfer to continue.
If the AAK bit in the I2C_CTL register is set to 1 then an ACK bit (Low level on SDA) is
transmitted and the IFLG bit is set after each byte is received. The I2C_SR register con-
tains the two status codes 80h or 90h if SLAVE RECEIVE mode is entered with the gen-
eral call address. The received data byte are read from the I2C_DR register and the IFLG
bit must be cleared to allow the transfer to continue. If a STOP condition or a repeated
START condition is detected after the acknowledge bit, the IFLG bit is set and the I2C_SR
register contains status code A0h.
If the AAK bit is cleared to 0 during a transfer, the I2C transmits a NACK bit (High level
on SDA) after the next byte is received, and sets the IFLG bit to 1. The I2C_SR register

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contains the two status codes 88h or 98h if SLAVE RECEIVE mode is entered with the
general call address. The I2C returns to an idle state when the IFLG bit is cleared to 0.

I2C Registers
The section that follows describes each of the eZ80F91 MCU’s Inter-Integrated Circuit
(I2C) registers.

Addressing
The CPU interface provides access to seven 8-bit registers: four Read/Write registers, one
Read Only register and two Write Only registers, as listed in Table 123.

Table 123. I2C Register Descriptions

Register Description
I2C_SAR Slave address register
I2C_XSAR Extended slave address register
I2C_DR Data byte register
I2C_CTL Control register
I2C_SR Status register (Read Only)
I2C_CCR Clock Control register (Write Only)
I2C_SRR Software reset register (Write Only)

Resetting the I2C Registers

Hardware Reset—When the I2C is reset by a hardware reset of the eZ80F91 device, the
I2C_SAR, I2C_XSAR, I2C_DR, and I2C_CTL registers are cleared to 00h; while the
I2C_SR register is set to F8h.
Software Reset—Perform a software reset by writing any value to the I2C Software Reset
Register (I2C_SRR). A software reset clears the STP, STA, and IFLG bits of the I2C_CTL
register to 0 and sets the I2C back to an idle state.

I2C Slave Address Register

The I2C_SAR register provides the 7-bit address of the I2C when in SLAVE mode and
allows 10-bit addressing in conjunction with the I2C_XSAR register. I2C_SAR[7:1] =
SLA[6:0] is the 7-bit address of the I2C when in 7-bit SLAVE mode. When the I2C
receives this address after a START condition, it enters SLAVE mode. I2C_SAR[7] corre-
sponds to the first bit received from the I2C bus.
When the register receives an address starting with F7h to F0h (I2C_SAR[7:3] = 11110b),
the I2C recognizes that a 10-bit slave addressing mode is being selected. The I2C sends an
ACK after receiving the I2C_SAR byte (the device does not generate an interrupt at this

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point). After the next byte of the address (I2C_XSAR) is received, the I2C generates an
interrupt and enters SLAVE mode.Then I2C_SAR[2:1] are used as the upper 2 bits for the
10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See Table 124.

Table 124. I2C Slave Address Register (I2C_SAR = 00C8h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:1] 00h–7Fh 7-bit slave address or upper 2 bits, I2C_SAR[2:1], of
SLA address when operating in 10-bit mode.
0 0 I2C not enabled to recognize the General Call Address.
GCE
1 I2C enabled to recognize the General Call Address.

I2C Extended Slave Address Register

The I2C_XSAR register is used in conjunction with the I2C_SAR register to provide 10-
bit addressing of the I2C when in SLAVE mode. The I2C_SAR value forms the lower 8
bits of the 10-bit slave address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}.
When the register receives an address starting with F7h to F0h (I2C_SAR[7:3] = 11110b),
the I2C recognizes that a 10-bit slave addressing mode is being selected. The I2C sends an
ACK after receiving the I2C_XSAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I2C generates an
interrupt and enters SLAVE mode.Then I2C_SAR[2:1] are used as the upper 2 bits for the
10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See Table 125.

Table 125. I2C Extended Slave Address Register (I2C_XSAR = 00C9h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

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Bit
Position Value Description
[7:0] 00h–FFh Least-significant 8 bits of the 10-bit extended slave address
SLAX

I2C Data Register

This register contains the data byte/slave address to be transmitted or the data byte just
received. In TRANSMIT mode, the MSb of the byte is transmitted first. In RECEIVE
mode, the first bit received is placed in the MSb of the register. After each byte is transmit-
ted, the I2C_DR register contains the byte that is present on the bus in case a lost arbitra-
tion event occurs. See Table 126.

Table 126. I2C Data Register (I2C_DR = 00CAh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FFh I2C data byte
DATA

I2C Control Register

The I2C_CTL register is a control register that is used to control the interrupts and the
master slave relationships on the I2C bus.
When the Interrupt Enable bit (IEN) is set to 1, the interrupt line goes High when the IFLG
is set to 1. When IEN is cleared to 0, the interrupt line always remains Low.
When the Bus Enable bit (ENAB) is set to 0, the I2C bus inputs SCLx and SDAx are
ignored and the I2C module does not respond to any address on the bus. When ENAB is
set to 1, the I2C responds to calls to its slave address and to the general call address if the
GCE bit (I2C_SAR[0]) is set to 1.
When the Master Mode Start bit (STA) is set to 1, the I2C enters MASTER mode and
sends a START condition on the bus when the bus is free. If the STA bit is set to 1 when
the I2C module is already in MASTER mode and one or more bytes are transmitted, then a
repeated START condition is sent. If the STA bit is set to 1 when the I2C block is being
accessed in SLAVE mode, the I2C completes the data transfer in SLAVE mode and then
enters MASTER mode when the bus is released. The STA bit is automatically cleared after
a START condition is set. Writing 0 to the STA bit produces no effect.

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If the Master Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition is
transmitted on the I2C bus. If the STP bit is set to 1 in SLAVE mode, the I2C module oper-
ates as if a STOP condition is received, but no STOP condition is transmitted. If both STA
and STP bits are set, the I2C block first transmits the STOP condition (if in MASTER
mode), then transmits the START condition. The STP bit is cleared to 0 automatically.
Writing a 0 to this bit produces no effect.
The I2C Interrupt Flag (IFLG) is set to 1 automatically when any of 30 of the possible 31
I2C states is entered. The only state that does not set the IFLG bit is state F8h. If IFLG is
set to 1 and the IEN bit is also set, an interrupt is generated. When IFLG is set by the I2C,
the Low period of the I2C bus clock line is stretched and the data transfer is suspended.
When a 0 is written to IFLG, the interrupt is cleared and the I2C clock line is released.
When the I2C Acknowledge bit (AAK) is set to 1, an acknowledge is sent during the
acknowledge clock pulse on the I2C bus if:
• Either the whole of a 7-bit slave address or the first or second byte of a 10-bit slave ad-
dress is received.
• The general call address is received and the General Call Enable bit in I2C_SAR is set
to 1.
• A data byte is received while in MASTER or SLAVE modes.
When AAK is cleared to 0, a NACK is sent when a data byte is received in MASTER or
SLAVE mode. If AAK is cleared to 0 in SLAVE TRANSMIT mode, the byte in the
I2C_DR register is assumed to be the final byte. After this byte is transmitted, the I2C
block enters the C8h state, then returns to an idle state. The I2C module does not respond
to its slave address unless AAK is set to 1. See Table 127 on page 226.

Table 127. I2C Control Register (I2C_CTL = 00CBh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R R

Note: R/W = Read/Write; R = Read Only.

Bit
Position Value Description
7 0 I2C interrupt is disabled.
IEN
1 I2C interrupt is enabled.
6 0 The I2C bus (SCL/SDA) is disabled and all inputs are ignored.
ENAB
1 The I2C bus (SCL/SDA) is enabled.

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Bit
Position Value Description
5 0 Master mode START condition is sent.
STA
1 Master mode start-transmit START condition on the bus.
4 0 Master mode STOP condition is sent.
STP
1 Master mode stop-transmit STOP condition on the bus.
3 0 I2C interrupt flag is not set.
IFLG
1 I2C interrupt flag is set.
2 0 Not Acknowledge.
AAK
1 Acknowledge.
[1:0] 00 Reserved.

I2C Status Register

The I2C_SR register is a Read Only register that contains a 5-bit status code in the five
MSbs; the three LSbs are always 0. The Read Only I2C_SR registers share the same I/
O addresses as the Write Only I2C_CCR registers. See Table 128.

Table 128. I2C Status Registers (I2C_SR = 00CCh)

Bit 7 6 5 4 3 2 1 0
Reset 1 1 1 1 1 0 0 0

CPU Access R R R R R R R R
Note: R = Read only.

Bit
Position Value Description
[7:3] 00000– 5-bit I2C status code.
STAT 11111
[2:0] 000 Reserved.

There are 29 possible status codes, as listed in Table 129. When the I2C_SR register
contains the status code F8h, no relevant status information is available, no interrupt is
generated, and the IFLG bit in the I2C_CTL register is not set. All other status codes
correspond to a defined state of the I2C.

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When each of these states is entered, the corresponding status code appears in this register
and the IFLG bit in the I2C_CTL register is set to 1. When the IFLG bit is cleared, the sta-
tus code returns to F8h.

Table 129. I2C Status Codes

Code Status
00h Bus error.
08h START condition transmitted.
10h Repeated START condition transmitted.
18h Address and Write bit transmitted, ACK received.
20h Address and Write bit transmitted, ACK not received.
28h Data byte transmitted in MASTER mode, ACK received.
30h Data byte transmitted in MASTER mode, ACK not received.
38h Arbitration lost in address or data byte.
40h Address and Read bit transmitted, ACK received.
48h Address and Read bit transmitted, ACK not received.
50h Data byte received in MASTER mode, ACK transmitted.
58h Data byte received in MASTER mode, NACK transmitted.
60h Slave address and Write bit received, ACK transmitted.
68h Arbitration lost in address as master, slave address and Write bit received, ACK transmitted.
70h General Call address received, ACK transmitted.
78h Arbitration lost in address as master, General Call address received, ACK transmitted.
80h Data byte received after slave address received, ACK transmitted.
88h Data byte received after slave address received, NACK transmitted.
90h Data byte received after General Call received, ACK transmitted.
98h Data byte received after General Call received, NACK transmitted.
A0h STOP or repeated START condition received in SLAVE mode.
A8h Slave address and Read bit received, ACK transmitted.
B0h Arbitration lost in address as master, slave address and Read bit received, ACK transmitted.
B8h Data byte transmitted in SLAVE mode, ACK received.
C0h Data byte transmitted in SLAVE mode, ACK not received.
C8h Last byte transmitted in SLAVE mode, ACK received.
D0h Second Address byte and Write bit transmitted, ACK received.

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Table 129. I2C Status Codes (Continued)

Code Status
D8h Second Address byte and Write bit transmitted, ACK not received.
F8h No relevant status information, IFLG = 0.

If an illegal condition occurs on the I2C bus, the bus error state is entered (status code
00h). To recover from this state, the STP bit in the I2C_CTL register must be set and the
IFLG bit cleared. The I2C then returns to an idle state. No STOP condition is transmitted
on the I2C bus.
Note: The STP and STA bits are set to 1 at the same time to recover from the bus error. The I2C
then sends a START condition.

I2C Clock Control Register

The I2C_CCR register is a Write Only register. The seven LSBs control the frequency at
which the I2C bus is sampled and the frequency of the I2C clock line (SCL) when the I2C
is in MASTER mode. The Write Only I2C_CCR registers share the same I/O addresses as
the Read Only I2C_SR registers. See Table 130.

Table 130. I2C Clock Control Registers (I2C_CCR = 00CCh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access W W W W W W W W
Note: W = Read only.

Bit
Position Value Description
7 0 Reserved.
[6:3] 0000–1111 I2C clock divider scalar value.
M
[2:0] 000–111 I2C clock divider exponent.
N
The I2C clocks are derived from the system clock of the eZ80F91 device. The frequency
of this system clock is fSCK. The I2C bus is sampled by the I2C block at the frequency
fSAMP supplied by the following equation:

fSCLK
fSAMP =
2N

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In MASTER mode, the I2C clock output frequency on SCL (fSCL) is supplied by the fol-
lowing equation:

fSCLK
fSCL =
10 • (M + 1)(2)N

The use of two separately-programmable dividers allows the MASTER mode output
frequency to be set independently of the frequency at which the I2C bus is sampled. This
feature is particularly useful in multimaster systems because the frequency at which the
I2C bus is sampled must be at least 10 times the frequency of the fastest master on the bus
to ensure that START and STOP conditions are always detected. By using two
programmable clock divider stages, a high sampling frequency is ensured while allowing
the MASTER mode output to be set to a lower frequency.

Bus Clock Speed

The I2C bus is defined for bus clock speeds up to 100 kbps (400 kbps in FAST mode).
To ensure correct detection of START and STOP conditions on the bus, the I2C must sam-
ple the I2C bus at least ten times faster than the bus clock speed of the fastest master on the
bus. The sampling frequency must therefore be at least 1 MHz (4 MHz in FAST mode) to
guarantee correct operation with other bus masters.
The I2C sampling frequency is determined by the frequency of the eZ80F91 system clock
and the value in the I2C_CCR bits 2 to 0. The bus clock speed generated by the I2C in
MASTER mode is determined by the frequency of the input clock and the values in
I2C_CCR[2:0] and I2C_CCR[6:3].

I2C Software Reset Register

The I2C_SRR register is a Write Only register. Writing any value to this register performs
a software reset of the I2C module. See Table 131.

Table 131. I2C Software Reset Register (I2C_SRR = 00CDh)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access W W W W W W W W
Note: W = Write Only.

Bit
Position Value Description
[7:0] 00h–FFh Writing any value to this register performs a software reset
SRR of the I2C module.

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Zilog Debug Interface

Introduction
The Zilog Debug Interface (ZDI) provides a built-in debugging interface to the CPU. ZDI
provides basic in-circuit emulation features including:
• Examining and modifying internal registers.
• Examining and modifying memory.
• Starting and stopping the user program.
• Setting program and data break points.
• Single-stepping the user program.
• Executing user-supplied instructions.
• Debugging the final product with the inclusion of one small connector.
• Downloading code into SRAM.
• C source-level debugging using Zilog Developer Studio II (ZDS II).

The above features are built into the silicon. Control is provided via a two-wire interface
that is connected to the USB Smart Cable emulator. Figure 48 displays a typical setup
using a a target board, USB Smart Cable, and the host PC running Zilog Developer Studio
II. For more information on USB Smart Cable and ZDS II, refer to www.zilog.com.

Target Board
C
O
N
Zilog N
Developer USB Smart eZ80®
E
Studio Cable C Product
Emulator T
O
R

Figure 48. Typical ZDI Debug Setup

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ZDI allows reading and writing of most internal registers without disturbing the state of
the machine. Reads and Writes to memory occurs as fast as the ZDI downloads and
uploads data, with a maximum supported ZDI clock frequency of 0.4 times the eZ80F91
system clock frequency. Also, regardless of the ZDI clock frequency, the duration of the
low-phase of the ZDI clock (that is, ZCL = 0) must be at least 1.25 times the system clock
period.
For the description on how to enable the ZDI interface on the exit of RESET, see the OCI
Activation on page 258.

Table 132. Recommend ZDI Clock versus System Clock Frequency

System Clock Frequency ZDI Clock Frequency

3–10 MHz 1 MHz
8–16 MHz 2 MHz
12–24 MHz 4 MHz
20–50 MHz 8 MHz

ZDI-Supported Protocol
ZDI supports a bidirectional serial protocol. The protocol defines any device that sends
data as the transmitter and any receiving device as the receiver. The device controlling the
transfer is the master and the device being controlled is the slave. The master always initi-
ates the data transfers and provides the clock for both receive and transmit operations. The
ZDI block on the eZ80F91 device is considered a slave in all data transfers.
Figure 49 on page 233 displays the schematic for building a connector on a target board.
This connector allows you to connect directly to the USB Smart Cable emulator using a
six-pin header.

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TVDD
(Target VDD )

10 Kohm 10 Kohm
2 1

4 3
eZ80F91 TCK (ZCL)
6 5
TDI (ZDA)

6-Pin Target Connector

Figure 49. Schematic For Building a Target Board USB Smart Cable
Connector

ZDI Clock and Data Conventions

The two pins used for communication with the ZDI block are the ZDI clock pin (ZCL) and
the ZDI data pin (ZDA). On eZ80F91, the ZCL pin is shared with the TCK pin while the
ZDA pin is shared with the TDI pin. The ZCL and ZDA pin functions are only available
when the On-Chip Instrumentation is disabled and the ZDI is therefore enabled. For gen-
eral data communication, the data value on the ZDA pin changes only when ZCL is Low
(0). The only exception is the ZDI START bit, which is indicated by a High-to-Low transi-
tion (falling edge) on the ZDA pin while ZCL is High.
Data is shifted into and out of ZDI, with the MSb (bit 7) of each byte being first in time,
and the LSb (bit 0) last in time. All information is passed between the master and the slave
in 8-bit (single-byte) units. Each byte is transferred with nine clock cycles; eight to shift
the data, and the ninth for internal operations.

ZDI START Condition

All ZDI commands are preceded by the ZDI START signal, which is a High-to-Low tran-
sition of ZDA when ZCL is High. The ZDI slave on the eZ80F91 device continually mon-
itors the ZDA and ZCL lines for the START signal and does not respond to any command
until this condition is met. The master pulls ZDA Low, with ZCL High, to indicate the
beginning of a data transfer with the ZDI block. Figure 50 on page 234 and Figure 51 on
page 234 displays a valid ZDI START signal prior to writing and reading data, respec-
tively. A Low-to-High transition of ZDA while the ZCL is High produces no effect.

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Data is shifted in during a Write to the ZDI block on the rising edge of ZCL, as displayed
in Figure 50. Data is shifted out during a Read from the ZDI block on the falling edge of
ZCL as displayed in Figure 51. When an operation is completed, the master stops during
the ninth cycle and holds the ZCL signal High.

ZDI Data In ZDI Data In

(Write) (Write)

ZCL

ZDA

Start Signal

Figure 50. ZDI Write Timing

ZDI Data Out ZDI Data Out

(Read) (Read)

ZCL

ZDA

Start Signal

Figure 51. ZDI Read Timing

ZDI Single-Bit Byte Separator

Following each 8-bit ZDI data transfer, a single-bit byte separator is used. To initiate a
new ZDI command, the single-bit byte separator must be High (logical 1) to allow for a
new ZDI START command to be sent. For all other cases, the single-bit byte separator is
either Low (logical 0) or High (logical 1). When ZDI is configured to allow the CPU to

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accept external bus requests, the single-bit byte separator must be Low (logical 0) during
all ZDI commands. This Low value indicates that ZDI is still operating and is not ready to
relinquish the bus. The CPU does not accept the external bus requests until the single-bit
byte separator is a High (logical 1). For more information on accepting bus requests in
ZDI DEBUG mode, see Bus Requests During ZDI Debug Mode on page 238.

ZDI Register Addressing

Following a START signal the ZDI master must output the ZDI register address. All data
transfers with the ZDI block use special ZDI registers. The ZDI control registers that
reside in the ZDI register address space must not be confused with the eZ80F91 device
peripheral registers that reside in the I/O address space.
Many locations in the ZDI control register address space are shared by two registers—one
for Read Only access and one for Write Only access. For example, a Read from ZDI regis-
ter address 00h returns the eZ80® Product ID Low Byte, while a Write to this same loca-
tion, 00h, stores the Low byte of one of the address match values used for generating
break points.
The format for a ZDI address is seven bits of address, followed by one bit for Read or
Write control, and completed by a single-bit byte separator. The ZDI executes a Read or
Write operation depending on the state of the R/W bit (0 = Write, 1 = Read). If no new
START command is issued at completion of the Read or Write operation, the operation is
repeated. This allows repeated Read or Write operations without having to resend the ZDI
command. A START signal must follow to initiate a new ZDI command. Figure 52 dis-
plays the timing for address Writes to ZDI registers.

Single-Bit
Byte Separator
or new ZDI
START Signal

ZDI Address Byte

ZCL S 1 2 3 4 5 6 7 8 9

ZDA A6 A5 A4 A3 A2 A1 A0 R/W 0/1

msb lsb

START 0 = WRITE
Signal 1 = READ

Figure 52. ZDI Address Write Timing

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ZDI Write Operations

ZDI Single-Byte Write
For single-byte Write operations, the address and write control bit are first written to the
ZDI block. Following the single-bit byte separator, the data is shifted into the ZDI block
on the next 8 rising edges of ZCL. The master terminates activity after 8 clock cycles.
Figure 53 displays the timing for ZDI single-byte Write operations.

ZDI Data Byte

ZCL 7 8 9 1 2 3 4 5 6 7 8 9

ZDA A0 Write 0/1 D7 D6 D5 D4 D3 D2 D1 D0 1

msb lsb
of DATA of DATA

lsb of Single-Bit End of Data

ZDI Address Byte Separator or New ZDI
START Signal

Figure 53. ZDI Single-Byte Data Write Timing

ZDI Block Write

The block Write operation is initiated in the same manner as the single-byte Write opera-
tion, but instead of terminating the Write operation after the first data byte is transferred,
the ZDI master continues to transmit additional bytes of data to the ZDI slave on the
eZ80F91 device. After the receipt of each byte of data the ZDI register address increments
by 1. If the ZDI register address reaches the end of the Write Only ZDI register address
space (30h), the address stops incrementing. Figure 54 displays the timing for ZDI block
Write operations.

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ZDI Data Bytes

ZCL 7 8 9 1 2 3 7 8 9 1 2 9

ZDA A0 Write 0/1 D7 D6 D5 D1 D0 0/1 D7 D6 1

msb lsb msb
of DATA of DATA of DATA
Byte 1 Byte 1 Byte 2
lsb of Single-Bit Single-Bit
ZDI Address Byte Separator Byte Separator

Figure 54. ZDI Block Data Write Timing

ZDI Read Operations

ZDI Single-Byte Read
Single-byte Read operations are initiated in the same manner as single-byte Write opera-
tions, with the exception that the R/W bit of the ZDI register address is set to 1. Upon
receipt of a slave address with the R/W bit set to 1, the eZ80F91 device’s ZDI block loads
the selected data into the shifter at the beginning of the first cycle following the single-bit
data separator. The most significant bit (msb) is shifted out first. Figure 55 displays the
timing for ZDI single-byte Read operations.

ZDI Data Byte

ZCL 7 8 9 1 2 3 4 5 6 7 8 9

ZDA A0 Read 0/1 D7 D6 D5 D4 D3 D2 D1 D0 1

msb lsb
of DATA of DATA

lsb of Single-Bit End of Data

ZDI Address Byte Separator or New ZDI
START Signal

Figure 55. ZDI Single-Byte Data Read Timing

Note: In ZDI single-byte read operations, after each read operation, the Program Counter (PC)
address is incremented by two bytes. For example, if the current PC address is 0x00, then

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a read operation at 0x00 increments the PC to 0x02. To read the next byte, the PC must be
decremented by one.

ZDI Block Read

A block Read operation is initiated in the same manner as a single-byte Read; however,
the ZDI master continues to clock in the next byte from the ZDI slave as the ZDI slave
continues to output data. The ZDI register address counter increments with each Read. If
the ZDI register address reaches the end of the Read Only ZDI register address space
(20h), the address stops incrementing. Figure 56 displays the ZDI’s block Read timing.

ZDI Data Bytes

ZCL 7 8 9 1 2 3 7 8 9 1 2 9

ZDA A0 Read 0/1 D7 D6 D5 D1 D0 0/1 D7 D6 1

msb lsb msb
of DATA of DATA of DATA
Byte 1 Byte 1 Byte 2
lsb of Single-Bit Single-Bit
ZDI Address Byte Separator Byte Separator

Figure 56. ZDI Block Data Read Timing

Operation of the eZ80F91 Device during ZDI Break Points

If the ZDI forces the CPU to break, only the CPU suspends operation. The system clock
continues to operate and drive other peripherals. Those peripherals that operate autono-
mously from the CPU continues to operate, if so enabled. For example, the Watchdog
Timer and Programmable Reload Timers continue to count during a ZDI break point.
When using the ZDI interface, any Write or Read operations of peripheral registers in the
I/O address space produces the same effect as Read or Write operations using the CPU. As
many register Read/Write operations exhibit secondary effects, such as clearing flags or
causing operations to commence, the effects of the Read/Write operations during a ZDI
break must be taken into consideration.

Bus Requests During ZDI Debug Mode

The ZDI block on the eZ80F91 device allows an external device to take control of the
address and data bus while the eZ80F91 device is in DEBUG mode. ZDI_BUSACK_EN
causes ZDI to allow or prevent acknowledgement of bus requests by external peripherals.
The bus acknowledge occurs only at the end of the current ZDI operation (indicated by a
High during the single-bit byte separator). The default reset condition is for bus acknowl-

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edgement to be disabled. To allow bus acknowledgement, the ZDI_BUSACK_EN must be

written.
When an external bus request (BUSREQ pin asserted) is detected, ZDI waits until comple-
tion of the current operation before responding. ZDI acknowledges the bus request by
asserting the bus acknowledge (BUSACK) signal. If the ZDI block is not currently shift-
ing data, it acknowledges the bus request immediately. ZDI uses the single-bit byte separa-
tor of each data word to determine if it is at the end of a ZDI operation. If the bit is a
logical 0, ZDI does not assert BUSACK to allow additional data Read or Write operations.
If the bit is a logical 1, indicating completion of the ZDI commands, BUSACK is asserted.

Potential Hazards of Enabling Bus Requests During DEBUG Mode

There are some potential hazards that you must be aware of when enabling external bus
requests during ZDI DEBUG mode. First, when the address and data bus are being used
by an external source, ZDI must only access ZDI registers and internal CPU registers to
prevent possible bus contention. The bus acknowledge status is reported in the
ZDI_BUS_STAT register. The BUSACK output pin also indicates the bus acknowledge
state.
A second hazard is that when a bus acknowledge is granted, the ZDI is subject to any wait
states that are assigned to the device currently being accessed by the external peripheral.
To prevent data errors, ZDI must avoid data transmission while another device is
controlling the bus.
Finally, exiting ZDI DEBUG mode while an external peripheral controls the address and
data buses, as indicated by BUSACK assertion produces unpredictable results.

ZDI Write Only Registers

Table 133 lists the ZDI Write Only registers. Many of the ZDI Write Only addresses are
shared with ZDI Read Only registers.

Table 133. ZDI Write Only Registers

Reset
ZDI Address ZDI Register Name ZDI Register Function Value
00h ZDI_ADDR0_L Address Match 0 Low Byte XXh
01h ZDI_ADDR0_H Address Match 0 High Byte XXh
02h ZDI_ADDR0_U Address Match 0 Upper Byte XXh
04h ZDI_ADDR1_L Address Match 1 Low Byte XXh
05h ZDI_ADDR1_H Address Match 1 High Byte XXh
06h ZDI_ADDR1_U Address Match 1 Upper Byte XXh

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Table 133. ZDI Write Only Registers (Continued)

Reset
ZDI Address ZDI Register Name ZDI Register Function Value
08h ZDI_ADDR2_L Address Match 2 Low Byte XXh
09h ZDI_ADDR2_H Address Match 2 High Byte XXh
0Ah ZDI_ADDR2_U Address Match 2 Upper Byte XXh
0Ch ZDI_ADDR3_L Address Match 3 Low Byte XXh
0Dh ZDI_ADDR3_H Address Match 3 High Byte XXh
0Eh ZDI_ADDR3_U Address Match 4 Upper Byte XXh
10h ZDI_BRK_CTL Break Control Register 00h
11h ZDI_MASTER_CTL Master Control Register 00h
13h ZDI_WR_DATA_L Write Data Low Byte XXh
14h ZDI_WR_DATA_H Write Data High Byte XXh
15h ZDI_WR_DATA_U Write Data Upper Byte XXh
16h ZDI_RW_CTL Read/Write Control Register 00h
17h ZDI_BUS_CTL Bus Control Register 00h
21h ZDI_IS4 Instruction Store 4 XXh
22h ZDI_IS3 Instruction Store 3 XXh
23h ZDI_IS2 Instruction Store 2 XXh
24h ZDI_IS1 Instruction Store 1 XXh
25h ZDI_IS0 Instruction Store 0 XXh
30h ZDI_WR_MEM Write Memory Register XXh

ZDI Read Only Registers

Table 134 lists the ZDI Read Only registers. Many of the ZDI Read Only addresses are
shared with ZDI Write Only registers.

Table 134. ZDI Read Only Registers

Reset
ZDI Address ZDI Register Name ZDI Register Function Value
00h ZDI_ID_L eZ80® Product ID Low Byte Register 08h
01h ZDI_ID_H eZ80 Product ID High Byte Register 00h
02h ZDI_ID_REV eZ80 Product ID Revision Register XXh

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Table 134. ZDI Read Only Registers (Continued)

Reset
ZDI Address ZDI Register Name ZDI Register Function Value
03h ZDI_STAT Status Register 00h
10h ZDI_RD_L Read Memory Address Low Byte Register XXh
11h ZDI_RD_H Read Memory Address High Byte Register XXh
12h ZDI_RD_U Read Memory Address Upper Byte Register XXh
17h ZDI_BUS_STAT Bus Status Register 00h
20h ZDI_RD_MEM Read Memory Data Value XXh

ZDI Register Definitions

ZDI Address Match Registers
The four sets of address match registers are used for setting the addresses for generating
break points. When the accompanying BRK_ADDRX bit is set in the ZDI Break Control
register to enable the particular address match, the current eZ80F91 address is compared
with the 3-byte address set, {ZDI_ADDRx_U, ZDI_ADDRx_H, and ZDI_ADDR_x_L}.
If the CPU is operating in ADL mode, the address is supplied by ADDR[23:0]. If the CPU
is operating in Z80® mode, the address is supplied by {MBASE[7:0], ADDR[15:0]}. If a
match is found, ZDI issues a break to the eZ80F91 device placing the CPU in ZDI mode
pending further instructions from the ZDI interface block. If the address is not the first op-
code fetch, the ZDI break is executed at the end of the instruction in which it is executed.
There are four sets of address match registers. They are used in conjunction with each
other to break on branching instructions. See Table 135 on page 241.

Table 135. ZDI Address Match Registers

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access W W W W W W W W
Note: W = Write Only.

Bit
Position Value Description
[7:0] 00h–FFh The four sets of ZDI address match registers are used for
zdi_addrx_l, setting the addresses for generating break points. The 24
zdi_addrx_h, bit addresses are supplied by {ZDI_ADDRx_U,
or ZDI_ADDRx_H, ZDI_ADDRx_L, where x is 0, 1, 2, or 3.
zdi_addrx_u

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Address Information for ZDI Address Match Registers

ZDI_ADDR0_L = 00h, ZDI_ADDR0_H = 01h, ZDI_ADDR0_U = 02h, ZDI_ADDR1_L =
04h, ZDI_ADDR1_H = 05h, ZDI_ADDR1_U = 06h, ZDI_ADDR2_L = 08h, ZDI_ADDR2_H
= 09h, ZDI_ADDR2_U = 0Ah, ZDI_ADDR3_L = 0Ch, ZDI_ADDR3_H = 0Dh, and
ZDI_ADDR3_U = 0Eh in the ZDI Register Write Only Address Space.

ZDI Break Control Register

The ZDI Break Control register is used to enable break points. ZDI asserts a break when
the CPU instruction address, ADDR[23:0], matches the value in the ZDI Address Match 3
registers, {ZDI_ADDR3_U, ZDI_ADDR3_H, ZDI_ADDR3_L}. BREAKs occurs only
on an instruction boundary. If the instruction address is not the beginning of an instruction
(that is, for multibyte instructions), then the break occurs at the end of the current instruc-
tion. The brk_next bit is set to 1. The brk_next bit must be reset to 0 to release the break.
See Table 136 on page 243.

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Table 136. ZDI Break Control Register (ZDI_BRK_CTL = 10h in the ZDI Write Only Register
Address Space)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access W W W W W W W W
Note: W = Write Only.

Bit
Position Value Description
7 0 The ZDI break on the next CPU instruction is disabled.
brk_next Clearing this bit releases the CPU from its current BREAK
condition.
1 The ZDI break on the next CPU instruction is enabled. The
CPU uses multibyte Op Codes and multibyte operands.
Break points only occur on the first Op Code in a multibyte
Op Code instruction. If the ZCL pin is High and the ZDA pin
is Low at the end of RESET, this bit is set to 1 and a break
occurs on the first instruction following the RESET. This bit
is set automatically during ZDI break on address match. A
break is also forced by writing a 1 to this bit.
6 0 The ZDI break, upon matching break address 3, is
brk_addr3 disabled.
1 The ZDI break, upon matching break address 3, is
enabled.
5 0 The ZDI break, upon matching break address 2, is
brk_addr2 disabled.
1 The ZDI break, upon matching break address 2, is
enabled.
4 0 The ZDI break, upon matching break address 1, is
brk_addr1 disabled.
1 The ZDI break, upon matching break address 1, is
enabled.
3 0 The ZDI break, upon matching break address 0, is
brk_addr0 disabled.
1 The ZDI break, upon matching break address 0, is
enabled.

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Bit
Position Value Description
2 0 The Ignore the Low Byte function of the ZDI Address Match
ign_low_1 1 registers is disabled. If brk_addr1 is set to 1, ZDI initiates
a break when the entire 24-bit address, ADDR[23:0],
matches the 3-byte value {ZDI_ADDR1_U,
ZDI_ADDR1_H, ZDI_ADDR1_L}.
1 The Ignore the Low Byte function of the ZDI Address Match
1 registers is enabled. If brk_addr1 is set to 1, ZDI initiates
a break when only the upper 2 bytes of the 24-bit address,
ADDR[23:8], match the 2-byte value {ZDI_ADDR1_U,
ZDI_ADDR1_H}. As a result, a break occurs anywhere
within a 256-byte page.
1 0 The Ignore the Low Byte function of the ZDI Address Match
ign_low_0 1 registers is disabled. If brk_addr0 is set to 1, ZDI initiates
a break when the entire 24-bit address, ADDR[23:0],
matches the 3-byte value {ZDI_ADDR0_U,
ZDI_ADDR0_H, ZDI_ADDR0_L}.
1 The Ignore the Low Byte function of the ZDI Address Match
1 registers is enabled. If the brk_addr1 is set to 0, ZDI
initiates a break when only the upper 2 bytes of the 24-bit
address, ADDR[23:8], match the 2 bytes value
{ZDI_ADDR0_U, ZDI_ADDR0_H}. As a result, a break
occurs anywhere within a 256-byte page.
0 0 ZDI single step mode is disabled.
single_step
1 ZDI single step mode is enabled. ZDI asserts a break
following execution of each instruction.

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ZDI Master Control Register

The ZDI Master Control register provides control of the eZ80F91 device. It is capable of
forcing a RESET and waking up the eZ80F91 from the LOW-POWER modes (HALT or
SLEEP). See Table 137.

Table 137. ZDI Master Control Register (ZDI_MASTER_CTL = 11h in ZDI Register Write
Address Spaces)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access W W W W W W W W
Note: W = Write Only.

Bit
Position Value Description
7 0 No action.
ZDI_RESET
1 Initiate a RESET of the eZ80F91. This bit is automatically
cleared at the end of the RESET event.
[6:0] 0000000 Reserved.

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ZDI Write Data Registers

These three registers are used in the ZDI Write Only register address space to store the
data that is written when a Write instruction is sent to the ZDI Read/Write Control register
(ZDI_RW_CTL). The ZDI Read/Write Control register is located at ZDI address 16h
immediately following the ZDI Write Data registers. As a result, the ZDI Master is
allowed to write the data to {ZDI_WR_U, ZDI_WR_H, ZDI_WR_L} and the Write
command in one data transfer operation. See Table 138.

Table 138. ZDI Write Data Registers (ZDI_WR_U = 13h, ZDI_WR_H = 14h, and ZDI_WR_L =
15h in the ZDI Register Write Only Address Space)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access W W W W W W W W
Note: X = Undefined; W = Write.

Bit
Position Value Description
[7:0] 00h–FFh These registers contain the data that is written during
zdi_wr_l, execution of a Write operation defined by the
zdi_wr_h, ZDI_RW_CTL register. The 24-bit data value is stored
or as {ZDI_WR_U, ZDI_WR_H, ZDI_WR_L}. If less than
zdi_wr_l 24 bits of data are required to complete the required
operation, the data is taken from the LSBs.

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ZDI Read/Write Control Register

The ZDI Read/Write Control register is used in the ZDI Write Only Register address to
read data from, write data to, and manipulate the CPU’s registers or memory locations.
When this register is written, the eZ80F91 device immediately performs the operation
corresponding to the data value written as listed in Table 139. When a Read operation is
executed via this register, the requested data values are placed in the ZDI Read Data
registers {ZDI_RD_U, ZDI_RD_H, ZDI_RD_L}. When a Write operation is executed via
this register, the Write data is taken from the ZDI Write Data registers {ZDI_WR_U,
ZDI_WR_H, ZDI_WR_L}. See Table 139. For information on the CPU registers, refer to
eZ80® CPU User Manual (UM0077) available on www.zilog.com.
Note: The CPU’s alternate register set (A’, F’, B’, C’, D’, E’, HL’) cannot be read directly. The
ZDI programmer must execute the exchange instruction (EXX) to gain access to the alter-
nate CPU register set.

Table 139. ZDI Read/Write Control Register Functions (ZDI_RW_CTL = 16h in the ZDI
Register Write Only Address Space)

Hex Hex
Value Command Value Command
00 Read {MBASE, A, F} 80 Write AF
ZDI_RD_U ← MBASE MBASE ← ZDI_WR_U
ZDI_RD_H ← F F ← ZDI_WR_H
ZDI_RD_L ← A A ← ZDI_WR_L
01 Read BC 81 Write BC
ZDI_RD_U ← BCU BCU ← ZDI_WR_U
ZDI_RD_H ← B B ← ZDI_WR_H
ZDI_RD_L ← C C ← ZDI_WR_L
02 Read DE 82 Write DE
ZDI_RD_U ← DEU DEU ← ZDI_WR_U
ZDI_RD_H ← D D ← ZDI_WR_H
ZDI_RD_L ← E E ← ZDI_WR_L
03 Read HL 83 Write HL
ZDI_RD_U ← HLU HLU ← ZDI_WR_U
ZDI_RD_H ← H H ← ZDI_WR_H
ZDI_RD_L ← L L ← ZDI_WR_L
04 Read IX 84 Write IX
ZDI_RD_U ← IXU IXU ← ZDI_WR_U
ZDI_RD_H ← IXH IXH ← ZDI_WR_H
ZDI_RD_L ← IXL IXL ← ZDI_WR_L

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Table 139. ZDI Read/Write Control Register Functions (ZDI_RW_CTL = 16h in the ZDI
Register Write Only Address Space) (Continued)

Hex Hex
Value Command Value Command
05 Read IY 85 Write IY
ZDI_RD_U ← IYU IYU ← ZDI_WR_U
ZDI_RD_H ← IYH IYH ← ZDI_WR_H
ZDI_RD_L ← IYL IYL ← ZDI_WR_L
06 Read SP 86 Write SP
In ADL mode, SP = SPL. In ADL mode, SP = SPL.
In Z80® mode, SP = SPS. In Z80 mode, SP = SPS.
07 Read PC 87 Write PC
ZDI_RD_U ← PC[23:16] PC[23:16] ← ZDI_WR_U
ZDI_RD_H ← PC[15:8] PC[15:8] ← ZDI_WR_H
ZDI_RD_L ← PC[7:0] PC[7:0] ← ZDI_WR_L
08 Set ADL 88 Reserved
ADL ← 1
09 Reset ADL 89 Reserved
ADL ← 0
0A Exchange CPU register sets 8A Reserved
AF ← AF’
BC ← BC’
DE ← DE’
HL ← HL’
0B Read memory from current PC 8B Write memory from current PC
value, increment PC value, increment PC

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ZDI Bus Control Register

The ZDI Bus Control register controls bus requests during DEBUG mode. It enables or
disables bus acknowledge in ZDI DEBUG mode and allows ZDI to force assertion of the
BUSACK signal. This register must only be written during ZDI DEBUG mode (that is,
following a break). See Table 140.

Table 140. ZDI Bus Control Register (ZDI_BUS_CTL = 17h in the ZDI Register Write Only
Address Space)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access W W W W W W W W
Note: W = Write Only.

Bit
Position Value Description
7 0 Bus requests by external peripherals using the BUSREQ
ZDI_BUSAK_EN pin are ignored. The bus acknowledge signal, BUSACK, is
not asserted in response to any bus requests.
1 Bus requests by external peripherals using the BUSREQ
pin are accepted. A bus acknowledge occurs at the end of
the current ZDI operation. The bus acknowledge is
indicated by asserting the BUSACK pin in response to a
bus request.
6 0 Deassert the bus acknowledge pin (BUSACK) to return
ZDI_BUSAK control of the address and data buses back to ZDI.
1 Assert the bus acknowledge pin (BUSACK) to pass control
of the address and data buses to an external peripheral.
[5:0] 000000 Reserved.

Instruction Store 4:0 Registers

The ZDI Instruction Store registers are located in the ZDI Register Write Only address
space. They are written with instruction data for direct execution by the CPU. When the
ZDI_IS0 register is written, the eZ80F91 device exits the ZDI break state and executes a
single instruction. The opcodes and operands for the instruction come from these Instruc-
tion Store registers. The Instruction Store Register 0 is the first byte fetched, followed by
Instruction Store registers 1, 2, 3, and 4, as necessary. Only the bytes the CPU requires to
execute the instruction must be stored in these registers. Some CPU instructions, when
combined with the MEMORY mode suffixes (.SIS, .SIL, .LIS, or .LIL), require 6 bytes to

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operate. These 6-byte instructions cannot be executed directly using the ZDI Instruction
Store registers. See Table 141.
Note: The Instruction Store 0 register is located at a higher ZDI address than the other Instruc-
tion Store registers. This feature allows the use of the ZDI auto-address increment function
to load and execute a multibyte instruction with a single data stream from the ZDI master.
Execution of the instruction commences with writing the final byte to ZDI_IS0.

Table 141. Instruction Store 4:0 Registers (ZDI_IS4 = 21h, ZDI_IS3 = 22h, ZDI_IS2 = 23h,
ZDI_IS1 = 24h, and ZDI_IS0 = 25h in the ZDI Register Write Only Address Space)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access W W W W W W W W
Note: X = Undefined; W = Write.

Bit
Position Value Description
[7:0] 00h–FFh These registers contain the Op Codes and operands for
zdi_is4, immediate execution by the CPU following a Write to
zdi_is3, ZDI_IS0. The ZDI_IS0 register contains the first Op Code
zdi_is2, of the instruction. The remaining ZDI_ISx registers
zdi_is1, contain any additional Op Codes or operand dates
or required for execution of the required instruction.
zdi_is0

ZDI Write Memory Register

A Write to the ZDI Write Memory register causes the eZ80F91 device to write the 8-bit
data to the memory location specified by the current address in the Program Counter. In
Z80® MEMORY mode, this address is {MBASE, PC[15:0]}. In ADL MEMORY mode,
this address is PC[23:0]. The Program Counter, PC, increments after each data Write.
However, the ZDI register address does not increment automatically when this register
is accessed. As a result, the ZDI master is allowed to write any number of data bytes by
writing to this address one time followed by any number of data bytes. See Table 142
on page 251.

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Table 142. ZDI Write Memory Register (ZDI_WR_MEM = 30h in the ZDI Register Write Only
Address Space)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X
CPU Access W W W W W W W W
Note: X = Undefined; W = Write.

Bit
Position Value Description
[7:0] 00h–FFh The 8-bit data that is transferred to the ZDI slave
zdi_wr_mem following a Write to this address is written to the address
indicated by the current Program Counter. The Program
Counter is incremented following each 8 bits of data. In
Z80® MEMORY mode, ({MBASE, PC[15:0]}) ← 8 bits of
transferred data. In ADL MEMORY mode, (PC[23:0]) ←
8-bits of transferred data.

eZ80® Product ID Low and High Byte Registers

The eZ80 Product ID Low and High Byte registers combine to provide a means for an
external device to determine the particular eZ80 product being addressed. See Table 143
and Table 144 on page 252.

Table 143. eZ80 Product ID Low Byte Register (ZDI_ID_L = 00h in the ZDI Register Read Only
Address Space, ZDI_ID_L = 0000h in the I/O Register Address Space)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 1 0 0 0

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0] 08h {ZDI_ID_H, ZDI_ID_L} = {00h, 08h} indicates the eZ80F91
zdi_id_l product.

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Table 144. eZ80® Product ID High Byte Register (ZDI_ID_H = 01h in the ZDI Register Read Only
Address Space, ZDI_ID_H = 0001h in the I/O Register Address Space)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0] 00h {ZDI_ID_H, ZDI_ID_L} = {00h, 08h} indicates the eZ80F91
zdi_id_H device.

eZ80 Product ID Revision Register

The eZ80 Product ID Revision register identifies the current revision of the eZ80F91
product. See Table 145.

Table 145. eZ80 Product ID Revision Register (ZDI_ID_REV = 02h in the ZDI Register Read
Only Address Space, ZDI_ID_REV = 0002h in the I/O Register Address Space)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R R R R R R R R
Note: X = Undetermined; R = Read Only.

Bit
Position Value Description
[7:0] 00h–FFh Identifies the current revision of the eZ80F91 product.
zdi_id_rev

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ZDI Status Register

The ZDI Status register provides current information on the eZ80F91 device and the CPU.
See Table 146.

Table 146. ZDI Status Register (ZDI_STAT = 03h in the ZDI Register Read Only Address Space)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
7 0 The CPU is not functioning in ZDI mode.
zdi_active
1 The CPU is currently functioning in ZDI mode.
6 0 Reserved.
5 0 The CPU is not currently in HALT or SLEEP mode.
halt_SLP
1 The CPU is currently in HALT or SLEEP mode.
4 0 The CPU is operating in Z80® MEMORY mode.
ADL (ADL bit = 0)
1 The CPU is operating in ADL MEMORY mode.
(ADL bit = 1)
3 0 The CPU’s Mixed-Memory mode (MADL) bit is reset to 0.
MADL
1 The CPU’s Mixed-Memory mode (MADL) bit is set to 1.
2 0 The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable
IEF1 interrupts are disabled.
1 The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable
interrupts are enabled.
[1:0] 00 Reserved.
Reserved

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ZDI Read Register Low, High, and Upper

The ZDI register Read Only address space offers Low, High, and Upper functions, which
contain the value read by a Read operation from the ZDI Read/Write Control register
(ZDI_RW_CTL). This data is valid only while in ZDI BREAK mode and only if the
instruction is read by a request from the ZDI Read/Write Control register. See Table 147.

Table 147. ZDI Read Register Low, High, and Upper (ZDI_RD_L = 10h, ZDI_RD_H = 11h, and
ZDI_RD_U = 12h in the ZDI Register Read Only Address Space)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0] 00h–FFh Values read from the memory location as requested by the
zdi_rd_l, ZDI Read Control register during a ZDI Read operation.
zdi_rd_h, The 24-bit value is supplied by {ZDI_RD_U, ZDI_RD_H,
or ZDI_RD_L}.
zdi_rd_u

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ZDI Bus Status Register

The ZDI Bus Status register monitors BUSACKs during DEBUG mode. See Table 148.

Table 148. ZDI Bus Control Register (ZDI_BUS_STAT = 17h in the ZDI Register Read Only
Address Space)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
7 0 Bus requests by external peripherals using the
ZDI_BUSAcK_En BUSREQ pin are ignored. The bus acknowledge signal,
BUSACK, is not asserted.
1 Bus requests by external peripherals using the
BUSREQ pin are accepted. A bus acknowledge occurs
at the end of the current ZDI operation. The bus
acknowledge is indicated by asserting the BUSACK pin.
6 0 Address and data buses are not relinquished to an
ZDI_BUS_STAT external peripheral. bus acknowledge is deasserted
(BUSACK pin is High).
1 Address and data buses are relinquished to an external
peripheral. bus acknowledge is asserted (BUSACK pin
is Low).
[5:0] 000000 Reserved.

ZDI Read Memory Register

When a Read is executed from the ZDI Read Memory register, the eZ80F91 device
fetches the data from the memory address currently pointed to by the Program Coun-
ter, PC; the Program Counter is then incremented. In Z80® MEMORY mode, the
memory address is {MBASE, PC[15:0]}. In ADL MEMORY mode, the memory
address is PC[23:0]. For more information on Z80 and ADL MEMORY modes, refer
to the eZ80® CPU User Manual (UM0077) available on www.zilog.com. The Pro-
gram Counter, PC, increments after each data Read. However, the ZDI register address
does not increment automatically when this register is accessed. As a result, the ZDI
master reads any number of data bytes out of memory via the ZDI Read Memory reg-
ister. See Table 149 on page 256.

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Note that the delay between issuing a memory read request and the return of the corre-
sponding data amount to multiple ZDI clock cycles. This delay is a function of the wait
state configuration of the memory space being accessed as well as the relative frequencies
of the ZDI clock and the system clock. If the ZDI master begins clocking the read data out
of the eZ80F91 soon after issuing the memory read request, invalid data will be returned.
Since no data-valid handshake mechanism exists in the ZDI protocol, the ZDI master must
account for expected memory read delay in some way.
A technique exists to mask this delay in almost all situations. It always reads at least two
consecutive bytes, starting one address lower than the address of interest. In this situation,
the eZ80F91 internally prefetches the data from the second address while the ZDI master
is sending the second read request. This allows enough time for the second ZDI memory
read to return valid data. The first data byte returned to the ZDI master must be discarded
since it is invalid. Memory reads of more than two consecutive bytes will also return cor-
rect data for all but the first address.

Table 149. ZDI Read Memory Register (ZDI_RD_MEM = 20h in the ZDI Register Read Only
Address Space)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0] 00h–FFh 8-bit data Read from the memory address indicated by
zdi_rd_mem the CPU’s Program Counter. In Z80® Memory mode, 8-
bit data is transferred out from address {MBASE,
PC[15:0]}. In ADL Memory mode, 8-bit data is
transferred out from address PC[23:0].

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On-Chip Instrumentation
Introduction to On-Chip Instrumentation
On-Chip Instrumentation1 (OCI™) for the eZ80® CPU core enables powerful debugging
features. The OCI provides run control, memory and register visibility, complex break
points, and trace history features.
The OCI employs all of the functions of the Zilog Debug Interface (ZDI) as described in
the ZDI section. It also adds the following debug features:
• Control via a 4-pin Joint Test Action Group (JTAG) port that conforms to IEEE Stan-
dard 1149.1 (Test Access Port and Boundary Scan Architecture)
• Complex break point trigger functions
• Break point enhancements, such as the ability to:
– Define two break point addresses that form a range
– Break on masked data values
– Start or stop trace
– Assert a trigger output signal

• Trace history buffer

• Software break point instruction
There are four sections to the OCI:
• JTAG interface
• ZDI debug control
• Trace buffer memory
• Complex triggers
This document contains information to activate the OCI for JTAG boundary scan register
operations. For additional information regarding OCI features, or to order OCI debug
tools, contact:

First Silicon Solutions, Inc.

www.fs2.com

1. On-Chip Instrumentation and OCI are trademarks of First Silicon Solutions, Inc.

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OCI Activation
OCI features clock initialization circuitry so that external debug hardware is detected dur-
ing power-up. The external debugger must drive the OCI clock pin (TCK) Low at least
two system clock cycles prior to the end of the RESET to activate the OCI block. If TCK
is High at the end of the RESET, the OCI block shuts down so that it does not draw power
in normal product operation. When the OCI is shut down, ZDI is enabled directly and is
accessed via the clock (TCK) and data (TDI) pins. For more information on ZDI, see Zilog
Debug Interface on page 231.

OCI Interface
There are six dedicated pins on the eZ80F91 for the OCI interface. Four pins—TCK,
TMS, TDI, and TDO—are required for IEEE Standard 1149.1-compliant JTAG ports. A
fifth pin, TRSTn, is optional for IEEE 1149.1 and utilized by the eZ80F91 device. The
TRIGOUT pin provides additional testability features. These six OCI pins are listed in
Table 150.

Table 150. OCI Pins

Symbol Name Type Description

TCK Clock Input Asynchronous to the primary eZ80F91 system clock.
The TCK period must be at least twice the system
clock period. During RESET, this pin is sampled to
select either OCI or ZDI DEBUG modes. If Low
during RESET, the OCI is enabled. If High during
RESET, the OCI is powered down and ZDI DEBUG
mode is enabled. When ZDI DEBUG mode is active,
this pin is the ZDI clock. On-chip pull-up ensures a
default value of 1 (High).
TRSTn TAP Reset Input Active Low asynchronous reset for the Test Access
Port state register. On-chip pull-up ensures a default
value of 1 (High).
TMS Test Mode Select Input This serial test mode input controls JTAG mode
selection. On-chip pull-up ensures a default value of
1 (High). The TMS signal is sampled on the rising
edge of the TCK signal.
TDI Data In Input Serial test data input. This pin is input-only when the
(OCI enabled) OCI is enabled. The input data is sampled on the
rising edge of the TCK signal.
I/O When the OCI is disabled, this pin functions as the
(OCI disabled) ZDA (ZDI Data) I/O pin. NORMAL mode, following
RESET, configures TDI as an input.

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Table 150. OCI Pins (Continued)

Symbol Name Type Description

TDO Data Out Output The output data changes on the falling edge of the
TCK signal.
TRIGOUT Trigger Output Output Generates an active High trigger pulse when valid
OCI trigger events occur. Output is open-drain when
no data is being driven out.

JTAG Boundary Scan

Introduction
This section describes coverage, implementation, and usage of the eZ80F91 boundary
scan register based on the JTAG standard. A working knowledge of the IEEE 1149.1 spec-
ification, particularly Clause 11, is required.

Pin Coverage
All pins are included in the boundary scan chain, except the following:
• TCK
• TMS
• TDI
• TDO
• TRSTN
• VDD
• VSS
• PLL_VDD
• PLL_VSS
• RTC_VDD
• XIN
• XOUT
• RTC_XIN
• RTC_XOUT
• LOOP_FILT

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Boundary Scan Cell Functionality

The boundary scan cells implemented are analogous to cell BC_1, defined in the Standard
VHDL Package STD_1149_1_2001.
All boundary scan cells are of the type control-and-observe; they provide both controlla-
bility and observability for the pins to which they are connected. For open-drain outputs
and bidirectional pins, this type includes controllability and observability of output
enables.

Chain Sequence and Length

When enabled to shift data, the boundary scan shift register is connected to TDI at the
input line for TRIGOUT and to TDO at PD0. The shift register is arranged so that data is
shifted via the pins starting to the left of the OCI interface pins and proceeding clockwise
around the chip. If a pin features multiple scannable bits (example: bidirectional pins or
open-drain output pins), the data is shifted first into the input signal, then the output, then
the output enable (OEN).
The boundary scan register is 213 bits wide. Table 151 lists the ordering of bits in the shift
register, numbering them in clockwise order.

Table 151. Pin to Boundary Scan Cell Mapping

Pin Direction Scan Cell No Pin Direction Scan Cell No

TRIGOUT Input 0 MII_TxD2 Output 107
TRIGOUT Output 1 MII_TxD3 Output 108
TRIGOUT OEN 2 MII_COL Input 109
HALT_SLP Output 3 MII_CRS Input 110
BUSACK Output 4 PA7 Input 111
BUSREQ Input 5 PA7 Output 112
NMI Input 6 PA7 OEN 113
RESET Input 7 PA6 Input 114
RESET_OUT Output 8 PA6 Output 115
WAIT Input 9 PA6 OEN 116
INSTRD Output 10 PA5 Input 117
WR Output 11 PA5 Output 118
WR OEN 12 PA5 OEN 119
RD Output 13 PA4 Input 120
MREQ Input 14 PA4 Output 121

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Table 151. Pin to Boundary Scan Cell Mapping (Continued)

Pin Direction Scan Cell No Pin Direction Scan Cell No

MREQ Output 15 PA4 OEN 122
IORQ Input 16 PA3 Input 123
IORQ Output 17 PA3 Output 124
D7 Input 18 PA3 OEN 125
D7 Output 19 PA2 Input 126
D6 Input 20 PA2 Output 127
D6 Output 21 PA2 OEN 128
D5 Input 22 PA1 Input 129
D5 Output 23 PA1 Output 130
D4 Input 24 PA1 OEN 131
D4 Output 25 PA0 Input 132
D3 Input 26 PA0 Output 133
D3 Output 27 PA0 OEN 134
D2 Input 28 PHI Output 135
D2 Output 29 PHI OEN 136
D1 Input 30 SCL Input 137
D1 Output 31 SCL Output 138
D0 Input 32 SDA Input 139
D0 Output 33 SDA Output 140
D0 OEN 34 PB7 Input 141
CS3 Output 35 PB7 Output 142
CS2 Output 36 PB7 OEN 143
CS1 Output 37 PB6 Input 144
CS0 Output 38 PB6 Output 145
A23 Input 39 PB6 OEN 146
A23 Output 40 PB5 Input 147
A22 Input 41 PB5 Output 148
A22 Output 42 PB5 OEN 149
A21 Input 43 PB4 Input 150

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Table 151. Pin to Boundary Scan Cell Mapping (Continued)

Pin Direction Scan Cell No Pin Direction Scan Cell No

A21 Output 44 PB4 Output 151
A20 Input 45 PB4 OEN 152
A20 Output 46 PB3 Input 153
A19 Input 47 PB3 Output 154
A19 Output 48 PB3 OEN 155
A18 Input 49 PB2 Input 156
A18 Output 50 PB2 Output 157
A17 Input 51 PB2 OEN 158
A17 Output 52 PB1 Input 159
A16 Input 53 PB1 Output 160
A16 Output 54 PB1 OEN 161
A16 OEN 55 PB0 Input 162
A15 Input 56 PB0 Output 163
A15 Output 57 PB0 OEN 164
A14 Input 58 PC7 Input 165
A14 Output 59 PC7 Output 166
A13 Input 60 PC7 OEN 167
A13 Output 61 PC6 Input 168
A12 Input 62 PC6 Output 169
A12 Output 63 PC6 OEN 170
A11 Input 64 PC5 Input 171
A11 Output 65 PC5 Output 172
A10 Input 66 PC5 OEN 173
A10 Output 67 PC4 Input 174
A9 Input 68 PC4 Output 175
A9 Output 69 PC4 OEN 176
A8 Input 70 PC3 Input 177
A8 Output 71 PC3 Output 178
A8 OEN 72 PC3 OEN 179

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Table 151. Pin to Boundary Scan Cell Mapping (Continued)

Pin Direction Scan Cell No Pin Direction Scan Cell No

A7 Input 73 PC2 Input 180
A7 Output 74 PC2 Output 181
A6 Input 75 PC2 OEN 182
A6 Output 76 PC1 Input 183
A5 Input 77 PC1 Output 184
A5 Output 78 PC1 OEN 185
A4 Input 79 PC0 Input 186
A4 Output 80 PC0 Output 187
A3 Input 81 PC0 OEN 188
A3 Output 82 PD7 Input 189
A2 Input 83 PD7 Output 190
A2 Output 84 PD7 OEN 191
A1 Input 85 PD6 Input 192
A1 Output 86 PD6 Output 193
A0 Input 87 PD6 OEN 194
A0 Output 88 PD5 Input 195
A0 OEN 89 PD5 Output 196
WP Input 90 PD5 OEN 197
MII_MDIO Input 91 PD4 Input 198
MII_MDIO Output 92 PD4 Output 199
MII_MDIO OEN 93 PD4 OEN 200
MII_MDC Output 94 PD3 Input 201
MII_RxD3 Input 95 PD3 Output 202
MII_RxD2 Input 96 PD3 OEN 203
MII_RxD1 Input 97 PD2 Input 204
MII_RxD0 Input 98 PD2 Output 205
MII_Rx_DV Input 99 PD2 OEN 206
MII_Rx_CLK Input 100 PD1 Input 207
MII_Rx_ER Input 101 PD1 Output 208

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Table 151. Pin to Boundary Scan Cell Mapping (Continued)

Pin Direction Scan Cell No Pin Direction Scan Cell No

MII_Tx_ER Output 102 PD1 OEN 209
MII_Tx_CLK Input 103 PD0 Input 210
MII_Tx_EN Output 104 PD0 Output 211
MII_TxD0 Output 105 PD0 OEN 212
MII_TxD1 Output 106
Notes
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
associated with the LSb that they control.
2. Direction on the data bus is controlled by a single output enable. It is associated in this table with D[0].
3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.

Usage
Boundary scan functionality is utilized by issuing the appropriate Test Access Port (TAP)
instruction and shifting data accordingly. Both of these steps are accomplished using the
JTAG interface. To activate the TAP (see OCI Activation on page 258), the TCK pin must
be driven Low at least two CPU system clock cycles prior to the deassertion of the RESET
pin. Otherwise the OCI-JTAG features are disabled.
As per the IEEE 1149.1 specification, the boundary scan cells capture system I/O on the
rising edge of TCK during the CAPTURE_DR state. This captured data is shifted on the
rising edge of TCK while in the SHIFT_DR state. Pins and logic receive shifted data only
when enabled, and only on the falling edge of TCK during the UPDATE_DR state, after
shifting is completed.
For more information about eZ80F91 boundary scan support, refer to Using BSDL Files
with eZ80® and eZ80Acclaim!® Devices (AN0114).

Boundary Scan Instructions

The eZ80F91 device’s boundary scan architecture supports the following instructions:
• BYPASS (required)
• SAMPLE (required)
• EXTEST (required)
• PRELOAD (required)
• IDCODE (optional)

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Phase-Locked Loop
Overview
The Phase-Locked-Loop (PLL) is a programmable frequency multiplier that satisfies the
equation SCLK (Hz) = N * FOSC(Hz). Figure 57 displays the PLL block diagram.

System Clock
(FOSC < SCLK < FOSC * N)

PLL_CTL1[0] = PLL Enable

SCLK-MUX

RTC_CLK
(1MHz < FOSC < 10MHz)
x2
Oscillator PFD Charge VCO Off-Chip
x1 Pump Loop Filter

CPLL1 RPLL
PLL_CTL0[7:6]
Lock CPLL2
PLL_INT Detect

Div N
PLL_CTL0[3:2]

{PLL_DIV_H, PLL_DIV_L}

Figure 57. Phase-Locked Loop Block Diagram

PLL includes seven main blocks as listed below:

• Phase Frequency Detector
• Charge Pump
• Voltage Controlled Oscillator
• Loop Filter
• Divider
• MUX/CLK Sync
• Lock Detect

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Phase Frequency Detector

The Phase Frequency Detector (PFD) is a digital block. The two inputs are the reference
clock (XTAL oscillator; see On-Chip Oscillators on page 335) and the PLL divider output.
The two outputs drive the internal charge pump and represent the error (or difference)
between the falling edges of the PFD inputs.

Charge Pump
The Charge Pump is an analog block that is driven by two digital inputs from the PFD that
control its programmable current sources. The internal current source contains four
programmable values: 1.5 mA, 1 mA, 500 µA, and 100 µA. These values are selected by
PLL_CTRL1[7:6]. The selected current drive is sinked/sourced onto the loop-filter node
according to the error (or difference) between the falling edges of the PFD inputs. Ideally,
when the PLL is locked, there are no errors (error = 0) and no current is sourced/sinked
onto the loop-filter node.

Voltage Controlled Oscillator

The Voltage Controlled Oscillator (VCO) is an analog block that exhibits an output
frequency proportional to its input voltage. The VCO input is driven from the charge
pump and filtered via the off-chip loop filter.

Loop Filter
The Loop Filter comprises off-chip passive components (usually 1 resistor and 2
capacitors) that filter/integrate charge from the internal charge pump. The filtered node
also drives the VCO input, which creates a proportional frequency output. When PLL is
not used, the Loop Filter pin must not be connected.

Divider
The Divider is a digital, programmable downcounter. The divider input is driven by the
VCO. The divider output drives the PFD. The function of the Divider is to divide the
frequency of its input signal by a programmable factor N and supply the result in its
output.

MUX/CLK Sync
The MUX/CLK Sync is a digital, software-controllable multiplexer that selects between
PLL or the XTAL oscillator as the system clock (SCLK). A PLL source is selected only
after the PLL is locked (via the lock detect block) to allow glitch-free clock switching.

Lock Detect
The Lock Detect digital block analyzes the PFD output for a locked condition. The PLL
block of the eZ80F91 device is considered locked when the error (or difference) between
the reference clock and divided-down VCO is less than the minimum timing lock criteria

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for the number of consecutive reference clock cycles. The lock criteria is selected in the
PLL Control Register, PLL_CTL0[LDS_CTL]. When the locked condition is met, this
block outputs a logic High signal (lock) that interrupts the CPU.

PLL Normal Operation

By default (after system reset) the PLL is disabled and SCLK = XTAL oscillator. Ensuring
proper loop filter, supply voltages and external oscillator are correctly configured, the PLL
is enabled. The SCLK/Timer cannot choose the PLL as its source until the PLL is locked,
as determined by the lock detect block. By forcing the PLL to be locked prior to enabling
the PLL as a SCLK/Timer source, it is assured to be stable and accurate.
Figure 58 displays the programming flow for normal PLL operation.

POR/System
Reset

Execute instructions with

SCLK = XTAL Oscillator

Program:
{PLL Divider}
PLL_DIV_L then PLL_DIV_H
{Charge Pump & Lock criteria}
PLL_CTL0

Enable:
{Interrupts & PLL}
PLL_CTL1

Upon Lock Interrupt:

Set SCLK MUX to PLL (PLL_CTL0)
Disable Lock Interrupt Mask
(PLL_CTL1)

Execute Application Code

Figure 58. Normal PLL Programming Flow

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Power Requirement to the Phase-Locked Loop Function

Regardless of whether or not you chooses to use the PLL module block as a clock source
for the eZ80F91 device, the PLL_VDD (pin 87) must be connected to a VDD supply and
the PLL_VSS (pin 84) must be connected to a VSS supply for proper operation of the
eZ80F91 using any system clock source.

PLL Registers
PLL Divider Control Register—Low and High Bytes
This register is designed such that the 11 bit divider value is loaded into the divider mod-
ule whenever the PLL_DIV_H register is written. Therefore, the procedure must be to
load the PLL_DIV_L register, followed by the PLL_DIV_H register, for the divider to
receive the appropriate value.
The divider is designed such that any divider value less than two is ignored; a value of two
is used in its place.
The LSB of PLL divider N is set via the corresponding bits in the PLL_DIV_L register.
See Table 152 and Table 153 on page 269.
Note: The PLL divider register are written only when the PLL is disabled. A read-back of the
PLL Divider registers returns 0.

Table 152. PLL Divider Register—Low Bytes (PLL_DIV_L = 005Ch)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 1 0

CPU Access W W W W W W W W
Note: W = Write only.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the Low byte of the 11 bit PLL divider
PLL_DIV_L value. The complete PLL divider value is returned by
{PLL_DIV_H, PLL_DIV_L}.

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Table 153. PLL Divider Register—High Bytes (PLL_DIV_H = 005Dh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access W W W W W W W W
Note: R = Read only; R/W = Read/Write.

Bit
Position Value Description
[7:3] 00h Reserved
[2:0] 0h–7h These bits represent the High byte of the 11 bit PLL divider
PLL_DIV_H value. The complete PLL divider value is returned by
{PLL_DIV_H, PLL_DIV_L}.

PLL Control Register 0

The charge pump program, lock detect sensitivity, and system clock source selections are
set using this register. A brief description of each of these PLL Control Register 0 attri-
butes is listed below, and further listed in Table 154.

Charge Pump Program (CHRP_CTL)—Selects one of four values of charge pump

current.

Lock Detect Sensitivity (LDS_CTL)—Determines the lock criteria for the PLL.

System Clock Source (CLK_MUX)—Selects the system clock source from a choice of
the external crystal oscillator (XTAL), PLL, or Real-Time Clock crystal oscillator.

Table 154. PLL Control Register 0 (PLL_CTL0 = 005Eh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R R R/W R/W R/W R/W

Note: R = Read Only; R/W = Read/Write.

Bit
Position Value Description
[7:6] 00 Charge pump current = 100 µA
CHRP_CTL1
01 Charge pump current = 500 µA
10 Charge pump current = 1.0 mA
11 Charge pump current = 1.5 mA

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Bit
Position Value Description
[5:4] 00 Reserved
[3:2] 00 Lock criteria—8 consecutive cycles of 20 ns
LDS_CTL1
01 Lock criteria—16 consecutive cycles of 20 ns
10 Lock criteria—8 consecutive cycles of 400 ns
11 Lock criteria—16 consecutive cycles of 400 ns
[1:0] 00 System clock source is the external crystal oscillator
CLK_MUX
01 System clock source is the PLL2
10 System clock source is the Real-Time Clock crystal oscillator
11 Reserved (previous select is preserved)
Notes
1. Bits are programmed only when the PLL is disabled. The PLL is disabled when PLL_CTL1 bit
0 is equal to 0.
2. PLL cannot be selected when disabled or out of lock.

PLL Control Register 1

The PLL is enabled using this register. PLL lock-detect status, the PLL interrupt signals
and the PLL interrupt enables are accessed via this register. A brief description of each of
these PLL Control Register 1 attributes is listed below, and further listed in Table 155 on
page 271.

Lock Status (LCK_STATUS)—The current lock bit out of the PLL is synchronized and
read via this bit.

Interrupt Lock (INT_LOCK)—This signal feeds the interrupt line out of the CLKGEN
module and indicates that a rising edge on the lock signal out of the PLL has been
observed.

Interrupt Unlock (INT_UNLOCK)—This signal feeds the interrupt line out of the clkgen
module and indicates that a falling edge on the lock signal out of the PLL has been
observed.

Interrupt Lock Enable (INT_LOCK_EN)—This signal enables the interrupt lock bit.

Interrupt Unlock Enable (INT_UNLOCK_EN)—This signal enables the interrupt unlock

bit.

PLL Enable (PLL_ENABLE)—Enables/disables the PLL.

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.Table 155. PLL Control Register 1 (PLL_CTL1 = 005Fh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R/W R/W R/W R/W R/W

Note: R = Read Only; R/W = Read/Write.

Bit
Position Value Description
[7:6] 00 Reserved.
5 0 PLL is currently out of lock.
LCK_STATUS
1 PLL is currently locked.
4 0 Lock signal from PLL has not risen since last time register was
INT_LOCK read.
1 Interrupt generated when PLL enters LOCK mode. Held until
register is read.
3 0 Lock signal from PLL has not fallen since last time register was
INT_UNLOCK read.
1 Interrupt generated when PLL goes out of lock. Held until
register is read.
2 0 Interrupt generation for PLL locked condition (Bit 4) is disabled.
INT_LOCK_EN
1 Interrupt generation for PLL locked condition is enabled.
1 0 Interrupt generation for PLL unlocked condition (Bit 3) is
INT_UNLOCK_ disabled.
EN
1 Interrupt generation for PLL unlocked condition is enabled.
0 0 PLL is disabled.1
PLL_ENABLE
1 PLL is enabled.
Note
1. PLL cannot be disabled if the CLK_MUX bit of PLL_CTL0[1:0] is set to 01, because the PLL is
selected as the clock source.

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PLL Characteristics
The operating and testing characteristics for the PLL are listed in Table 156.
Note: Not all conditions are tested in production test. The values in Table 156 are for design and
characterization only.

Table 156. PLL Characteristics

Symbol Parameter Test Condition Min Typ Max Units

IoHCP_OUT High level output current for 3.0 < VDD < 3.6 –0.86 –1.50 –2.13 mA
CP_OUT pin (programmed 0.6 < PD_OUT < VDD – 0.6
value ± 42%) PLL_CTL0[7:6] = 11
IoLCP_OUT Low level output current for 3.0 < VDD <3.6 0.86 1.50 2.13 mA
CP_OUT pin (programmed 0.6 < PD_OUT < VDD – 0.6
value ± 42%) PLL_CTL0[7:6] = 11
IoHCP_OUT High level output current for 3.0 < VDD <3.6 –0.42 –1.0 –1.42 mA
CP_OUT pin (programmed 0.6 < PD_OUT < VDD – 0.6
value ± 42%) PLL_CTL0[7:6] = 10
IoLCP_OUT Low level output current for 3.0 < VDD <3.6 0.42 1.0 1.42 mA
CP_OUT pin (programmed 0.6 < PD_OUT <VDD – 0.6
value ± 42%) PLL_CTL0[7:6] = 10
IoHCP_OUT High level output current for 3.0 < VDD <3.6 –210 –500 –710 µA
CP_OUT pin (programmed 0.6 < PD_OUT <VDD – 0.6
value ± 42%) PLL_CTL0[7:6] = 01
IoLCP_OUT Low level output current for 3.0 < VDD <3.6 210 500 710 µA
CP_OUT pin (programmed 0.6 < PD_OUT <VDD – 0.6
value ± 42%) PLL_CTL0[7:6] = 01
IoHCP_OUT High level output current for 3.0 < VDD <3.6 –42 –100 –142 µA
CP_OUT pin (programmed 0.6 < PD_OUT <VDD – 0.6
value ± 42%) PLL_CTL0[7:6] = 00
IoLCP_OUT Low level output current for 3.0 < VDD <3.6 42 100 142 µA
CP_OUT pin (programmed 0.6 < PD_OUT <VDD – 0.6
value ± 42%) PLL_CTL0[7:6] = 00
Match IOHCP_OUT–IOLCP_OUT 3.0 < VDD <3.6 –15 +15 %
current match 0.6 < CP_OUT <VDD – 0.6
PLL_CTL0[7:6] = XX
ILCP_OUT Tristate leakage on CP_OUT CP_OUT tristated –1 1 µA
output pin
Fosc Crystal oscillator frequency PLL_CTL0[5:4] = 01 1M 10 M Hz

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Table 156. PLL Characteristics (Continued)

Symbol Parameter Test Condition Min Typ Max Units

Fvco VCO frequency Recommended operating 50 MHz
conditions
Gvco VCO Gain Recommended operating 36 120 MHz/
conditions V
D1 SCLK Duty Cycle from PLL or Recommended operating 45 50 55 %
XTALOSC source conditions
T1A PLL Clock Jitter FVCO = 50 MHz. XTALOSC 350 500 ps
= 10 MHz
Lock2 PLL Lock-Time FVCO = 50 MHz. XTALOSC s
= 3.579 MHz
Cpll1 = 220 pF, Rpll = 499 ¾,
Cpll2 = 0.056 µF
IoH1 High-level Output Current for VoH = VDD–0.4 V –0.3 mA
(XTL) XTAL2 pin PLL_CTL0[5:4] = 01
IoL1 Low-level Output Current for VoL = 0.4 V 0.6 mA
(XTL) XTAL2 pin PLL_CTL0[5:4] = 01
IoH2 High-level Output Current for VoH = VDD–0.4 V mA
(XTL) XTAL2 pin PLL_CTL0[5:4] = 11
IoL2 Low-level Output Current for VoL = 0.4 V mA
(XTL) XTAL2 pin PLL_CTL0[5:4] = 11
VPP3M Peak-to-peak voltage under FOSC = 3.579 MHz V
(XTL) oscillator conditions for Cx1 = 10 pF
XTAL2 pin Cx2 = 10 pF
VPP10M Peak-to-peak voltage under FOSC = 10 MHz V
(XTL) oscillator conditions for Cx1 = 10 pF
XTAL2 pin Cx2 = 10 pF
Cxtal1 Capacitance measured from T = 25 ºC pF
(package XTAL1 pin to GND
type)
Cxtal2 Capacitance measured from T = 25 ºC pF
(package XTAL2 pin to GND
type)
Cloop Capacitance measured from T = 25 ºC pF
(package loop filter pin to GND
type)

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eZ80® CPU Instruction Set

Table 157 through Table 166 on page 278 lists the CPU instructions available for use with
the eZ80F91 device. The instructions are grouped by class. For more information, refer to
eZ80® CPU User Manual (UM0077).

Table 157. Arithmetic Instructions

Mnemonic Instruction
ADC Add with Carry
ADD Add without Carry
CP Compare with Accumulator
DAA Decimal Adjust Accumulator
DEC Decrement
INC Increment
MLT Multiply
NEG Negate Accumulator
SBC Subtract with Carry
SUB Subtract without Carry

Table 158. Bit Manipulation Instructions

Mnemonic Instruction
BIT Bit Test
RES Reset Bit
SET Set Bit

Table 159. Block Transfer and Compare Instructions

Mnemonic Instruction
CPD (CPDR) Compare and Decrement (with Repeat)
CPI (CPIR) Compare and Increment (with Repeat)
LDD (LDDR) Load and Decrement (with Repeat)
LDI (LDIR) Load and Increment (with Repeat)

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Table 160. Exchange Instructions

Mnemonic Instruction
EX Exchange registers
EXX Exchange CPU Multibyte register banks

Table 161. Input/Output Instructions

Mnemonic Instruction
IN Input from I/O
IN0 Input from I/O on Page 0
IND (INDR) Input from I/O and Decrement (with Repeat)
INDRX Input from I/O and Decrement Memory Address with Stationary
I/O Address
IND2 (IND2R) Input from I/O and Decrement (with Repeat)
INDM (INDMR) Input from I/O and Decrement (with Repeat)
INI (INIR) Input from I/O and Increment (with Repeat)
INIRX Input from I/O and Increment Memory Address with Stationary
I/O Address
INI2 (INI2R) Input from I/O and Increment (with Repeat)
INIM (INIMR) Input from I/O and Increment (with Repeat)
OTDM (OTDMR) Output to I/O and Decrement (with Repeat)
OTDRX Output to I/O and Decrement Memory Address with Stationary
I/O Address
OTIM (OTIMR) Output to I/O and Increment (with Repeat)
OTIRX Output to I/O and Increment Memory Address with Stationary
I/O Address
OUT Output to I/O
OUT0 Output to I/0 on Page 0
OUTD (OTDR) Output to I/O and Decrement (with Repeat)
OUTD2 (OTD2R) Output to I/O and Decrement (with Repeat)
OUTI (OTIR) Output to I/O and Increment (with Repeat)

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Table 161. Input/Output Instructions (Continued)

Mnemonic Instruction
OUTI2 (OTI2R) Output to I/O and Increment (with Repeat)
TSTIO Test I/O

Table 162. Load Instructions

Mnemonic Instruction
LD Load
LEA Load Effective Address
PEA Push Effective Address
POP Pop
PUSH Push

Table 163. Logical Instructions

Mnemonic Instruction
AND Logical AND
CPL Complement Accumulator
OR Logical OR
TST Test Accumulator
XOR Logical Exclusive OR

Table 164. Processor Control Instructions

Mnemonic Instruction
CCF Complement Carry Flag
DI Disable Interrupts
EI Enable Interrupts
HALT Halt
IM Interrupt Mode
NOP No Operation

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Table 164. Processor Control Instructions (Continued)

Mnemonic Instruction
RSMIX Reset Mixed-Memory Mode Flag
SCF Set Carry Flag
SLP Sleep
STMIX Set Mixed-Memory Mode Flag

Table 165. Program Control Instructions

Mnemonic Instruction
CALL Call Subroutine
CALL cc Conditional Call Subroutine
DJNZ Decrement and Jump if Nonzero
JP Jump
JP cc Conditional Jump
JR Jump Relative
JR cc Conditional Jump Relative
RET Return
RET cc Conditional Return
RETI Return from Interrupt
RETN Return from Nonmaskable interrupt
RST Restart

Table 166. Rotate and Shift Instructions

Mnemonic Instruction
RL Rotate Left
RLA Rotate Left–Accumulator
RLC Rotate Left Circular
RLCA Rotate Left Circular–Accumulator
RLD Rotate Left Decimal
RR Rotate Right

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Table 166. Rotate and Shift Instructions (Continued)

Mnemonic Instruction
RRA Rotate Right–Accumulator
RRC Rotate Right Circular
RRCA Rotate Right Circular–Accumulator
RRD Rotate Right Decimal
SLA Shift Left Arithmetic
SRA Shift Right Arithmetic
SRL Shift Right Logical

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Opcode Map
Table 167 through Table 173 on page 286 list the hex values for each of the eZ80® instruc-
tions.
Table 167. Opcode Map—First Opcode

Legend
Lower Opcode Nibble
Upper
Opcode 4
Nibble AND
A Mnemonic
A,H
First Operand Second Operand
Lower Nibble (Hex)
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 NOP LD LD INC INC DEC LD RLCA EX ADD LD DEC INC DEC LD RRCA
BC, (BC),A BC B B B,n AF,AF’ HL,BC A,(BC) BC C C C,n
Mmn
1 DJNZ LD LD INC INC DEC LD RLA JR ADD LD DEC INC DEC LD RRA
d DE, (DE),A DE D D D,n d HL,DE A,(DE) DE E E E,n
Mmn
2 JR LD LD INC INC DEC LD DAA JR ADD LD DEC INC DEC LD CPL
NZ,d HL, (Mmn), HL H H H,n Z,d HL,HL HL, HL L L L,n
Mmn HL (Mmn)
3 JR LD LD INC INC DEC LD SCF JR ADD LD DEC INC DEC LD CCF
NC,d SP, (Mmn), SP (HL) (HL) (HL),n CF,d HL,SP A, SP A A A,n
Mmn A (Mmn)
4 .SIS LD LD LD LD LD LD LD LD .LIS LD LD LD LD LD LD
suffix B,C B,D B,E B,H B,L B,(HL) B,A C,B suffix C,D C,E C,H C,L C,(HL) C,A
5 LD LD .SIL LD LD LD LD LD LD LD LD .LIL LD LD LD LD
D,B D,C suffix D,E D,H D,L D,(HL) D,A E,B E,C E,D suffix E,H E,L E,(HL) E,A
6 LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD
H,B H,C H,D H,E H,H H,L H,(HL) H,A L,B L,C L,D L,E L,H L,L L,(HL) L,A
Upper Nibble (Hex)

7 LD LD LD LD LD LD HALT LD LD LD LD LD LD LD LD LD
(HL),B (HL),C (HL),D (HL),E (HL),H (HL),L (HL),A A,B A,C A,D A,E A,H A,L A,(HL) A,A
8 ADD ADD ADD ADD ADD ADD ADD ADD ADC ADC ADC ADC ADC ADC ADC ADC
A,B A,C A,D A,E A,H A,L A,(HL) A,A A,B A,C A,D A,E A,H A,L A,(HL) A,A
9 SUB SUB SUB SUB SUB SUB SUB SUB SBC SBC SBC SBC SBC SBC SBC SBC
A,B A,C A,D A,E A,H A,L A,(HL) A,A A,B A,C A,D A,E A,H A,L A,(HL) A,A
A AND AND AND AND AND AND AND AND XOR XOR XOR XOR XOR XOR XOR XOR
A,B A,C A,D A,E A,H A,L A,(HL) A,A A,B A,C A,D A,E A,H A,L A,(HL) A,A
B OR OR OR OR OR OR OR OR CP CP CP CP CP CP CP CP
A,B A,C A,D A,E A,H A,L A,(HL) A,A A,B A,C A,D A,E A,H A,L A,(HL) A,A
C RET POP JP JP CALL PUSH ADD RST RET RET JP See CALL CALL ADC RST
NZ BC NZ, Mmn NZ, BC A,n 00h Z Z, Z, Mmn A,n 08h
Mmn Mmn Mmn
Table Mmn
168
D RET POP JP OUT CALL PUSH SUB RST RET EXX JP IN CALL See SBC RST
NC DE NC, (n),A NC, DE A,n 10h CF CF, A,(n) CF, A,n 18h
Mmn Mmn Mmn Mmn
Table
169
E RET POP JP EX CALL PUSH AND RST RET JP JP EX CALL See XOR RST
PO HL PO, (SP),HL PO, HL A,n 20h PE (HL) PE, DE,HL PE, Table A,n 28h
Mmn Mmn Mmn Mmn
170
F RET POP JP DI CALL PUSH OR RST RET LD JP EI CALL See CP RST
P AF P, P, AF A,n 30h M SP,HL M, M, Table A,n 38h
Mmn Mmn Mmn Mmn
171

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Table 167. Opcode Map—First Opcode (Continued)

Note: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.

Table 168. Opcode Map—Second Opcode after 0CBh

Legend
Lower Nibble of 2nd Opcode
Upper
Nibble 4
of Second
Opcode A RES Mnemonic
4,H
First Operand Second Operand
Lower Nibble (Hex)
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 RLC RLC RLC RLC RLC RLC RLC RLC RRC RRC RRC RRC RRC RRC RRC RRC
B C D E H L (HL) A B C D E H L (HL) A
1 RL RL RL RL RL RL RL RL RR RR RR RR RR RR RR RR
B C D E H L (HL) A B C D E H L (HL) A
2 SLA SLA SLA SLA SLA SLA SLA SLA SRA SRA SRA SRA SRA SRA SRA SRA
B C D E H L (HL) A B C D E H L (HL) A
3 SRL SRL SRL SRL SRL SRL SRL SRL
B C D E H L (HL) A
4 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
0,B 0,C 0,D 0,E 0,H 0,L 0,(HL) 0,A 1,B 1,C 1,D 1,E 1,H 1,L 1,(HL) 1,A
5 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
2,B 2,C 2,D 2,E 2,H 2,L 2,(HL) 2,A 3,B 3,C 3,D 3,E 3,H 3,L 3,(HL) 3,A
6 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
4,B 4,C 4,D 4,E 4,H 4,L 4,(HL) 4,A 5,B 5,C 5,D 5,E 5,H 5,L 5,(HL) 5,A
Upper Nibble (Hex)

7 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
6,B 6,C 6,D 6,E 6,H 6,L 6,(HL) 6,A 7,B 7,C 7,D 7,E 7,H 7,L 7,(HL) 7,A
8 RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES
0,B 0,C 0,D 0,E 0,H 0,L 0,(HL) 0,A 1,B 1,C 1,D 1,E 1,H 1,L 1,(HL) 1,A
9 RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES
2,B 2,C 2,D 2,E 2,H 2,L 2,(HL) 2,A 3,B 3,C 3,D 3,E 3,H 3,L 3,(HL) 3,A
A RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES
4,B 4,C 4,D 4,E 4,H 4,L 4,(HL) 4,A 5,B 5,C 5,D 5,E 5,H 5,L 5,(HL) 5,A
B RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES
6,B 6,C 6,D 6,E 6,H 6,L 6,(HL) 6,A 7,B 7,C 7,D 7,E 7,H 7,L 7,(HL) 7,A
C SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET
0,B 0,C 0,D 0,E 0,H 0,L 0,(HL) 0,A 1,B 1,C 1,D 1,E 1,H 1,L 1,(HL) 1,A
D SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET
2,B 2,C 2,D 2,E 2,H 2,L 2,(HL) 2,A 3,B 3,C 3,D 3,E 3,H 3,L 3,(HL) 3,A
E SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET
4,B 4,C 4,D 4,E 4,H 4,L 4,(HL) 4,A 5,B 5,C 5,D 5,E 5,H 5,L 5,(HL) 5,A
F SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET
6,B 6,C 6,D 6,E 6,H 6,L 6,(HL) 6,A 7,B 7,C 7,D 7,E 7,H 7,L 7,(HL) 7,A
Note: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.

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Table 169. Opcode Map—Second Opcode After 0DDh

Legend
Lower Nibble of 2nd Opcode

Upper
Nibble 9
of Second
Opcode F LD Mnemonic
SP,IX
First Operand Second Operand
Lower Nibble (Hex)
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 LD BC, ADD LD
(IX+d) IX,BC (IX+d),
BC
1 LD DE, ADD LD
(IX+d) IX,DE (IX+d),
DE
2 LD LD INC INC DEC LD LD HL, ADD LD DEC INC DEC LD LD
IX, (Mmn), IX IXH IXH IXH,n (IX+d) IX,IX IX, IX IXL IXL IXL,n (IX+d),
Mmn IX (Mmn) HL
3 LD IY, INC DEC LD (IX LD IX, ADD LD LD
(IX+d) (IX+d) (IX+d) +d),n (IX+d) IX,SP (IX+d), (IX+d),
IY IX
4 LD LD LD B, LD LD LD C,
B,IXH B,IXL (IX+d) C,IXH C,IXL (IX+d)
5 LD LD LD D, LD LD LD E,
D,IXH D,IXL (IX+d) E,IXH E,IXL (IX+d)
Upper Nibble (Hex)

6 LD LD LD LD LD LD LD H, LD LD LD LD LD LD LD LD L, LD
IXH,B IXH,C IXH,D IXH,E IXH,IXH IXH,IXL (IX+d) IXH,A IXL,B IXL,C IXL,D IXL,E IXL,IXH IXL,IXL (IX+d) IXL,A
7 LD LD LD LD LD LD LD LD LD LD A,
(IX+d),B (IX+d),C (IX+d),D (IX+d),E (IX+d),H (IX+d),L (IX+d),A A,IXH A,IXL (IX+d)
8 ADD ADD ADD A, ADC ADC ADC A,
A,IXH A,IXL (IX+d) A,IXH A,IXL (IX+d)
9 SUB SUB SUB A, SBC SBC SBC A,
A,IXH A,IXL (IX+d) A,IXH A,IXL (IX+d)
A AND AND AND A, XOR XOR XOR A,
A,IXH A,IXL (IX+d) A,IXH A,IXL (IX+d)
B OR OR OR A, CP CP CP A,
A,IXH A,IXL (IX+d) A,IXH A,IXL (IX+d)
C Table
172
D

E POP EX PUSH JP
IX (SP),IX IX (IX)
F LD
SP,IX
Note: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.

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Table 170. Opcode Map—Second Opcode After 0EDh

Legend
Lower Nibble of 2nd Opcode

Upper
Nibble 2
of Second
Opcode 4 SBC Mnemonic
HL,BC
First Operand Second Operand
Lower Nibble (Hex)
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 IN0 OUT0 LEA LEA TST LD BC, IN0 OUT0 TST LD
B,(n) (n),B BC, BC, A,B (HL) C,(n) (n),C A,C (HL),
IX+d IY+d BC
1 IN0 OUT0 LEA LEA TST LD DE, IN0 OUT0 TST LD(HL),
D,(n) (n),D DE, DE, A,D (HL) E,(n) (n),E A,E DE
IX+d IY+d
2 IN0 OUT0 LEA HL LEA HL TST LD HL, IN0 OUT0 TST LD
H,(n) (n),H ,IX+d ,IY+d A,H (HL) L,(n) (n),L A,L (HL),
HL
3 LD IY, LEA IX LEA IY TST LD IX, IN0 OUT0 TST LD LD
(HL) ,IX+d ,IY+d A,(HL) (HL) A,(n) (n),A A,A (HL),IY (HL),
IX
4 IN OUT SBC LD NEG RETN IM 0 LD IN OUT ADC LD MLT RETI LD
B,(BC) (BC),B HL,BC (Mmn), I,A C,(C) (C),C HL,BC BC, BC R,A
BC (Mmn)
5 IN OUT SBC LD LEA IX, LEA IY, IM 1 LD IN OUT ADC LD MLT IM 2 LD
D,(BC) (BC),D HL,DE (Mmn), IY+d IX+d A,I E,(C) (C),E HL,DE DE, DE A,R
Upper Nibble (Hex)

DE (Mmn)
6 IBN OUT SBC LD TST PEA PEA RRD IN OUT ADC LD MLT LD LD RLD
H,(C) (BC),H HL,HL (Mmn), A,n IX+d IY+d L,(C) (C),L HL,HL HL, HL MB,A A,MB
HL (Mmn)
7 SBC LD TSTIO SLP IN OUT ADC LD MLT STMIX RSMIX
HL,SP (Mmn), n A,(C) (C),A HL,SP SP, SP
SP (Mmn)
8 INIM OTIM INI2 INDM OTDM IND2

9 INIMR OTIMR INI2R INDMR OTDMR IND2R

A LDI CPI INI OUTI OUTI2 LDD CPD IND OUTD OUTD2

B LDIR CPIR INIR OTIR OTI2R LDDR CPDR INDR OTDR OTD2R

C INIRX OTIRX LD INDRX OTDRX

I,HL
D LD
HL,I
E

Note: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.

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Table 171. Opcode Map—Second Opcode After 0FDh

Legend Lower Nibble of 2nd Opcode

Upper
Nibble 9
of Second
Opcode F LD Mnemonic
SP,IY
First Operand Second Operand
Lower Nibble (Hex)
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 LD BC, ADD LD (IY
(IY+d) IY,BC +d),BC
1 LD DE, ADD LD (IY
(IY+d) IY,DE +d),DE
2 LD LD INC INC DEC LD LD HL, ADD LD DEC INC DEC LD LD (IY
IY,Mmn (Mmn),I IY IYH IYH IYH,n (IY+d) IY,IY IY, IY IYL IYL IYL,n +d),HL
Y (Mmn)
3 LD IX, INC DEC LD (IY LD IY, ADD LD (IY LD (IY
(IY+d) (IY+d) (IY+d) +d),n (IY+d) IY,SP +d),IX +d),IY
4 LD LD LD B, LD LD LD C,
B,IYH B,IYL (IY+d) C,IYH C,IYL (IY+d)
5 LD LD LD D, LD LD LD E,
D,IYH D,IYL (IY+d) E,IYH E,IYL (IY+d)
6 LD LD LD LD LD LD LD H, LD LD LD LD LD LD LD LD L, LD
Upper Nibble (Hex)

IYH,B IYH,C IYH,D IYH,E IYH,IYH IYH,IYL (IY+d) IYH,A IYL,B IYL,C IYL,D IYL,E IYL,IYH IYL,IYL (IY+d) IYL,A
7 LD (IY LD (IY LD (IY LD (IY LD (IY LD (IY LD (IY LD LD LD A,
+d),B +d),C +d),D +d),E +d),H +d),L +d),A A,IYH A,IYL (IY+d)
8 ADD ADD ADD A, ADC ADC ADC A,
A,IYH A,IYL (IY+d) A,IYH A,IYL (IY+d)
9 SUB SUB SUB A, SBC SBC SBC A,
A,IYH A,IYL (IY+d) A,IYH A,IYL (IY+d)
A AND AND AND A, XOR XOR XOR A,
A,IYH A,IYL (IY+d) A,IYH A,IYL (IY+d)
B OR OR OR A, CP CP CP A,
A,IYH A,IYL (IY+d) A,IYH A,IYL (IY+d)
C Table
173
D

E POP EX PUSH JP
IY (SP),IY IY (IY)
F LD
SP,IY
Note: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.

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Table 172. Opcode Map—Fourth Byte After 0DDh, 0CBh, and dd

Legend
Lower Nibble of 4th Byte

Upper
Nibble 6
of Fourth BIT
Byte 4 0,(IX+d) Mnemonic

First Operand Second Operand

Lower Nibble (Hex)
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 RLC RRC
(IX+d) (IX+d)
1 RL RR
(IX+d) (IX+d)
2 SLA SRA
(IX+d) (IX+d)
3 SRL
(IX+d)
4 BIT 0, BIT 1,
(IX+d) (IX+d)
5 BIT 2, BIT 3,
(IX+d) (IX+d)
6 BIT 4, BIT 5,
Upper Nibble (Hex)

(IX+d) (IX+d)
7 BIT 6, BIT 7,
(IX+d) (IX+d)
8 RES 0, RES 1,
(IX+d) (IX+d)
9 RES 2, RES 3,
(IX+d) (IX+d)
A RES 4, RES 5,
(IX+d) (IX+d)
B RES 6, RES 7,
(IX+d) (IX+d)
C SET 0, SET 1,
(IX+d) (IX+d)
D SET 2, SET 3,
(IX+d) (IX+d)
E SET 4, SET 5,
(IX+d) (IX+d)
F SET 6, SET 7,
(IX+d) (IX+d)
Note: d = 8-bit two’s-complement displacement

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Table 173. Opcode Map—Fourth Byte After 0FDh, 0CBh, and dd

Legend Lower Nibble of 4th Byte

Upper
Nibble 6
of Fourth
Byte 4 BIT Mnemonic
0,(IY+d)
First Operand Second Operand
Lower Nibble (Hex)
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 RLC RRC
(IY+d) (IY+d)
1 RL RR
(IY+d) (IY+d)
2 SLA SRA
(IY+d) (IY+d)
3 SRL
(IY+d)
4 BIT 0, BIT 1,
(IY+d) (IY+d)
5 BIT 2, BIT 3,
(IY+d) (IY+d)
6 BIT 4, BIT 5,
Upper Nibble (Hex)

(IY+d) (IY+d)
7 BIT 6, BIT 7,
(IY+d) (IY+d)
8 RES 0, RES 1,
(IY+d) (IY+d)
9 RES 2, RES 3,
(IY+d) (IY+d)
A RES 4, RES 5,
(IY+d) (IY+d)
B RES 6, RES 7,
(IY+d) (IY+d)
C SET 0, SET 1,
(IY+d) (IY+d)
D SET 2, SET 3,
(IY+d) (IY+d)
E SET 4, SET 5,
(IY+d) (IY+d)
F SET 6, SET 7,
(IY+d) (IY+d)
Note: d = 8-bit two’s-complement displacement

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Ethernet Media Access Controller

The Ethernet Media Access Controller (EMAC) is a full-function 10/100 Mbps media
access control module with a Media-Independent Interface (MII). When communicating
with an external PHY device, the eZ80F91 MCU uses the MII to gain access to the
Ethernet network.
Figure 59 displays the EMAC block diagram.

MDIO
MDC TxDMA
TxD
TxCLK
TxFIFO
TxER
Media Access Controller

TxEN

Memory
COL

Arbiter
CRS

MII Interface
RxD
RxCLK RxD
RxDV RxD/CTRL
RxER
RxFIFO
Accept
CTRL RxDMA
Reject

Figure 59. EMAC Block Diagram

Note: For additional information about the Ethernet protocol and using it with the eZ80F91
MCU, refer to the IEEE 802.3 specification, 1998 edition, Section 22. The eZ80F91 MCU
supports the IEEE 802.3 protocol with the following exception:

The eZ80F91 MCU does not support the Giga Media Independent Interface (GMII)
referred to in the following sections of the IEEE 802.3 1998 version: section 22.1.5, sec-
tion 22.2.4, section 22.2.4.1.2, section 22.2.4.1.5, and section 22.2.4.1.6.

The EMAC is used for many different applications, including network interface, ethernet
switching, and test equipment designs. The EMAC includes the following blocks:
• Central clock and reset module (not shown in the block diagram).
• Host memory interface and transmit/receiver arbiter.

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• FIFO buffer and DMA control blocks for transmit and receive.
• 802.3x media access control block.
• MII interface management.
The media access control block implements 802.3x flow control functions for both trans-
mit and receive.
The MII management module provides a two-wire control/status path to the MII PHY.
Read and Write communication to and from registers within the PHY is accomplished via
the host interface.
Note: MII PHY is a Physical Layer transceiver device; PHY does not refer to the eZ80F91 sys-
tem clock output pin, PHI.

The MII management module provides a two-wire control/status path to the MII. Read
and Write communication to and from registers within the PHY is accomplished via the
host interface.

EMAC Functional Description

The EMAC block implements memory, arbiter, and transmit and receive direct memory
access functions, and offers four communication modes: HALF-DUPLEX, FULL-
DUPLEX, NIBBLE, and ENDEC. In HALF-DUPLEX and FULL-DUPLEX modes,
throughput occurs at both 10 Mbps and 100 Mbps speeds. Throughput in ENDEC and
NIBBLE modes occurs at 10 Mbps. A brief description of these four modes are as follows:
10/100 Mbps HALF-DUPLEX Mode— In this mode, data are transferred only in one
direction at a time; that is, one can either transmit or receive, but both cannot occur
simultaneously.
10/100 Mbps FULL-DUPLEX Mode— In this mode, data are transmitted and received at
the same time.
10 Mbps ENDEC Mode— This mode affects the MII interface between the PHY and the
MAC. In ENDEC mode, the RxCLK and TxCLK clocks are bit clocks instead of the nor-
mal nibble clock. In NIBBLE mode, 4 bits are transferred on each clock. In ENDEC
mode, 1 bit is transferred per clock.
For more information on throughput, see EMAC and the System Clock on page 296.

Memory
EMAC memory is the shared Ethernet memory location of the Transmit and Receive buf-
fers. This memory is broken into two parts: the Tx buffer and the Rx buffer. The Transmit
Lower Boundary Pointer Register, EmacTLBP, is the register that holds the starting
address of the Tx buffer. The Boundary Pointer Register, EmacBP, points to the start of the
Rx buffer (end of Tx buffer + 1). The Receive High Boundary Pointer Register, Emac-

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RHBP, points to the end of the Rx buffer + 1. The Tx and Receive buffers are divided into
packet buffers of either 256, 128, 64, or 32 bytes. These buffer sizes are selected by
EmacBufSize register bits 7 and 6.
The EmacBlksLeft register contains the number of Receive packet buffers remaining in
the Rx buffer. This buffer is used for software flow control. If the Block_Level is nonzero
(bits 5:0 of the EmacBufSize register), hardware flow control is enabled. If in FULL-
DUPLEX mode, the EMAC transmits a pause control frame when the EmacBlksLeft reg-
ister is less than the Block_Level. In HALF-DUPLEX mode, the EMAC continually trans-
mits a nibble pattern of hexadecimal 5’s to jam the channel.
Four pointers are defined for reading and writing the Tx and Rx buffers. The Transmit
Write Pointer, TWP, is a software pointer that points to the next available packet buffer.
The TWP is reset to the value stored in EmacTLBP. The Transmit Read Pointer, TRP, is a
hardware pointer in the Transmit Direct Memory Access Register, TxDMA, that contains
the address of the next packet to be transmitted. It is automatically reset to the EmacTLBP.
The Receive Write Pointer, RWP, is a hardware pointer in the Receive Direct Memory
Access Register, RxDMA, which contains the storage address of the incoming packet. The
RWP pointer is automatically initialized to the Boundary Pointer registers. The Receive
Read Pointer, RRP, is a software pointer to where the next packet must be read from. The
RRP pointer must be initialized to the Boundary Pointer registers. For the hardware flow
control to function properly, the software must update the hardware RRP (EmacRrp)
pointer whenever the software version is updated. The RxDMA uses RWP and the RRP to
determine how many packet buffers remain in the Rx buffer.

Arbiter
The arbiter controls access to EMAC memory. It prioritizes the requests for memory
access between the CPU, the TxDMA, and the RxDMA. The TxDMA offers two levels of
priority: a high priority when the TxFIFO is less than half full and a Low priority when the
TxFIFO is more than half full. Similarly, the RxDMA offers two levels of priority: a high
priority when the RxFIFO is more than half full and a Low priority when the RxFIFO is
less than half full.
The arbiter determines resolution between the CPU, the RxDMA, and the TxDMA
requests to access EMAC memory. Post writing for CPU Writes results in Zero-Wait-state
write access timing when the CPU assumes the highest priority. CPU Reads require a min-
imum of 1 Wait state and takes more when the CPU does not hold the highest priority. The
CPU Read Wait state is not a user-controllable operation, because it is controlled by the
arbiter. The RxDMA and TxDMA requests are not allowed to occur back-to-back. There-
fore, the maximum throughput rate for the two Direct Memory Access (DMA) ports is 25
Mbps each (one byte every 2 clocks) when the system clock is running at 50 MHz. The
rate is reduced to 20 MBps for a 40 MHz system clock. The arbiter uses the internal WAIT
signal to add Wait states to CPU access when required. See Table 174 on page 290.

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Table 174. Arbiter Priority

Priority Device
Level Serviced Flags
0 RxDMA High RxFIFO > half full (FAF)
1 TxDMA High TxFIFO < half full (FAE)
2 eZ80® CPU
3 RxDMA Low RxFIFO < half full (FAE)
4 TxDMA Low TxFIFO > half full (FAF)

TxDMA
The TxDMA module moves the next packet to be transmitted from EMAC memory into
the TxFIFO. Whenever the polling timer expires, the TxDMA reads the High status byte
from the Tx descriptor table pointed to by the Transmit Read Pointer, TRP. Polling contin-
ues until the High status Read reaches bit 7, when the Emac_Owns ownership semaphore,
bit 15 of the descriptor table (see Table 178 on page 295) is set to 1. The TxDMA then ini-
tializes the packet length counter with the size of the packet from descriptor table bytes 3
and 4. The TxDMA moves the data into the TxFIFO until the packet length counter down-
counts to zero. The TxDMA then waits for Transmission Complete signal to be asserted to
indicate that the packet is sent and that the Transmit status from the EMAC is valid. The
TxDMA updates the descriptor table status and resets the ownership semaphore, bit 15.
Finally, the Tx_DONE_STAT bit of the EMAC Interrupt Status Register is set to 1, the
address field, DMA_Address, is updated from the descriptor table next pointer, NP (see
Figure 62 on page 294). The High byte of the status is read to determine if the next packet
is ready to be transmitted.
While the TxDMA is filling the TxFIFO, it monitors two signals from the Transmit FIFO
State Machine (TxFifoSM) to detect error conditions and to determine if the packet is to
be retransmitted (TxDMA_Retry asserted) or the packet is aborted (TxDMA_Abort
asserted). If the packet is aborted, the TxDMA updates the descriptor status and moves to
the next packet. If the packet is to be retried, the DMA_Address is reset to the start of the
packet, the packet length counter is reloaded from the descriptor table, bytes 3 and 4, and
the packet is moved into the TxFIFO again. When an abort or retry event occurs, the
TxDMA asserts the appropriate signal to reset the TxFIFO Read and Write pointers which
clears out any data that is in the FIFO. The TxFifoSM negates the TxDMA_Abort or
TxDMA_Retry signal(s) or both when the TxFCWP signal is High. This handshaking
maintains synchronization between the TxDMA and the TxFifoSM.

RxDMA
The RxDMA reads the data from the RxFIFO and stores it in the EMAC memory Receive
buffer. When the end of the packet is detected, the RxDMA reads the next two bytes from

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the RxFIFO and writes them into the Rx descriptor status LSB and MSB. The packet-
length counter is stored into the descriptor table’s Packet Length field, and the descriptor
table’s next pointer is written into the Rx descriptor table. Additionally, the
Rx_DONE_STAT bit in the EMAC Interrupt Status Register is set to 1.

Signal Termination
When the EMAC interface is not used, the MII signals must be terminated as listed in
Table 175. Terminated pins are either left unconnected (float) or tied to ground.
MDIO is controlled by the MDC output signal. When the EMAC is not being used, these
two pins are not driven. The RX_DV, RX_ER, and RXD[3:0] inputs are controlled by the
rising edge of the RX_CLK input signal. When RX_CLK is tied to Ground, these pins do
not affect the EMAC. The TX_EN, TX_ER, and TXD[3:0] outputs are controlled by the
rising edge of the TX_CLK input signal. When TX_CLK is tied to Ground, these pins do
not affect the EMAC. The CRS and COL input pins have no relationship to the clock, and
therefore must be placed into nonactive states and tied to Ground.

Table 175. MII Signal Termination When EMAC is Not Used

Termination
Signal Pin Type Direction
MDIO Bidirectional Float
MDC Output pin Float
RX_DV Input pin Float
CRS Input pin Ground
RX_CLK Input pin Ground
RX_ER Input pin Float
RXD[3:0] Input pins Float
COL Input pin Ground
TX_CLK Input pin Ground
TX_EN Output pin Float
TXD[3:0] Output pins Float
TX_ER Output pin Float

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EMAC Interrupts
Eight different sources of interrupts from the EMAC are listed in Table 176.

Table 176. EMAC Interrupts

Interrupt Description
EMAC System Interrupts
Transmit State Machine Error Bit 7 (TxFSMERR_STAT) of the EMAC Interrupt Status Register
(EMAC_ISTAT). A Transmit State Machine Error must not occur.
However, if this bit is set, the entire transmitter module must be
reset.
MIIMGT Done Bit 6 (MGTDONE_STAT) of the Interrupt Status Register
(EMAC_ISTAT). This bit is set when communicating to the PHY
over the MII during a Read or Write operation.
Receive Overrun Bit 2 (Rx_OVR_STAT) of the Interrupt Status Register
(EMAC_ISTAT). If this bit is set, all incoming packets are ignored
until this bit is cleared by software.
EMAC Transmitter Interrupts
Transmit Control Frame Transmit Control Frame = Bit 1 (Tx_CF_STAT) of the Interrupt
Status Register (EMAC_ISTAT). Denotes when control frame
transmission is complete.
Transmit Done Bit 0 (Tx_DONE_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when packet transmission is complete.
EMAC Receiver Interrupts
Receive Packet Bit 5 (Rx_CF_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when packet reception is complete.
Receive Pause Packet Bit 4 (Rx_PCF_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when pause packet reception is
complete.
Receive Done Bit 3 (Rx_DONE_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when packet reception is complete.

EMAC Shared Memory Organization

Internal Ethernet SRAM shares memory with the CPU. This memory is divided into the
Transmit buffer and the Receive buffer by defining three registers, as listed below.
• Transmit Lower Boundary Pointer (TLBP)—this register points to the start of the
Transmit buffer in the internal Ethernet shared memory space.
• Boundary Pointer (BP)—this register points to the start of the Receive buffer.

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• Receive High Boundary Pointer (RHBP)—this register points to the end of the Receive
buffer + 1.

Figure 60 displays the internal Ethernet shared memory.

Upper Memory Address

RHBP
Rx Buffer
BP
Tx Buffer
TLBP

Lower Memory Address

Figure 60. Internal Ethernet Shared Memory

The Transmit and Receive buffers are subdivided into packet buffers of 32, 64, 128, or 256
bytes in size. The packet buffer size is set in bits 7 and 6 of the EmacBufSize register. An
Ethernet packet accommodate multiple packet buffers. First, however, a brief listing of the
contents of a typical Ethernet packet is in order. See Table 177.

Table 177. Ethernet Packet Contents

Byte Range Contents

Bytes 0–5 MAC destination address.
Bytes 6–11 MAC source address.
Bytes 12–13 Length/Type field.
Bytes 14–n MAC Client Data.
Bytes (n+1)–(n+4) Frame Check Sequence.

At the start of each packet is a descriptor table that describes the packet. Each actual
Ethernet packet follows the descriptor table as displayed in Figure 61 on page 294.

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Offset

Ethernet
Packet

0007h
Descriptor
Table
TWP 0000h

Figure 61. Descriptor Table

Note: For an official description of an Ethernet packet, refer to IEEE 802.3 specification, Figure
3-1.

The descriptor table contains three entries: the next pointer (NP), the packet size
(Pkt_Size), and the packet status (Stat), as displayed in Figure 62.

Offset

Stat

0005h

Pkt_Size

0003h

NP

TWP 0000h

Figure 62. Descriptor Table Entries

NP is a 24-bit pointer to the start of the next packet. Pkt_Size contains the number of bytes
of data in the Ethernet packet, including the four CRC bytes, but does not contain the
seven descriptor table bytes. Stat contains the status of the packet. Stat differs for Transmit
and Receive packets. See Table 178 on page 295 and Table 179 on page 295.

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Table 178. Transmit Descriptor Status

Bit Name Description

15 TxOwner 0 = Host (eZ80®) owns, 1 = EMAC owns.
14 TxAbort 1 = Packet aborted (not transmitted).
13 TxBPA 1 = Back pressure applied.
12 TxHuge 1 = Packet size is very large (Pkt_Size > EmacMaxf).
11 TxLOOR 1 = Type/Length field is out of range (larger than 1518 bytes).
10 TxLCError 1 = Type/Length field is not a Type field and it does not match the
actual data byte length of the Ethernet packet. The data byte length is
the number of bytes of data in the Ethernet packet between the Type/
Length field and the FCS.
9 TxCrcError 1 = The packet contains an invalid FCS (CRC). This flag is set when
CRCEN = 0 and the last 4 bytes of the packet are not the valid FCS.
8 TxPktDeferred 1 = Packet is deferred.
7 TxXsDfr 1 = Packet is excessively deferred. (> 6071 nibble times in 100 BaseT
or 24,287 bit times in 10 BaseT).
6 TxFifoUnderRun 1 = TxFIFO experiences underrun. Check the TxAbort bit to see if the
packet is aborted or retried.
5 TxLateCol 1 = A late collision occurs. Collision is detected at a byte count >
EmacCfg2[5:0]. Collisions detected before the byte count reaches
EmacCfg2[5:0] are early collisions and retried.
4 TxMaxCol 1 = The maximum number of collisions occurs. # Collisions >
EmacCfg3[3:0]. These packets are aborted.
[3:0] TxNumberOfCollisions This field contains the number of collisions that occur while transmitting
the packet.

Table 179. Receive Descriptor Status

Bit Name Description

15 RxOK 1 = Packet received intact.
14 RxAlignError 1 = An odd number of nibbles is received.
13 RxCrcError 1 = The CRC (FCS) is in error.

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Table 179. Receive Descriptor Status (Continued)

Bit Name Description

12 RxLongEvent 1 = A Long or Dropped Event occurs. A Long Event is when a packet
over 50,000 bit times occurs. A Dropped Packet occurs if the minimum
interpacket gap is not met, the preamble is not pure, and the
EmacCfg3[PUREP] bit is set, or if a preamble over 11 bytes in length is
detected and the EmacCfg3[LONGP] bit is set to 1.
11 RxPCF 1 = The packet is a pause control frame.
10 RxCF 1 = The packet is a control frame.
9 RxMcPkt 1 = The packet contains a multicast address.
8 RxBcPkt 1 = The packet contains a broadcast address.
7 RxVLAN 1 = The packet is a VLAN packet.
6 RxUOpCode 1 = An unsupported opcode is indicated in the opcode field of the
Ethernet packet.
5 RxLOOR 1 = The Type/Length field is out of range (larger than 1518 bytes).
4 RxLCError 1 = Type/Length field is not a Type field and it does not match the
actual data byte length of the Ethernet packet. The data byte length is
the number of bytes of data in the Ethernet packet between the Type/
Length field and the FCS.
3 RxCodeV 1 = A code violation is detected. The PHY asserts Rx error (RxER).
2 RxCEvent 1 = A carrier event is previously seen. This event is defined as Rx error
RxER = 1, receive data valid (RxDV) = 0 and receive data (RxD) = Eh.
1 RxDvEvent 1 = A receive data (RxDV) event is previously seen. Indicates that the
last Receive event is not long enough to be a valid packet.
0 RxOVR 1 = A Receive overrun occurs in this packet. An overrun occurs when
all of the EMAC Receive buffers are in use and the Receive FIFO is full.
The hardware ignores all incoming packets until the EmacIStat
Register [Rx_Ovr] bit is cleared by the software. There is no indication
as to how many packets are ignored.

EMAC and the System Clock

Effective Ethernet throughput in any given system is dependent upon factors such as sys-
tem clock speed, network protocol overhead, application complexity, and network traffic
conditions at any given moment. The following information provides a general guideline
about the effects of system clock speed on Ethernet operation.
The eZ80F91 MCU's EMAC block performs a synchronous function that is designed to
operate over a wide range of system clock frequencies. To understand its maximum data

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transfer capabilities at certain system operating frequencies, you must first understand the
internal data bus bandwidth that is required under ideal conditions.
For 10 BaseT Ethernet connectivity, the data rate is 10 Mbps, which equates to 1.25 Mbps.
If the eZ80F91 MCU is operating in FULL-DUPLEX mode over 10BaseT, the data rate for
RX data and TX data is 1.25 Mbps. Because raw data transfers at this rate consume a cer-
tain amount of CPU bandwidth, the CPU must support traffic from both directions as well
as operate at a minimum clock frequency of (1.25 + 1.25) * 2 = 5 MHz while transferring
Ethernet packets to and from the physical layer.
Similarly, for 100 BaseT Ethernet, the data rate is 100 Mbps, which equates to 12.5 Mbps.
If the eZ80F91 MCU is operating in FULL-DUPLEX mode over 100 BaseT, the data rate
for RX data and TX data is 12.5 Mbps. Because raw data transfers at this rate consume a
certain amount of CPU bandwidth, the CPU must support traffic from both directions as
well as operate at a minimum clock frequency of (12.5 + 12.5) x 2 = 50 MHz while trans-
ferring Ethernet packets to and from the physical layer. Consequently, 50 MHz is the min-
imum system clock speed that the eZ80® CPU requires to sustain EMAC data transfers
while not including any software overhead or additional eZ80 tasks.
The FIFO functionality of the EMAC operates at any frequency as long as the user appli-
cation avoids overrun and underrun errors via higher-level flow control. Actual applica-
tion requirements will dictate Ethernet modes of operation (FULL-DUPLEX, HALF-
DUPLEX, etc.). Because each user and application is different, it becomes your responsi-
bility to control the data flow with these parameters. Under ideal conditions, the system
clock will operate somewhere between 5 MHz and 50 MHz to handle the EMAC data
rates.

EMAC Operation in HALT Modes

When the CPU is in HALT mode, the eZ80F91 device’s EMAC block cannot be disabled
as other peripherals. Upon receipt of an Ethernet packet, a maskable Receive interrupt is
generated by the EMAC block, just as it would be in a non-halt mode. Accordingly, the
processor wakes up and continues with the user-defined application.

EMAC Registers
After a system reset, all EMAC registers are set to their default values. Any Writes to
unused registers or register bits are ignored and reads return a value of 0. For compatibil-
ity with future revisions, unused bits within a register must always be written with a value
of 0. Read/Write attributes, reset conditions, and bit descriptions of all of the EMAC reg-
isters are provided in this section.

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EMAC Test Register

The EMAC Test Register allows test functionality of the EMAC block. Available test
modes are defined for bits [6:0]. See Table 180.

Table 180. EMAC Test Register (EMAC_ TEST = 0020h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
CPU Access R R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write, R = Read Only.

Bit
Position Value Description
7 0 Reserved.
6 0 FIFO test mode disabled—Normal operation.
TEST_FIFO
1 FIFO test mode enabled.
5 0 Select the Receive FIFO when FIFO test mode is enabled.
TxRx_SEL
1 Select the Transmit FIFO when FIFO test mode is enabled.
4 0 Normal operation.
SSTC
1 Short Cut Slot Timer Counter. Slot time is shortened to
speed up simulation.
3 0 Normal operation.
SIMR
1 Simulation Reset.
2 0 Normal operation.
FRC_OVR_ERR
1 Force Overrun error in Receive FIFO.
1 0 Normal operation.
FRC_UND_ERR
1 Force Underrun error in Transmit FIFO.
0 0 Normal operation.
LPBK
1 EMAC Transmit interface is looped back into EMAC Receive
interface.

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EMAC Configuration Register 1

The EMAC Configuration Register 1 allows control of the padding, autodetection, cyclic
redundancy checking (CRC) control, full-duplex, field length checking, maximum packet
ignores, and proprietary header options. See Table 181.

Table 181. EMAC Configuration Register 1 (EMAC_CFG1 = 0021h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
7 0 No padding. Assume all frames presented to EMAC have
PADEN proper length.
1 EMAC pads all short frames by adding zeroes to the end of the
data field. This bit is used in conjunction with ADPADN and
VLPAD.
6 0 Disable autodetection.
ADPADN
1 Enable frame detection by comparing the two bytes following
the source address with 0x8100 (VLAN Protocol ID) and pad
accordingly. This bit is ignored if PADEN is cleared to 0.
5 0 Do not pad all short frames.
VLPAD
1 EMAC pads all short frames to 64 bytes and append a valid
CRC. This bit is ignored if PADEN is cleared to 0.
4 0 Do not append CRC.
CRCEN
1 Append CRC to every frame regardless of padding options.
3 0 HALF-DUPLEX mode. CSMA/CD is enabled.
FULLD
1 Enable FULL-DUPLEX mode. CSMA/CD is disabled.
2 0 Ignore the length field within Transmit/Receive frames.
FLCHK
1 Both Transmit and Receive frame lengths are compared to the
length/type field. If the length/type field represents a length
then the frame length check is performed.
1 0 Limit the Receive frame-size to the number of bytes specified
HUGEN in the MAXF[15:0] field.
1 Allow unlimited sized frames to be received. Ignore the
MAXF[15:0] field.

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Bit
Position Value Description
0 0 No proprietary header. Normal operation.
DCRCC
1 Four bytes of proprietary header, ignored by CRC, exists on
the front of IEEE 802.3 frames.

Table 182 lists the results of different settings for bits [7:4] of EMAC Configuration Reg-
ister 1.

Table 182. CRC/PAD Features of EMAC Configuration Register

ADPADN VLPADN PADEN CRCEN Result

0 0 0 0 No pad or CRC appended.
0 0 0 1 CRC appended.
0 0 1 0 Pad to 60 bytes if necessary; append CRC (min. size = 64).
0 0 1 1 Pad to 60 bytes if necessary; append CRC (min. size = 64).
0 1 0 0 No pad or CRC appended.
0 1 0 1 CRC appended.
0 1 1 0 Pad to 64 bytes if necessary, append CRC (min. size = 68).
0 1 1 1 Pad to 64 bytes if necessary, append CRC (min. size = 68).
1 0 0 0 No pad or CRC appended.
1 0 0 1 CRC appended.
1 0 1 0 If VLAN not detected, pad to 60, add CRC.
If VLAN detected, pad to 64, add CRC.
1 0 1 1 If VLAN not detected, pad to 60, add CRC.
If VLAN detected, pad to 64, add CRC.
1 1 0 0 No pad or CRC appended.
1 1 0 1 CRC appended.
1 1 1 0 If VLAN not detected, pad to 60, add CRC.
If VLAN detected, pad to 64, add CRC.
1 1 1 1 If VLAN not detected, pad to 60, add CRC.
If VLAN detected, pad to 64, add CRC.

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EMAC Configuration Register 2

The EMAC Configuration Register 2 controls the behavior of the back pressure and late
collision data from the Descriptor table. See Table 183.

Table 183. EMAC Configuration Register 2 (EMAC_CFG2 = 0022h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 1 1 0 1 1 1

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
7 0 Use normal back-off algorithm prior to transmitting packet. No
BPNB back pressure applied.
1 After incidentally causing a collision during back pressure, the
EMAC immediately (that is, no back-off) retransmits the packet
without back-off, which reduces the chance of further collisions
and ensures that the Transmit packets are sent.
6 0 Enable exponential back-off.
NOBO
1 The EMAC immediately retransmits following a collision rather
than use the binary exponential backfill algorithm, as specified
in the IEEE 802.3 specification.
[5:0] 00h–3Fh Sets the number of bytes after Start Frame Delimiter (SFD) for
LCOL which a late collision occurs. By default, all late collisions are
aborted.

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EMAC Configuration Register 3

The EMAC Configuration Register 3 controls preamble length and value, excessive defer-
ment, and the number of retransmission tries. See Table 184.

Table 184. EMAC Configuration Register 3 (EMAC_CFG3 = 0023h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 1 1 1 1

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
7 0 The EMAC allows any preamble length as per the IEEE 802.3
LONGP specification.*
1 The EMAC only allows Receive packets that contain preamble
fields less than 12 bytes in length.*
6 0 No preamble error checking is performed.
PUREP
1 The EMAC verifies the content of the preamble to ensure that it
contains a value of 55h and that it is error-free. Packets
containing an errored preamble are discarded.
5 0 The EMAC aborts when the excessive deferral limit is reached.
XSDFR
1 The EMAC defers to the carrier indefinitely as per the IEEE
802.3 specification.
4 0 Disable 10 Mbps ENDEC mode.
BITMD
1 Enable 10 Mbps ENDEC mode.
[3:0] 0h–Fh A programmable field specifying the number of retransmission
RETRY attempts following a collision before aborting the packet due to
excessive collisions.
Note: IEEE 802.3 specifies a minimum of 56 bits of preamble. A maximum number of bits is not de-
fined. For details, see the IEEE 802.3 Specification, Section 7.2.3.2.

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EMAC Configuration Register 4

The EMAC Configuration Register 4 controls pause control frame behavior, back
pressure, and receive frame acceptance. See Table 185.

Table 185. EMAC Configuration Register 4 (EMAC_CFG4 = 0024h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R/W R/W R/W R/W R/W R/W R/W

Note: R = Read Only; R/W = Read/Write.

Bit
Position Value Description
7 0 Reserved.
6 0 Do not transmit a pause control frame.
TPCF
1 Transmit pause control frame (FULL-DUPLEX mode). TPCF
continually sends pause control frames until negated.
5 0 Disable back pressure.
THDF
1 EMAC asserts back pressure on the link. Back pressure
causes preamble to be transmitted, raising carrier sense
(HALF-DUPLEX mode).
4 0 Only accept frames that meet preset criteria (that is, address,
PARF CRC, length, etc.).
1 All frames are received regardless of address, CRC, length,
etc.
3 0 EMAC ignores received pause control frames.
RxFC
1 EMAC acts upon pause control frames received.
2 0 PAUSE control frames are not allowed to be transmitted.
TxFC
1 PAUSE control frames are allowed to be transmitted.
1 0 Do not force a pause condition.
TPAUSE
1 Force a pause condition while this bit is asserted.
0 0 EMAC receiver disabled.
RxEN
1 EMAC receiver enabled.

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EMAC Station Address Register

The EMAC Station Address register is used for two functions. In the address recogni-
tion logic for Receive frames, EMAC_STAD_0–EMAC_STAD_5 are matched against
the sixth byte Destination Address (DA) field of the Receive frame. EMAC_STAD_0 is
matched against the first byte of the Receive frame, and EMAC_STAD_5 is matched
against the sixth byte of the Receive frame. Bit 0 of EMAC_STAD_0 (STAD[40]) is
matched against the first bit (Unicast/Multicast bit) of the first byte of the Receive
frame. This bit ordering is used to logically map the PE-MACMII station address as
illustrated below.
EMAC_STAD0[7:0] contains STAD[47:40]
....
....
EMAC_STAD5[7:0] contains STAD[7:0]

The second function of the EMAC Station Address registers is to provide the Source
Address (SA) field of Transmit Pause frames when these frames are transmitted by the
EMAC. EMAC_STAD_0 provides the first byte of the 6 byte SA field and
EMAC_STAD_5 provides the final byte of the SA field in order of transmission. The LSB
is the first byte sent out. The EMAC Station Address register is listed in Table 186.

Table 186. EMAC Station Address Register (EMAC_STAD_0 = 0025h, EMAC_STAD_1 =

0026h, EMAC_STAD_2 = 0027h, EMAC_STAD_3 = 0028h, EMAC_STAD_4 = 0029h,
EMAC_STAD_5 = 002Ah)

Bit 7 6 5 4 3 2 1 0
EMAC_STAD_0 Reset 0 0 0 0 0 0 0 0

EMAC_STAD_1 Reset 0 0 0 0 0 0 0 0

EMAC_STAD_2 Reset 0 0 0 0 0 0 0 0

EMAC_STAD_3 Reset 0 0 0 0 0 0 0 0

EMAC_STAD_4 Reset 0 0 0 0 0 0 0 0

EMAC_STAD_5 Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

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Bit
Position Value Description
[7:0] 00h–FFh This 48-bit station address comprises {EMAC_STAD_5,
EMAC_STAD_x EMAC_STAD_4, EMAC_STAD_3, EMAC_STAD_2,
EMAC_STAD_1, EMAC_STAD_0}.

EMAC Transmit Pause Timer Value Register—Low and High Bytes

The Low and High bytes of the EMAC Transmit Pause Timer Value Register are inserted
into outgoing pause control frames. See Table 187 and Table 188.

Table 187. EMAC Transmit Pause Timer Value Register—Low Byte (EMAC_TPTV_L = 002Bh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FFh The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is
EMAC_TPTV_L inserted into outgoing pause control frames as the pause
timer value upon asserting TPCF.

Table 188. EMAC Transmit Pause Timer Value Register—High Byte (EMAC_TPTV_H = 002Ch)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FFh The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is
EMAC_TPTV_H inserted into outgoing pause control frames as the pause
timer value upon asserting TPCF.

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EMAC Interpacket Gap

EMAC Interpacket Gap Overview
Interpacket Gap (IPG) is measured between the last nibble of the frame check sequence
(FCS) and the first nibble of the preamble of the next packet. Three registers are available
to fine tune the IPG, the EMAC_IPGT, EMAC_IPGR1, and the EMAC_IPGR2. The first
register EMAC_IPGT determines the back-to-back Transmit IPG. The other two registers
determine the non-back-to-back IPG in two parts. Table 189 lists the values for the
EMAC_IPGT and the corresponding IPGs for both FULL-DUPLEX and HALF-
DUPLEX modes.

Table 189. EMAC_IPGT Back-to-Back Settings for Full- and Half-Duplex Modes

MII, RMII/SMII, PMD MII, RMII/SMII ENDEC Mode

(100 Mbps) (10 Mbps) (10 Mbps)
Clock Period = 40 ns Clock Period = 400 ns Clock Period = 100 ns
IPGT[6:0] IPGT[6:0] IPGT[6:0]
Half Full Interpacket Half Full Interpacket Half Full Interpacket
Duplex Duplex Gap Duplex Duplex Gap Duplex Duplex Gap
0Dh 0.12 µs 00h 1.2 µs 10h 1.9 µs
0Bh 0.44 µs 08h 4.4 µs 18h 2.7 µs
0Ch 0.60 µs 0Ch 6.0 µs 20h 3.5 µs
10h 0.76 µs 10h 7.5 µs 40h 6.7 µs
*12h 15h 0.96 µs 12h 15h 9.6 µs 5Ah 5Dh 9.6 µs
20h 1.40 µs 20h 14.0 µs 20h 13.0 µs
Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.

The equations for back-to-back Transmit IPG are determined by the following:

FULL-DUPLEX Mode (3 clocks + IPGT clocks) * clock period = IPG

HALF-DUPLEX Mode (6 clocks + IPGT clocks) * clock period = IPG

Table 190 on page 307 lists the IPGR2 settings for the non-back-to-back packets.

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Table 190. EMAC_IPGT Non-Back-to-Back Settings for Full- /Half-Duplex Modes

MII, RMII/SMII, PMD MII, RMII/SMII ENDEC Mode

(100 Mbps) (10 Mbps) (10 Mbps)
Clock Period = 40 ns Clock Period = 400 ns Clock Period = 100 ns
IPGR2[6:0] Interpacket IPGR2[6:0] Interpacket IPGR2[6:0] Interpacket
Gap Gap Gap
00h 0.24 µs 00h 2.4 µs 00h 0.6 µs
10h 0.88 µs 10h 8.8 µs 10h 2.2 µs
*12h 0.96 µs 12h 9.6 µs 20h 3.8 µs
20h 1.52 µs 20h 15.2 µs 40h 7.0 µs
40h 2.80 µs 40h 28.0 µs 5Ah 9.6 µs
7Fh 5.32 µs 7Fh 53.2 µs 7Fh 13.3 µs
Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.

A non-back-to-back Transmit IPG is determined by the following formula:

(6 clocks + IPGR2 clocks) * clock period = IPG

The difference in values between Table 189 on page 306 and Table 190 is due to the
asynchronous nature of the Carrier Sense (CRS). The CRS must undergo a 2-clock
synchronization before the internal Tx state machine detects it. This synchronization
equates to a 6-clock intrinsic delay between packets instead of the 3-clock intrinsic delay
in the back-to-back packet mode. More information covering this topic is found in the
IEEE 802.3/4.2.3.2.1 Carrier Deference section.

EMAC Interpacket Gap Register

The EMAC Interpacket Gap (IPG) is a programmable field representing the IPG between
back-to-back packets. It is the IPG parameter used in FULL-DUPLEX and HALF-
DUPLEX modes between back-to-back packets. Set this field to the appropriate number
of IPG bytes. The default setting of 15h represents the minimum IPG of 0.96 µs
(at 100 Mbps) or 9.6 μs (at 10 Mbps). See Table 191.

Table 191. EMAC Interpacket Gap Register (EMAC_IPGT = 002Dh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 1 0 1 0 1

CPU Access R R/W R/W R/W R/W R/W R/W R/W

Note: R = Read Only; R/W = Read/Write

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Bit
Position Value Description
7 0 Reserved.
[6:0] 00h–7Fh The number of bytes of IPG.
IPGT

EMAC Non-Back-To-Back IPG Register—Part 1

Part 1 of the EMAC non-back-to-back IPG Register is a programmable field representing
the optional carrier sense window referenced in IEEE 802.3/4.2.3.2.1 Carrier Deference. If
a carrier is detected during the timing of IPGR1, the EMAC defers to the carrier. If, how-
ever, the carrier becomes active after IPGR1, the EMAC continues timing for IPGR2 and
transmits, knowingly causing a collision. This collision acts to ensure fair access to the
medium. Its range of values is 00h to IPGR2. See Table 192. The default setting of 0Ch
represents the Carrier Sense Window Referencing depicted tin IEEE 802.3, Section
4.2.3.2.1.

Table 192. EMAC Non-Back-To-Back IPG Register—Part 1 (EMAC_IPGR1 = 002Eh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 1 1 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write

Bit
Position Value Description
7 0 Reserved.
[6:0] 00h–7F This is a programmable field representing the optional carrier
IPGR 1 h sense window referenced in IEEE 802.3/4.2.3.2.1 Carrier
Deference.

EMAC Non-Back-To-Back IPG Register—Part 2

Part 2 of the EMAC non-back-to-back IPG Register is a programmable field representing
the non-back-to-back IPG. Its default is 12h, which represents the minimum IPG of
0.96 µs at 100 Mbps or 9.6 µs at 10 Mbps. See Table 193 on page 309.

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Table 193. EMAC Non-Back-To-Back IPG Register—Part 2 (EMAC_IPGR2 = 002Fh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 1 0 0 1 0

CPU Access R R/W R/W R/W R/W R/W R/W R/W

Note: R = Read Only; R/W = Read/Write.

Bit
Position Value Description
7 0 Reserved.
[6:0] 00h–7Fh This bit range is a programmable field representing the non-
IPGR2 back-to-back interpacket gap.

EMAC Maximum Frame Length Register—Low and High Bytes

The 16-bit field resets to 0600h, which represents a maximum Receive frame of 1536
bytes. An untagged maximum size Ethernet frame (packet) is 1518 bytes. A tagged frame
adds four bytes for a total of 1522 bytes. If a shorter maximum length restriction is more
appropriate, program this field. See Table 194 and Table 195 on page 310.
Note: The default value of 1536 bytes is large enough to cover the largest Ethernet packet, which
contains 14 bytes of Ethernet header, 1500 bytes of MAC client data, plus 4 bytes of CRC
for a total of 1518 maximum bytes. This value is also large enough to cover VLAN frames
with prepended headers up to 18 bytes.

VLAN frames have a proprietary header prepended to the Ethernet packet. Setting the
DCRCC bit in EMAC_CFG1 will exclude the first 4 bytes—the proprietary header—from
the CRC calculation. For VLAN packets, the maximum frame length is 1522, 4 more than
for normal Ethernet packets due to the 4 byte prepended header. Normal packets feature a
12 byte header before the MAC client data. For more information about this topic, refer to
Figure 3-1 of the IEEE 802.3 specification.

If a proprietary header is allowed, this field must be adjusted accordingly. For example, if
12 byte headers are prepended to frames, MAXF must be set to 1524 bytes to allow the
maximum VLAN tagged frame plus the 12 byte header. The default value of 1536 is large
enough to cover the largest Ethernet packet: 14 bytes of Ethernet header, 1500 bytes of
MAC client data, plus 4 bytes of CRC for a total of 1518 bytes maximum. It is also large
enough to cover VLAN packets with prepended headers up to 18 bytes. The following for-
mulas illustrate:

Ethernet Packet— Maximum frame size = normal Ethernet packet – 14 (Ethernet header)
+ 1500 (MAC client data) + 4 (CRC) = 1518 bytes

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VLAN Packet— Maximum frame size = VLAN with 4 byte header – 4 (VLAN header) +
14 (Ethernet header) + 1500 MAC client data) + 4 (CRC) = 1522 bytes.

Table 194. EMAC Maximum Frame Length Register—Low Byte (EMAC_MAXF_L = 0030h

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the Low byte of the 2 byte MAXF
EMAC_MAXF_L value, {EMAC_MAXF_H, EMAC_MAXF_L}. Bit 7 is bit 7 of
the 16-bit value. Bit 0 is bit 0 (lsb) of the 16-bit value.

Table 195. EMAC Maximum Frame Length Register—High Byte (EMAC_MAXF_H = 0031h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 1 1 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FF These bits represent the High byte of the 2 byte MAXF
EMAC_MAXF_H h value, {EMAC_MAXF_H, EMAC_MAXF_L}. Bit 7 is bit 15
(msb) of the 16-bit value. Bit 0 is bit 8 of the 16-bit value.

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EMAC Address Filter Register

The EMAC Address Filter Register functions as a filter to control Promiscuous mode, and
multicast and broadcast messaging. See Table 196.

Table 196. EMAC Address Filter Register (EMAC_AFR = 0032h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R/W R/W R/W R/W

Note: R = Read Only; R/W = Read/Write.

Bit
Position Value Description
[7:4] 0h Reserved.
3 1 Enable Promiscuous Mode. Receive all incoming packets
PROM regardless of station address. Disables station address
filtering.
0 Disable Promiscuous Mode.
2 1 Accept any multicast message. A multicast packet is
MC determined by the first bit in the destination address. If the first
LSB is a 1, it is a group address and is globally or locally
administered depending on the 2nd bit. For more information,
see IEEE 802.3/3.2.3.
0 Do not accept multicast messages of any type.
1 1 Accept only qualified multicast (QMC) messages as
QMC determined by the hash table.
0 Do not accept QMC messages.
0 1 Accept broadcast messages. Broadcast messages have the
BC destination address set to FFFFFFFFFFFFh.
0 Do not accept broadcast messages.

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EMAC Hash Table Register

The EMAC Hash Table Register represents the 8x8 hash table matrix. This table is used as
an option to select between different multicast addresses. If a multicast address is
received, the first 6 bits of the CRC are decoded and added to a table that points to a single
bit within the hash table matrix. If the selected bit = 1, the multicast packet is accepted. If
the bit = 0, the multicast packet is rejected. See Table 197.

Table 197. EMAC Hash Table Register (EMAC_HTBL_0 = 0033h, EMAC_HTBL_1 = 0034h,
EMAC_HTBL_2 = 0035h, EMAC_HTBL_3 = 0036h, EMAC_HTBL_4 = 0037h, EMAC_HTBL_5
= 0038h, EMAC_HTBL_6 = 0039h, EMAC_HTBL_7 = 003Ah)

Bit 7 6 5 4 3 2 1 0
EMAC_HTBL_0 Reset 0 0 0 0 0 0 0 0

EMAC_HTBL_1 Reset 0 0 0 0 0 0 0 0

EMAC_HTBL_2 Reset 0 0 0 0 0 0 0 0

EMAC_HTBL_3 Reset 0 0 0 0 0 0 0 0

EMAC_HTBL_4 Reset 0 0 0 0 0 0 0 0

EMAC_HTBL_5 Reset 0 0 0 0 0 0 0 0

EMAC_HTBL_6 Reset 0 0 0 0 0 0 0 0

EMAC_HTBL_7 Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write

Bit
Position Value Description
[7:0] 00h–FF This field is the hash table. The 64 bit hash table is
EMAC_HTBL_x h {EMAC_HTBL_7, EMAC_HTBL_6, EMAC_HTBL_5,
EMAC_HTBL_4, EMAC_HTBL_3, EMAC_HTBL_2,
EMAC_HTBL_1, EMAC_HTBL_0}.

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EMAC MII Management Register

The EMAC MII Management Register is used to control the external PHY attached to the
MII. See Table 198.

Table 198. EMAC MII Management Register (EMAC_MIIMGT = 003Bh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
7 1 Rising edge causes the CTLD control data to be transmitted to
LCTLD external PHY if MII is not busy. This bit is self clearing.
0 No operation.
6 1 Rising edge causes status to be read from external PHY via
RSTAT PRSD[15:0] bus if MII is not busy. This bit is self clearing.
0 No operation.
5 1 Scan PHY address increments upon SCAN cycle. The SCAN
SCINC bit must also be set for the PHY address to increment after
each scan. The scanning starts at the EMAC_FIAD and
increments up to 1Fh. It then returns to the EMAC_FIAD
address.
0 Normal operation.
4 1 Perform continuous Read cycles via MII management. While in
SCAN SCAN mode, the EMAC_ISTAT[MGTDONE] bit is set when the
current PHY Read has completed. At this time, the
EMAC_PRSD register holds the Read data and the
EMAC_MIISTAT[4:0] holds the address of the PHY for which
the EMAC_PRSD data pertains.
0 Normal operation.
3 1 Suppress the MDO preamble. MDO is management data
SPRE output, an internal signal driven from the MDIO pin.
0 Normal preamble.

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Bit
Position Value Description
[2:0] Programmable divisor that produces MDC from SCLK. MDC is the
CLKS management data clock pin, which clocks MDIO data to and from the
PHY. Its frequency is SCLK divided by the MDC clock divider.
000 MDC = SCLK ÷ 4.
001 MDC = SCLK ÷ 4.
010 MDC = SCLK ÷ 6.
011 MDC = SCLK ÷ 8.
100 MDC = SCLK ÷ 10.
101 MDC = SCLK ÷ 14.
110 MDC = SCLK ÷ 20.
111 MDC = SCLK ÷ 28.

EMAC PHY Configuration Data Register—Low and High Byte

The Low and High bytes of the EMAC PHY Configuration Data Register represents the
configuration data written to the external PHY. The EMAC_CTLD_H and
EMAC_CTLD_L registers form a 16-bit register. These registers are loaded with data to
be sent via the MDIO pin to the PHY. The PHY is selected by setting the EMAC_FIAD.
The register inside the PHY is selected by setting EMAC_RGAD. See Table 199 and
Table 200 on page 315.

Table 199. EMAC PHY Configuration Data Register—Low Byte (EMAC_CTLD_L = 003Ch)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FF These bits represent the Low byte of the 2 byte PHY
EMAC_CTLD_L h configuration data value, {EMAC_CTLD_H,
EMAC_CTLD_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit
0 (lsb) of the 16 bit value.

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Table 200. EMAC PHY Configuration Data Register—High Byte (EMAC_CTLD_H = 003Dh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FF These bits represent the High byte of the 2 byte PHY
EMAC_CTLD_H h configuration data value, {EMAC_CTLD_H,
EMAC_CTLD_L}. Bit 7 is bit 15 (msb) of the 16 bit value. Bit
0 is bit 8 of the 16 bit value.

EMAC PHY Address Register

The EMAC PHY Address Register allows access to the external PHY registers. See
Table 201.

Table 201. EMAC PHY Address Register (EMAC_RGAD = 003Eh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R/W R/W R/W R/W R/W

Note: R = Read Only; R/W = Read/Write.

Bit
Position Value Description
[7:5] 000 Reserved.
[4:0] 00h–1F Programmable 5 bit value which selects address within the
RGAD h selected external PHY.

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EMAC PHY Unit Select Address Register

The EMAC PHY Unit Select Address Register allows the selection of multiple connected
external PHY devices. See Table 202.

Table 202. EMAC PHY Unit Select Address Register (EMAC_FIAD = 003Fh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R/W R/W R/W R/W R/W

Note: R = Read Only; R/W = Read/Write.

Bit
Position Value Description
[7:5] 000 Reserved.
[4:0] 00h–1Fh Programmable 5-bit value that selects an external PHY.
FIAD

EMAC Transmit Polling Timer Register

This register sets the Transmit Polling Period in increments of TPTMR = SYSCLK ÷ 256.
Whenever this register is written, the status of the Transmit Buffer Descriptor is checked
to determine if the EMAC owns the Transmit buffer. It then rechecks this status every
TPTMR (calculated by TPTMR x EMAC_PTMR[7:0]). The Transmit Polling Timer is
disabled if this register is set to 00h (which also disables the transmitting of packets). If a
transmission is in progress when EMAC_PTMR is set to 00h, the transmission will com-
plete. See Table 203.

Table 203. EMAC Transmit Polling Timer Register (EMAC_PTMR = 0040h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FFh The Transmit polling period.
EMAC_PTMR

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EMAC Reset Control Register

The bit values in the EMAC Reset Control Register are not self-clearing bits. You are
responsible for controlling their state. See Table 204.

Table 204. EMAC Reset Control Register (EMAC_RST = 0041h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 1 0 0 0 0 0

CPU Access R R R/W R/W R/W R/W R/W R/W

Note: R = Read Only; R/W = Read/Write.

Bit
Position Value Description
[7:6] 00 Reserved
5 1 Software Reset Active—resets Receive, Transmit, EMAC
SRST Control and EMAC MII_MGT functions
0 Normal operation
4 1 Reset Transmit function
HRTFN
0 Normal operation
3 1 Reset Receive function
HRRFN
0 Normal operation
2 1 Reset EMAC Transmit Control function
HRTMC
0 Normal operation
1 1 Reset EMAC Receive Control function
HRRMC
0 Normal operation
0 1 Reset EMAC Management function
HRMGT
0 Normal operation

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EMAC Transmit Lower Boundary Pointer Register—Low and High Bytes

The EMAC Transmit Lower Boundary Pointer is set to the start of the Transmit buffer in
EMAC shared memory. See Table 205 and Table 206.

Table 205. EMAC Transmit Lower Boundary Pointer Register—Low Byte (EMAC_TLBP_L = 0042h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R R R R R

Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FF These bits represent the Low byte of the 2 byte Transmit
EMAC_TLBP_L h Lower Boundary Pointer value, {EMAC_TLBP_H,
EMAC_TLBP_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit 0
(lsb) of the 16 bit value.

Table 206. EMAC Transmit Lower Boundary Pointer Register—High Byte (EMAC_TLBP_H
= 0043h)*

Bit 7 6 5 4 3 2 1 0
Reset 1 1 0 0 0 0 0 0

CPU Access R R R R/W R/W R/W R/W R/W

Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FF These bits represent the High byte of the 2 byte Transmit
EMAC_TLBP_H h Lower Boundary Pointer value, {EMAC_TLBP_H,
EMAC_TLBP_L}. Bit 7 is bit 15 (msb) of the 16 bit value. Bits
7:5 default to 000 on reset; bit 0 is bit 8 of the 16-bit value.
Note: *Bits 7:5 are not used by the EMAC; these bits return 000.

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EMAC Boundary Pointer Register—Low and High Bytes

The Boundary Pointer is set to the start of the Receive buffer (end of Transmit buffer +1)
in EMAC shared memory. This pointer is 24 bits and determined by {RAM_ADDR_U,
EMAC_BP_H, EMAC_BP_L}. The upper 3 bits of the EMAC_BP_H register are hard-
wired inside the eZ80F91 device to locate the base of EMAC shared memory. The last 5
bits of the EMAC_BP_L register value are hard-wired to keep the addressing aligned to
a 32 byte boundary. See Table 207 and Table 208.

Table 207. EMAC Boundary Pointer Register—Low Byte (EMAC_BP_L = 0044h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R R R R R

Note: R = Read Only, R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the Low byte of the 3 byte EMAC
EMAC_BP_L Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,
EMAC_BP_L}. Bit 7 is bit 7 of the 24 bit value. Bit 0 is bit 0 of
the 24 bit value.

Table 208. EMAC Boundary Pointer Register—High Byte (EMAC_BP_H = 0045h)

Bit 15:13 12:8

Reset 1 1 0 0 0 0 0 0

CPU Access R R R R/W R/W R/W R/W R/W

Note: R = Read Only, R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the High byte of the 3 byte EMAC
EMAC_BP_H Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,
EMAC_BP_L}. Bit 7 is bit 15 of the 24 bit value. Bit 0 is bit 8 of
the 24 bit value.

EMAC Boundary Pointer Register—Upper Byte

The EMAC Boundary Pointer Register maps directly to the RAM_ADDR_U register
within the eZ80F91 device. This register value is Read Only. See Table 209 on page 320.

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Table 209. EMAC Boundary Pointer Register—Upper Byte (EMAC_BP_U = 0046h)

Bit 7 6 5 4 3 2 1 0
Reset 1 1 1 1 1 1 1 1

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the upper byte of the 3 byte EMAC
EMAC_BP_U Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,
EMAC_BP_L}. Bit 7 is bit 23 of the 24 bit value. Bit 0 is bit 16 of
the 24 bit value.

EMAC Receive High Boundary Pointer Register—Low and High Bytes

The Receive High Boundary Pointer Register must be set to the end of the Receive buffer
+1 in EMAC shared memory. This RHBP uses the same RAM_ADDR_U as the
EMAC_BP_U pointer above. See Table 210 and Table 211 on page 321.

Table 210. EMAC Receive High Boundary Pointer Register—Low Byte (EMAC_RHBP_L = 0047h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R R R R R

Note: R = Read Only, R/W = Read/Write

Bit
Position Value Description
[7:0] 00h–E0h These bits represent the Low byte of the 2 byte EMAC
EMAC_RHBP_L Receive High Boundary Pointer value, {EMAC_RHBP_H,
EMAC_RHBP_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit
0 (lsb) of the 16 bit value.

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Table 211. EMAC Receive High Boundary Pointer Register—High Byte (EMAC_RHBP_H = 0048h)

Bit 7 6 5 4 3 2 1 0
Reset 1 1 0 0 0 0 0 0
CPU Access R R R R/W R/W R/W R/W R/W
Note: R = Read Only, R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the High byte of the 2 byte EMAC
EMAC_RHBP_H Receive High Boundary Pointer value, {EMAC_RHBP_H,
EMAC_RHBP_L}. Bit 7 is bit 15 (msb) of the 16 bit value. Bit
0 is bit 8 of the 16 bit value.
Note: *Bits 7:5 are not used by the EMAC; these bits return 000 upon reset.

EMAC Receive Read Pointer Register—Low and High Bytes

The Receive Read Pointer Register must be initialized to the EMAC_BP value (start of the
Receive buffer). This register points to where the next Receive packet is read from. The
EMAC_BP[12:5] is loaded into this register whenever the EMAC_RST [(HRRFN) is set
to 1. The RxDMA block uses the Emac_Rrp[12:5] to compare to EmacRwp[12:5] for
determining how many buffers remain. The result equates to the EmacBlksLeft register.
See Table 212 and Table 213 on page 322.

Table 212. EMAC Receive Read Pointer Register—Low Byte (EMAC_RRP_L = 0049h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R R R R R

Note: R = Read Only, R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the Low byte of the 2 byte EMAC
EMAC_RRP_L Receive Read Pointer value, {EMAC_RRP_H,
EMAC_RRP_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit 0
(lsb) of the 16 bit value.

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Table 213. EMAC Receive Read Pointer Register—High Byte (EMAC_RRP_H = 004Ah)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
CPU Access R R R R/W R/W R/W R/W R/W
Note: R = Read Only, R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the High byte of the 2-byte EMAC
EMAC_RRP_H Receive Read Pointer value, {EMAC_RRP_H,
EMAC_RRP_L}. Bit 7 is bit 15 (msb) of the 16-bit value. Bits
7:5 default to 000 on reset; bit 0 is bit 8 of the 16-bit value.

EMAC Buffer Size Register

The lower six bits of this register set the level at which the EMAC either transmits a pause
control frame or jams the Ethernet bus, depending on the mode selected. When each of
these bits contain a zero, this feature is disabled.
In FULL-DUPLEX mode, a Pause Control Frame is transmitted as a One-shot operation.
The software must free up a number of Rx buffers so that the number of buffers remaining,
EmacBlksLeft, is greater than TCPF_LEV.
In HALF-DUPLEX mode, the EMAC jams the Ethernet by sending a continuous stream
of hexadecimal 5s (5fh). When the software frees up the Rx buffers and the number of
buffers remaining, EmacBlksLeft, is greater than TCPF_LEV, the EMAC stops jamming.

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Table 214. EMAC Buffer Size Register (EMAC_BUFSZ = 004Bh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:6] 00 Set EMAC Rx/Tx buffer size to 256 bytes.
BUFSZ
01 Set EMAC Rx/Tx buffer size to 128 bytes.
10 Set EMAC Rx/Tx buffer size to 64 bytes.
11 Set EMAC Rx/Tx buffer size to 32 bytes.
[5:0] 00h–3Fh Transmit Pause Control Frame level. 00h disables the
TPCF_LEV hardware generated transmit pause control frame.

EMAC Interrupt Enable Register

Enabling the Receive Overrun interrupt allows software to detect an overrun condition
as soon as it occurs. If this interrupt is not set, then an overrun cannot be detected until
the software processes the Receive packet with the overrun and checks the Receive sta-
tus in the Rx descriptor table. Because the receiver is disabled by an overrun error until
the Rx_OVR bit is cleared in the EMAC_ISTAT register, this packet is the final packet
in the Receive buffer. To re-enable the receiver before all of the Receive packets are
processed and the Receive buffer is empty, software enables this interrupt to detect the
overrun condition early. As it processes the Receive packets, it re-enables the receiver
when the number of free buffers is greater than the number of minimum buffers. See
Table 215 on page 324.

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Table 215. EMAC Interrupt Enable Register (EMAC_IEN = 004Ch)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
7 1 Enable Transmit State Machine Error Interrupt (system
TxFSMERR interrupt).
0 Disable Transmit State Machine Error Interrupt (system
interrupt).
6 1 Enable MII Management. Done Interrupt (system Interrupt).
MGTDONE
0 Disable MII Management. Done Interrupt (system Interrupt).
5 1 Enable Receive Control Frame Interrupt (Receive interrupt).
Rx_CF
0 Disable Receive Control Frame Interrupt (Receive interrupt).
4 1 Enable Receive Pause Control Frame interrupt (Receive
Rx_PCF interrupt).
0 Disable Receive Pause Control Frame interrupt (Receive
interrupt).
3 1 Enable Receive Done interrupt (Receive interrupt).
Rx_DONE
0 Disable Receive Done interrupt (Receive interrupt).
2 1 Enable Receive Overrun interrupt (System interrupt).
Rx_OVR
0 Disable Receive Overrun interrupt (System interrupt).
1 1 Enable Transmit Control Frame Interrupt (Transmit interrupt).
Tx_CF
0 Disable Transmit Control Frame Interrupt (Transmit interrupt).
0 1 Enable Transmit Done interrupt (Transmit interrupt).
Tx_DONE
0 Disable Transmit Done Interrupt (Transmit interrupt).

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EMAC Interrupt Status Register

When a Receive overrun occurs, all incoming packets are ignored until the
Rx_OVR_STAT status bit is cleared by software. Consequently, software controls when
the receiver is re-enabled after an overrun. Enable the Rx_OVR interrupt to detect overrun
conditions when they occur. Clear this condition when the Rx buffers are freed to avoid
additional overrun errors. See Table 216.
Note: Status bits are not self-clearing. Each status bit is cleared by writing a 1 into the selected
bit.

Table 216. EMAC Interrupt Status Register (EMAC_ISTAT = 004Dh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
7 1 An internal error occurs in the EMAC Transmit path. The
TxFSMERR_STAT Transmit path must be reset to reset this error condition.
0 Normal operation—no Transmit state machine errors.
6 1 The MII Management interrupt has completed a Read
MGTDONE_STAT (RSTAT or SCAN) or a Write (LDCTLD) access to the
PHY.
0 The MII Management interrupt does not occur.
5 1 Receive Control Frame interrupt (Receive Interrupt)
Rx_CF_STAT occurs.
0 Receive Control Frame interrupt does not occur.
4 1 Receive Pause Control Frame interrupt (Receive
Rx_PCF_STAT Interrupt) occurs.
0 Disable Receive Pause Control Frame interrupt (Receive
Interrupt) does not occur.
3 1 Receive Done interrupt (Receive Interrupt) occurs.
Rx_DONE_STAT
0 Disable Receive Done interrupt (Receive Interrupt) does
not occur.
2 1 Receive Overrun interrupt (System Interrupt) occurs.
Rx_OVR_STAT
0 Receive Overrun interrupt (System Interrupt) does not
occur.

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Bit
Position Value Description
1 1 Transmit Control Frame Interrupt (Transmit Interrupt)
Tx_CF_STAT occurs.
0 Transmit Control Frame Interrupt (Transmit Interrupt)
does not occur.
0 1 Transmit Done interrupt (Transmit Interrupt) occurs.
Tx_DONE_STAT
0 Transmit Done interrupt (Transmit Interrupt) does not
occur.

EMAC PHY Read Status Data Register—Low and High Bytes

The PHY MII Management Data Register is where the data Read from the PHY is stored.
See Table 217 and Table 218 on page 327.

Table 217. EMAC PHY Read Status Data Register—Low Byte (EMAC_PRSD_L = 004Eh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the Low byte of the 2 byte EMAC PHY
EMAC_PRSD_L Read Status Data value, {EMAC_PRSD_H,
EMAC_PRSD_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit
0 (lsb) of the 16 bit value.

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Table 218. EMAC PHY Read Status Data Register—High Byte (EMAC_PRSD_H = 004Fh)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the High byte of the 2-byte EMAC
EMAC_PRSD_H PHY Read Status Data value, {EMAC_PRSD_H,
EMAC_PRSD_L}. Bit 7 is bit 15 (msb) of the 16-bit value.
Bit 0 is bit 8 of the 16-bit value.

EMAC MII Status Register

The EMAC MII Status Register is used to determine the current state of the external PHY
device. See Table 219.

Table 219. EMAC MII Status Register (EMAC_MIISTAT = 0050h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
7 1 MII management operation in progress—Busy. This status bit
BUSY goes busy whenever the LCTLD (PHY Write) or the RSTAT
(PHY Read) is set in the EMAC_MIIMGT register. It is
negated when the Write or Read operation to the PHY has
completed. In SCAN mode, the BUSY will be asserted until
the SCAN is disabled. Use the EmacIStat[MGTDONE]
interrupt status bit to determine when the data is valid.
0 Not Busy.
6 1 Local copy of PHY Link fail bit.
MIILF
0 PHY Link OK.

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5 1 MII Scan result is not valid Emac_PRSD is invalid

NVALID
0 Emac_PRSD is valid.
[4:0] 00h–1Fh Denotes PHY addressed in current scan cycle.
RDADR

EMAC Receive Write Pointer Register—Low Byte

The Read Only Receive-Write-Pointer register reports the current RxDMA Receive Write
pointer. This pointer gets initialized to EmacTLBP whenever Emac_RST bits SRST or
HRRTN are set. Because the size of the packet is limited to a minimum of 32 bytes, the
last five bits are always zero. See Table 220 and Table 221 on page 329.

Table 220. EMAC Receive Write Pointer Register—Low Byte (EMAC_RWP_L = 0051h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0] 00h–E0 These bits represent the Low byte of the 2 byte EMAC
EMAC_RWP_L h RxDMA Receive Write Pointer value, {EMAC_RWP_H,
EMAC_RWP_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit 0
(lsb) of the 16 bit value.

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EMAC Receive Write Pointer Register—High Byte

Because of the size of the EMAC’s 8 KB SRAM, the upper three bits of the EMAC
Receive Write Pointer Register are always zero.

Table 221. EMAC Receive Write Pointer Register—High Byte (EMAC_RWP_H = 0052h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0] 00h–1Fh These bits represent the High byte of the 2 byte EMAC
EMAC_RWP_H RxDMA Receive Write Pointer value, {EMAC_RWP_H,
EMAC_RWP_L}. Bit 7 is bit 15 (msb) of the 16 bit value. Bit
0 is bit 8 of the 16 bit value.

EMAC Transmit Read Pointer Register—Low Byte

The Low byte of the Transmit Read Pointer register reports the current TxDMA Transmit
Read pointer.This pointer is initialized to EmacTLBP whenever Emac_RST bits SRST or
HRRTN are set. Because the size of the packet is limited to a minimum of 32 bytes, the
last five bits are always zero. See Table 222.

Table 222. EMAC Transmit Read Pointer Register—Low Byte (EMAC_TRP_L = 0053h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0] 00h–E0h These bits represent the Low byte of the 2 byte EMAC
EMAC_TRP_L TxDMA Transmit Read Pointer value, {EMAC_TRP_H,
EMAC_TRP_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit 0
(lsb) of the 16 bit value.

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EMAC Transmit Read Pointer Register—High Byte

Because of the size of the EMAC’s 8 KB SRAM, the upper three bits of the EMAC Trans-
mit Read Pointer Register are always zero. See Table 223.

Table 223. EMAC Transmit Read Pointer Register—High Byte (EMAC_TRP_H = 0054h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access RO RO RO RO RO RO RO RO
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–1Fh These bits represent the High byte of the 2 byte EMAC
EMAC_TRP_H TxDMA Transmit Read Pointer value, {EMAC_TRP_H,
EMAC_TRP_L}. Bit 7 is bit 15 (msb) of the 16 bit value. Bit
0 is bit 8 of the 16 bit value.

EMAC Receive Blocks Left Register—Low and High Bytes

This register reports the number of buffers left in the Receive EMAC shared memory. The
hardware uses this information along with the block-level set in the EMAC_BUFSZ regis-
ter to determine when to transmit a pause control frame. Software uses this information to
determine when it must request that a pause control frame be transmitted (by setting bit 6
of the EMAC_CFG4 register). For the BlksLeft logic to operate properly, the Receive buf-
fer must contain at least one more packet buffer than the number of packet buffers
required for the largest packet. That is, one packet cannot fill the entire Receive buffer.
Otherwise, the BlksLeft will be in error. See Table 224 and Table 225 on page 331.

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Table 224. EMAC Receive Blocks Left Register—Low Byte (EMAC_BLKSLFT_L = 0055h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the Low byte of the 2 byte EMAC
EMAC_BLKSLFT_L Receive Blocks Left value, {EMAC_BLKSLFT_H,
EMAC_BLKSLFT_L}. Bit 7 is bit 7 of the 16 bit value. Bit
0 is bit 0 (lsb) of the 16 bit value.

Table 225. EMAC Receive Blocks Left Register—High Byte (EMAC_BLKSLFT_H = 0056h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the High byte of the 2 byte EMAC
EMAC_BLKSLFT_H Receive Blocks Left value, {EMAC_BLKSLFT_H,
EMAC_BLKSLFT_L}. Bit 7 is bit 15 (msb) of the 16 bit
value. Bit 0 is bit 8 of the 16 bit value.

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EMAC FIFO Data Register—Low and High Bytes

The FIFO Read/Write Test Access Data Register allows writing and reading the FIFO
selected by the EMAC_TEST TxRx_SEL bit when the EMAC_TEST register
TEST_FIFO bit is set. See Table 226 and Table 227.

Table 226. EMAC FIFO Data Register—Low Byte (EMAC_FDATA_L = 0057h)

Bit 7 6 5 4 3 2 1 0
Reset X X X X X X X X

CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.

Bit
Position Value Description
[7:0] 00h–FFh These bits represent the Low byte of the 10 bit EMAC
EMAC_FDATA_L FIFO data value, {EMAC_FDATA_H[1:0],
EMAC_FDATA_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is
bit 0 (lsb) of the 10 bit value.

Table 227. EMAC FIFO Data Register—High Byte (EMAC_FDATA_H = 0058h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 X X

CPU Access R R R R R R R/W R/W

Note: R = Read Only; R/W = Read/Write.

Bit
Position Value Description
[7:2] 00h Reserved.
[1:0] 0h–3h These bits represent the upper two bits of the 10 bit EMAC
EMAC_FDATA_H FIFO data value, {EMAC_FDATA_H[1:0],
EMAC_FDATA_L}. Bit 1 is bit 9 (msb) of the 16 bit value.
Bit 0 is bit 8 of the 10 bit value.

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EMAC FIFO Flags Register

The FIFO Flags value is set in the EMAC hardware to half full, or 16 bytes. See Table 228.

Table 228. EMAC FIFO Flags Register (EMAC_FFLAGS = 0059h)

Bit 7 6 5 4 3 2 1 0
Reset 0 0 1 1 0 0 1 1

CPU Access R R R R R R R R
Note: R = Read Only.

Bit
Position Value Description
7 1 Transmit FIFO full
TFF
0 Transmit FIFO not full
6 0 Reserved
5 1 Transmit FIFO almost empty
TFAE
0 Transmit FIFO not almost empty
4 1 Transmit FIFO empty
TFE
0 Transmit FIFO not empty
3 1 Receive FIFO full
RFF
0 Receive FIFO not full
2 1 Receive FIFO almost full
RFAF
0 Receive FIFO not almost full
1 1 Receive FIFO almost empty
RFAE
0 Receive FIFO not almost empty
0 1 Receive FIFO empty
RFE
0 Receive FIFO not empty

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On-Chip Oscillators
The eZ80F91 features two on-chip oscillators for use with an external crystal. The primary
oscillator generates the system clock for the internal CPU and the majority of the on-chip
peripherals. Alternatively, the XIN input pin also accepts a CMOS-level clock input signal.
If an external clock generator is used, the XOUT pin must be left unconnected. The second-
ary oscillator drives a 32 kHz crystal to generate the time-base for the Real-Time Clock.

Primary Crystal Oscillator Operation

Figure 63 on page 336 displays a recommended configuration for connection with an
external 50 MHz, 3rd-overtone, parallel-resonant crystal. Recommended crystal specifica-
tions are provided in Table 229 on page 336 and Table 230 on page 337. Printed circuit
board layout must add not more than 4 pF of stray capacitance to either the XIN or XOUT
pins. If oscillation does not occur, try removing C1 for testing and decreasing the value of
C2 by the estimated stray capacitance to decrease loading.

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On-Chip Oscillator

XIN XOUT

50 MHz Crystal
(Third Overtone)

R = 100 K
C 1 = 5 pF (this value is not critical)

C 2 = 10-15 pF L = 3.3 H (± 10%)

C3 = .01-0.1 F

Figure 63. Recommended Crystal Oscillator Configuration—50 MHz Operation

Table 229. Recommended Crystal Oscillator Specifications—1 MHz Operation

Frequency
Parameter Dependent Value Units Comments
Frequency 1 MHz
Resonance Parallel
Mode Fundamental
Series Resistance (RS) 750 Ohms Maximum
Load Capacitance (CL) 13 pF Maximum

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Table 229. Recommended Crystal Oscillator Specifications—1 MHz Operation

(Continued)

Frequency
Parameter Dependent Value Units Comments
Shunt Capacitance (C0) 7 pF Maximum
Drive Level 1 mW Maximum

Table 230. Recommended Crystal Oscillator Specifications—10 MHz Operation

Frequency
Parameter Dependent Value Units Comments
Frequency 10 MHz
Resonance Parallel
Mode Fundamental
Series Resistance (RS) 35 Ohms Maximum
Load Capacitance (CL) 30 pF Maximum
Shunt Capacitance (C0) 7 pF Maximum
Drive Level 1 mW Maximum

32 kHz Real-Time Clock Crystal Oscillator Operation

Figure 64 on page 338 displays a recommended configuration for connecting the Real-
Time Clock oscillator with an external 32 kHz, fundamental mode, parallel-resonant crys-
tal. The recommended crystal specifications are provided in Table 231on page 338. A
printed circuit board layout must not add more than 4 pF of stray capacitance to either the
RTC_XIN or RTC_XOUT pins. If oscillation does not occur, reduce the values of capaci-
tors C1 and C2 to decrease loading.
An on-chip MOS resistor sets the crystal drive current limit. This configuration does not
require an external bias resistor across the crystal. An on-chip MOS resistor provides the
biasing.

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RTC_XIN RTC_XOUT

C1 = 10 pF 32 kHz Crystal C2 = 10 pF
(Fundamental Mode)

Figure 64. Recommended Crystal Oscillator Configuration—32 kHz Operation

Table 231. Recommended Crystal Oscillator Specifications—32 kHz Operation

Parameter Value Units Comments

Frequency 32 kHz 32768 Hz
Resonance Parallel
Mode Fundamental
Series Resistance (RS) 50 kΩ Maximum
Load Capacitance (CL) 12.5 pF Maximum
Shunt Capacitance (C0) 3 pF Maximum
Drive Level 1 µW Maximum

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Electrical Characteristics
Absolute Maximum Ratings
Stresses greater than those listed in Table 232 causes permanent damage to the device.
These ratings are stress ratings only. Operation of the device at any condition outside those
indicated in the operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods affects device reliability. For
improved reliability, unused inputs must be tied to one of the supply voltages (VDD or
VSS).

Table 232. Absolute Maximum Ratings

Parameter Minimum Maximum Units Notes

Ambient temperature under bias (ºC) –40 +105 ºC 1
Storage temperature (ºC) –65 +150 C
Voltage on any pin with respect to VSS –0.3 +5.5 V 2
Voltage on VDD pin with respect to VSS –0.3 +3.6 V
Total power dissipation 830 mW
Maximum current out of VSS 230 mA
Maximum current into VDD 230 mA
Maximum current on input and/or inactive output pin –15 +15 µA
Maximum output current from active output pin –8 +8 mA
Flash memory Writes to Same Single Address — 2 — 3
Flash Memory Data Retention 100 — Years
Flash Memory Write/Erase Endurance 10,000 — Cycles 4
Notes
1. Operating temperature is specified in DC Characteristics.
2. This voltage applies to all pins except XIN and XOUT.
3. Before next erase operation.
4. Write cycles.

DC Characteristics
Table 233 on page 340 lists the DC characteristics of the eZ80F91 device.

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Table 233. DC Characteristics

TA = TA =
0 ºC to 70 ºC –40 ºC to 105 ºC

Symbol Parameter Minimum Typ2 Maximum Minimum Typ2 Maximum Units Conditions
VDD Supply Voltage 3.0 3.3 3.6 3.0 3.3 3.6 V
VIL Low Level –0.3 0.3 x VDD –0.3 0.3 x VDD V
Input Voltage
VIH High Level 0.7 x VDD 5.5 0.7 x VDD 5.5 V
Input Voltage
VOL Low Level 0.4 0.4 V VDD = 3.0 V;
Output Voltage IOL = 1 mA
VOH High Level 2.4 2.4 V VDD = 3.0 V;
Output Voltage IOH = –1 mA
VRTC RTC Supply 2.0 3.6 2.0 3.6 V
Voltage
IIL Input Leakage –10 +10 –10 +10 μA VDD = 3.6 V;
Current VIN = VDD or
VSS1
ITL Open-drain –10 +10 –10 +10 μA VDD = 3.6 V
Leakage Current
ICC a Active Current 26 40 mA @ 10 MHz
52 80 mA @ 20 MHz
137 190 mA @ 50 MHz
ICC h HALT Mode 15 20 mA @ 10 MHz
Current
27 40 mA @ 20 MHz
75 100 mA @ 50 MHz
ICC s SLEEP Mode 2.5 20 2.5 95 μA VBO_OFF=1
Current (VBO
disabled)
IRTC RTC Supply 2.5 10 2.5 10 μA Supply current
Current into VRTC
1This
condition excludes all pins with on-chip pull-ups when driven Low.
2
Values in Typical column are for Vdd = 3.3 V and TA = 25 ºC.

POR and VBO Electrical Characteristics

Table 234 on page 341 lists the Power-On Reset and Voltage Brownout characteristics of
the eZ80F91 device.

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Table 234. POR and VBO Electrical Characteristics

TA = –40 ºC to 105 ºC

Symbol Parameter Minimum Typ Maximum Unit Conditions

VVBO VBO Voltage Threshold 2.45 2.65 2.90 V VCC = VVBO
VPOR POR Voltage Threshold 2.55 2.75 2.95 V VCC = VPOR
VHYST POR/VBO Hysteresis 30 100 120 mV
TANA POR/VBO analog RESET duration 40 100 μs
TVBO_MIN VBO pulse reject period 10 μs
IPOR_VBO POR/VBO DC current consumption 40 50 μA
ISPOR_VBO POR/VBO DC SLEEP mode current 120 150 μA VBO_OFF=0
consumption (VBO enabled)
VCCRAMP VCC ramp rate requirements to 0.1 100 V/ms
guarantee proper RESET occurs

Flash Memory Characteristics

Table 235 lists the Flash memory characteristics of the eZ80F91 device. For Flash
programming and erase timing information, see Flash Memory on page 97.

Table 235. Flash Memory Electrical Characteristics and Timing

VDD = 3.0 V to 3.6 V;

TA = –40 ºC to 105 ºC

Symbol Minimum Typical Maximum Units Notes

Flash Byte Read Cycle Time 78 — — ns

Current Consumption Under Various Operating Conditions

Figure 65 on page 342 displays the typical current consumption of the eZ80F91 device
versus Vdd while operating at 25 ºC, with zero Wait states, and with either a 10 MHz,
20 MHz, or 50 MHz system clock.

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eZ80F91 Active Idd vs CLK Freq @ Vdd (25C)

180.00

160.00

140.00
Actve Idd (Icca) (mA)

120.00
100.00

80.00
60.00
40.00

20.00
0.00
10Mhz 20Mhz 50Mhz
Frequency (MHz)

Vdd=2.9V Vdd=3.3V Vdd=3.7V

Figure 65. ICC vs. System Clock Frequency During ACTIVE Mode

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Figure 66 displays the typical current consumption of the eZ80F91 device versus system
clock frequency while operating in HALT mode.

e Z80F 91 HALT M ode Idd vs CLK Fre q @ V dd (25C)

100.00

90.00

80.00
HALT Mode Idd (Icch) (mA)

70.00

60.00

50.00

40.00

30.00

20.00

10.00

0.00
10Mhz 20Mhz 50Mhz
Fr e q u e n cy (M Hz )

V dd=2.9V V dd=3.3V V dd=3.7V

Figure 66. ICC vs. System Clock Frequency During HALT Mode

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Figure 67 displays the typical current consumption of the eZ80F91 device versus Vdd
while operating in SLEEP mode (units in microamps, 10-6A); all peripherals off, and VBO
disabled.

e Z8 0 F 9 1 S L EEP M o d e Id d v s V d d (2 5 C )

2 .6 5

2 .6 0
SLEEP Mode Idd (Iccs) (uA)

2 .5 5

2 .5 0

2 .4 5

2 .4 0

2 .3 5

2 .3 0

2 .2 5

2 .2 0

2 .1 5
2 .9 3 .3 3 .7
V d d (V )

Ic c s ( V B O d is a b le d )

Figure 67. ICC vs. Vdd During SLEEP Mode

AC Characteristics
This section provides information about the AC characteristics and timing of the
eZ80F91 device. All AC timing information assumes a standard load of 50 pF on all
outputs. See Table 236.

Table 236. AC Characteristics

TA = TA =
0 ºC to 70 ºC –40 ºC to 105 ºC

Symbol Parameter Minimum Maximum Minimum Maximum Units Conditions

TXIN System Clock 20 1000 20 1000 ns VDD = 3.0–3.6 V
Cycle Time
TXINH System Clock 8 8 ns VDD = 3.0–3.6 V;
High Time TCLK = 20 ns
TXINL System Clock 8 8 ns VDD = 3.0–3.6 V;
Low Time TCLK = 20 ns

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Table 236. AC Characteristics (Continued)

TA = TA =
0 ºC to 70 ºC –40 ºC to 105 ºC

Symbol Parameter Minimum Maximum Minimum Maximum Units Conditions

TXINR System Clock 3 3 ns VDD = 3.0–3.6 V;
Rise Time TCLK = 20 ns
TXINF System Clock 3 3 ns VDD = 3.0–3.6 V;
Fall Time TCLK = 20 ns
CIN Input capacitance 10 typical 10 typical pF

Table 237 lists simulated inductance, capacitance, and resistance results for the 144-pin
LQFP package at 100 MHz operating frequency.

Table 237. Typical 144-LQFP Package Electrical Characteristics

Lead Inductance (nH) Capacitance (pF) Resistance (mohm)

Longest 6.430 1.100 62.9
Shortest 4.230 1.070 52.6

Note: Package vendor-supplied; 100 MHz operating frequency

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External Memory Read Timing

Figure 68 and Table 238 display the timing for external memory reads.

TCLK

PHI

T1 T2

ADDR[23:0]

T3 T4
DATA[7:0]
(input)

T5 T6

CSx

T7 T8

MREQ

T9 T10

RD

Figure 68. External Memory Read Timing

Table 238. External Memory Read Timing

Delay (ns)

Parameter Abbreviation Minimum Maximum

T1 PHI Clock Rise to ADDR Valid Delay — 8.5
T2 PHI Clock Rise to ADDR Hold Time 1.0 —
T3 DATA Valid to PHI Clock Rise Setup Time 0.5 —
T4 PHI Clock Rise to DATA Hold Time 0.5 —
T5 PHI Clock Rise to CSx Assertion Delay 2.6 8.0
T6 PHI Clock Rise to CSx Deassertion Delay 0.0 6.0
T7 PHI Clock Rise to MREQ Assertion Delay 2.6 7.0
T8 PHI Clock Rise to MREQ Deassertion Delay 1.0 6.3

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Table 238. External Memory Read Timing (Continued)

Delay (ns)

Parameter Abbreviation Minimum Maximum

T9 PHI Clock Rise to RD Assertion Delay 2.7 7.0
T10 PHI Clock Rise to RD Deassertion Delay 1.0 6.3

External Memory Write Timing

Figure 69 and Table 239 on page 348 display the timing for external memory Writes.

TCLK

PHI

T1 T2

ADDR[23:0]

T3 T4
DATA[7:0]
(output)

T5 T6

CSx

T7 T8

MREQ

T9 T10

WR

Figure 69. External Memory Write Timing

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Table 239. External Memory Write Timing

Delay (ns)

Parameter Abbreviation Minimum Maximum

T1 PHI Clock Rise to ADDR Valid Delay — 8.5
T2 PHI Clock Rise to ADDR Hold Time 1 —
T3 PHI Clock Fall to DATA Valid — 2.5
T4 PHI Clock Rise to DATA Hold Time 1.0 —
T5 PHI Clock Rise to CSx Assertion Delay 2.3 10.8
T6 PHI Clock Rise to CSx Deassertion Delay 0.0 6.0
T7 PHI Clock Rise to MREQ Assertion Delay 2.3 7.0
T8 PHI Clock Rise to MREQ Deassertion Delay 2.3 6.5
T9 PHI Clock Fall to WR Assertion Delay — 1.0
T10 PHI Clock Rise to WR Deassertion Delay* 0.0 5.0
WR Deassertion to ADDR Hold Time 0.4 —
WR Deassertion to DATA Hold Time 0.5 —
WR Deassertion to CSx Hold Time 1.2 —
WR Deassertion to MREQ Hold Time 0.5 —
*At the conclusion of a Write cycle, deassertion of WR always occurs before any change to
ADDR, DATA, CSx, or MREQ.

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External I/O Read Timing

Figure 70 and Table 240 display the timing for external I/O reads. PHI clock rise/fall to
signal transition timing is independent of the particular bus mode employed (eZ80®,
Z80®, Intel, or Motorola).

TCLK

PHI

T1 T2

ADDR[23:0]

T3 T4
DATA[7:0]
(input)

T5 T6

CSx

T7 T8

IORQ

T9 T10

RD

Figure 70. External I/O Read Timing

Table 240. External I/O Read Timing

Delay (ns)

Parameter Abbreviation Minimum Maximum

T1 PHI Clock Rise to ADDR Valid Delay — 7.3
T2 PHI Clock Rise to ADDR Hold Time 1.0 —
T3 DATA Valid to PHI Clock Rise Setup Time 0.5 —
T4 PHI Clock Rise to DATA Hold Time 0.0 —
T5 PHI Clock Rise to CSx Assertion Delay 2.0 8.5
T6 PHI Clock Rise to CSx Deassertion Delay 0.0 6.0
T7 PHI Clock Rise to IORQ Assertion Delay 2.6 7.0

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Table 240. External I/O Read Timing (Continued)

Delay (ns)

Parameter Abbreviation Minimum Maximum

T8 PHI Clock Rise to IORQ Deassertion Delay 1.0 6.3
T9 PHI Clock Rise to RD Assertion Delay 2.7 7.0
T10 PHI Clock Rise to RD Deassertion Delay 0.5 6.3

External I/O Write Timing

Figure 71 and Table 241 on page 351 display the timing for external I/O Writes. PHI clock
rise/fall to signal transition timing is independent of the particular bus mode employed
(eZ80®, Z80®, Intel, or Motorola).

TCLK

PHI

T1 T2

ADDR[23:0]

T3 T4
DATA[7:0]
(output)

T5 T6

CSx

T7 T8

IORQ

T9 T10

WR

Figure 71. External I/O Write Timing

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Table 241. External I/O Write Timing

Delay (ns)

Parameter Abbreviation Min Max

T1 PHI Clock Rise to ADDR Valid Delay — 7.3
T2 PHI Clock Rise to ADDR Hold Time 1.0 —
T3 PHI Clock Fall to DATA Valid — 2.5
T4 PHI Clock Rise to DATA Hold Time 1.0 —
T5 PHI Clock Rise to CSx Assertion Delay 2.3 10.8
T6 PHI Clock Rise to CSx Deassertion Delay 1.0 6.0
T7 PHI Clock Rise to IORQ Assertion Delay 2.4 7.0
T8 PHI Clock Rise to IORQ Deassertion Delay 1.0 6.3
T9 PHI Clock Fall to WR Assertion Delay — 1.0
T10 PHI Clock Rise to WR Deassertion Delay* 0.0 5.0
WR Deassertion to ADDR Hold Time 0.4 —
WR Deassertion to DATA Hold Time 0.5 —
WR Deassertion to CSx Hold Time 1.2 —
WR Deassertion to IORQ Hold Time 0.5 —
*At the conclusion of a Write cycle, deassertion of WR always occurs before any change to ADDR,
DATA, CSx, or IORQ.

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Wait State Timing for Read Operations

Figure 72 displays the extension of the memory access signals using a single Wait state for
a Read operation. This Wait state is generated by setting CS_WAIT to 001 in the Chip
Select Control Register.

TCLK TWAIT

SCLK

ADDR[23:0]

DATA[7:0]
(output)

CSx

MREQ

RD

INSTRD

Figure 72. Wait State Timing for Read Operations

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Wait State Timing for Write Operations

Figure 73 displays the extension of the memory access signals using a single Wait state for
a Write operation. This Wait state is generated by setting CS_WAIT to 001 in the Chip
Select Control Register.

TCLK TWAIT

PHI

ADDR[23:0]

DATA[7:0]
(output)

CSx

MREQ

WR

Figure 73. Wait State Timing for Write Operations

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General-Purpose Input/Output Port Input Sample Timing

Figure 74 displays timing of the GPIO input sampling. The input value on a GPIO port pin
is sampled on the rising edge of the system clock. The port value is then available to the
CPU on the second rising clock edge following the change of the port value.

TCLK

PHI

Port Value
Changes to 0
GPIO Pin
Input Value

GPIO Input 0 Latched

Data Latch Into GPIO
Data Register
GPIO Data Register
GPIO Data Value 0 Read
READ on Data Bus by eZ80

Figure 74. Port Input Sample Timing

General-Purpose I/O Port Output Timing

Figure 75 and Table 242 on page 355 display timing information for GPIO port pins.

TCLK

PHI

Port Output

T1 T2

Figure 75. GPIO Port Output Timing

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Table 242. GPIO Port Output Timing

Delay (ns)

Parameter Abbreviation Minimum Maximum

T1 PHI Clock Rise to Port Output Valid Delay — 5
T2 PHI Clock Rise to Port Output Hold Time 1.0 —

External Bus Acknowledge Timing

Table 243 lists information on the bus acknowledge timing.

Table 243. Bus Acknowledge Timing

Delay (ns)

Parameter Abbreviation Minimum Maximum

T1 PHI Clock Rise to BUSACK Assertion Delay 2.8 7.1
T2 PHI Clock Rise to BUSACK Deassertion Delay 1.5 6.5

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Packaging
Figure 76 displays the 144-pin low-profile quad flat package (LQFP) for the eZ80F91
device.

HD
D A
A2
A1

CL

F E HE

CL DETAIL A

LE
c

b e

Figure 76. 144-Lead Plastic Low-Profile Quad Flat Package (LQFP)

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Ordering Information
Table 244 lists part name, a product specification index code, and a brief description of
each part. Order the eZ80F91 microcontroller from Zilog®, using the following part num-
bers. For more information on ordering, please consult your local Zilog sales office. The
Zilog website (www.zilog.com) lists all regional offices and provides additional eZ80F91
microcontroller product information.

Table 244. Ordering Information

Part PSI Description

eZ80F91 eZ80F91AZ050EK 144-pin LQFP, 256 KB Flash memory, 8 KB SRAM, 50 MHz,
Extended Temperature
ZUSBASC0200ZACG Acclaim! Smart Cable

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Part Number Description

Zilog® part numbers consists of number of components as described below:

eZ80 F91 AZ 050 E K

Environmental Flow
K = Lead-free RoHS compliant plastic
packaging compound
Temperature Range
E = Extended, –40 °C to +105 °C

Speed
0 = eZ80Acclaim!
50 = Speed
Package
AZ = LQFP (also called VQFP)

Product Number

Zilog eZ80® CPU

Example: Part number eZ80F91AZ050EK is an eZ80F91 Acclaim! product in a LQFP

package, operating with a 50 MHz external clock frequency over a -40 ºC to +105 ºC tem-
perature range and built using the Lead-Free environmental flow.

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Index Address Bus 6, 7

address bus 58, 68, 70, 71, 74, 75, 78, 81, 82,
85, 86, 161, 238, 239, 249, 255
address bus, 24-bit 27
Numerics Addressing, I2C 223
100-pin LQFP package 4, 5 ALARM 160, 174
16-bit clock divisor value 182, 206 ALARM bit flag 173
16-bit divisor count 182, 206 alarm condition 160, 161, 173, 174
32 KHz Real-Time Clock Crystal Oscillator Opera- AND/OR Gating of the PWM Outputs 148, 149
tion 337 Arbiter, EMAC 289
Arbitration, I2C 215
asynchronous communications protocol 175, 176
A asynchronous communications protocol bits 176
AAK 217, 218, 220, 221, 222, 226, 227 asynchronous serial data 11, 14
Absolute Maximum Ratings 339
Absolute maximum ratings 339
AC Characteristics 344 B
ACK 213, 217, 218, 219, 220, 221, 223, 228 Basic Timer Operation 122
Acknowledge 213 Basic Timer Register Set 130
Acknowledge, I2C 213 Baud Rate Generator 181
ADDR0 6 Baud Rate Generator Functional Description 205
ADDR1 6 BCD 159, 173, 174
ADDR10 6 Binary Operation 161, 162, 163, 166, 167, 168,
ADDR11 6 169, 170, 171, 172
ADDR12 7 binary operation 159
ADDR13 7 binary-coded-decimal 159
ADDR14 7 Binary-Coded-Decimal Operation 161, 164, 165,
ADDR15 7 166, 167, 168, 169, 170, 171, 172
ADDR16 7 bit generation 175, 176
ADDR17 7 Block Diagram 2
ADDR18 7 Boot Block 25, 97, 107, 109
ADDR19 7 Boundary Scan Cell Functionality 260
ADDR2 6 Boundary Scan Instructions 264
ADDR20 7 Boundary-Scan Architecture 257
ADDR21 7 break detection 175, 185
ADDR22 7 Break Point Halting 126
ADDR23 7 break point trigger functions 257
ADDR3 6 BRG Control Registers 182
ADDR4 6 Bus Acknowledge Cycle 70
ADDR5 6 bus acknowledge cycle 6, 8, 9, 89, 90, 91, 94
ADDR6 6 bus acknowledge pin 70, 249
ADDR7 6 Bus Arbiter 89
ADDR8 6 Bus Arbitration Overview 211
ADDR9 6 Bus Clock Speed, I2C 230

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

Bus Mode Controller 70 clock polarity bit 204

bus mode state 71, 72, 75 Clock Synchronization for Handshake 216
Bus modes 70 Clock Synchronization, I2C 214
bus modes 71, 84, 88 Clocking Overview 211
Bus Modes, Switching Between 84 COL 22
Bus Requests During ZDI Debug Mode 238 Complex triggers 257
bus timing 70 CONTINUOUS mode 125
BUSACK 9, 70, 239, 249, 255, 355 Continuous Mode 123, 126
BUSACK pin 89, 249, 255 continuous mode 121, 132, 138, 139
BUSREQ 9, 70, 255 Control Transfers, UART 179
BUSREQ pin 89, 239, 249, 255 CPHA—see clock phase 202, 203, 208
Byte Format, I2C 213 CPOL—see clock polarity 203, 208
CRC 294, 295, 299, 300, 312
CRS 22, 307
C CS0 7, 65, 66, 67, 68
C source-level debugging 231 CS1 7, 65, 66, 67, 68
capture flag 128 CS2 7, 65, 67, 68
Carrier Sense 307 CS3 7, 65, 67, 68
carrier sense 303 CTS 191, 193
carrier sense window 308 CTS0 12, 198
Carrier Sense Window Referencing 308 CTS1 15
Carrier Sense, MII 22 Customer Feedback Form 374
Chain Sequence and Length, JTAG Boundary Scan
260
Characteristics, electrical D
Absolute maximum ratings 339 DATA bus 78
Charge Pump 265 Data Bus 8
charge pump 269 data bus 70, 71, 73, 74, 75, 82, 88, 161, 238,
Charge Pump, PLL 266 239, 249, 255
Chip Select Registers 85 Data Carrier Detect 13, 16, 193
Chip Select x Bus Mode Control Register 88 Data Set Ready 13, 16, 193
Chip Select x Control Register 87 Data Terminal Ready 12, 15, 191
Chip Select x Lower Bound Register 85 Data Transfer Procedure with SPI configured as a
Chip Select x Upper Bound Register 86 Slave 206
Chip Select/Wait State Generator block 6 Data Transfer Procedure with SPI Configured as the
Chip Selects During Bus Request/Bus Acknowl- Master 205
edge Cycles 70 data transfer, SPI 209
Clear to Send 12, 15, 193 Data Transfers, UART 179
CLK_MUX 269 Data Validity, I2C 212
clock divisor value, 16-bit 182, 206 DATA0 8
clock initialization circuitry 258 DATA1 8
Clock Peripheral Power-Down Registers 46 DATA2 8
clock phase 202 DATA3 8
clock phase bit 204 DATA4 8

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

DATA5 8 EMAC Interpacket Gap 306

DATA6 8 EMAC Interpacket Gap Overview 306
DATA7 8 EMAC Interpacket Gap Register 307
DC Characteristics 339 EMAC Interrupt Enable Register 323
DCD 190, 193 EMAC Interrupt Status Register 325
DCD0 13, 198 EMAC Interrupts 292
DCD1 16 EMAC Maximum Frame Length Register—Low
DCTS 193 and High Bytes 309
DDCD 193 EMAC memory 288, 289
DDSR 193 EMAC MII Management Register 313
Divider, PLL 266 EMAC MII Status Register 327
divisor count 206 EMAC Non-Back-To-Back IPG Register—Part 1
divisor count, 16-bit 182 308
DSR 191, 193 EMAC Non-Back-To-Back IPG Register—Part 2
DSR0 13, 198 308
DSR1 16 EMAC PHY Address Register 315
DTACK 81, 82 EMAC PHY Configuration Data Register—Low
DTR 191, 193 Byte 314
DTR0 12, 198 EMAC PHY Read Status Data Register—Low and
DTR1 15 High Bytes 326
EMAC PHY Unit Select Address Register 316
EMAC RAM 93, 94, 95, 96
E EMAC Receive Blocks Left Register—Low and
EC0 17, 127, 129, 132 High Bytes 330
EC1 22, 127, 129, 132 EMAC Receive High Boundary Pointer Regis-
edge-selectable interrupts 55 ter—Low and High Bytes 320
Edge-Triggered Interrupts 54 EMAC Receive Read Pointer Register—Low and
EI, Op Code Map 280 High Bytes 321
EMAC 287 EMAC Receive Write Pointer Register—High Byte
EMAC Address Filter Register 311 329
EMAC Boundary Pointer Register—Low and High EMAC Receive Write Pointer Register—Low Byte
Bytes 319 328
EMAC Boundary Pointer Register—Upper Byte EMAC Receiver Interrupts 292
319 EMAC Registers 297
EMAC Buffer Size Register 322 EMAC Reset Control Register 317
EMAC Configuration Register 1 299 EMAC Shared Memory Organization 292
EMAC Configuration Register 2 301 EMAC Station Address Register 304
EMAC Configuration Register 3 302 EMAC System Interrupts 292
EMAC Configuration Register 4 303 EMAC Test Register 298
EMAC FIFO Data Register—Low and High Bytes EMAC Transmit Lower Boundary Pointer Regis-
332 ter—Low and High Bytes 318
EMAC FIFO Flags Register 333 EMAC Transmit Pause Timer Value Regis-
EMAC Functional Description 288 ter—Low and High Bytes 305
EMAC Hash Table Register 312 EMAC Transmit Polling Timer Register 316

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

EMAC Transmit Read Pointer Register—High FAST mode 211, 230

Byte 330 FCS 295, 296, 306
EMAC Transmit Read Pointer Register—Low Byte Features 1
329 Features, eZ80 CPU Core 39
EMAC Transmitter Interrupts 292 FIFO mode 176, 179
EMACMII module 287 Flash Address registers 100, 103, 110
Enabling and Disabling the WDT 116 Flash address registers 99
Endec 199 Flash Address Upper Byte Register 104
endec 195, 196, 198 Flash Column Select Register 112
ENDEC Mode 306 Flash Control Register 105
ENDEC mode 302 Flash Control Registers 102
endec signal pins 198 Flash controller 98, 99, 100, 106, 108
endec, IrDA 47 Flash controller clock 106
Erasing Flash Memory 101 Flash Data Register 103
Ethernet Media Access Controller 287 Flash Frequency Divider Register 106
event count input 132 Flash Interrupt Control Register 108
Event count mode 127 Flash Key Register 102
event count mode 128 Flash Memory 97
Event Counter 125, 127 Flash memory array 98, 109
event counter 127 Flash Memory Overview 98
External Bus Acknowledge Timing 355 Flash Page Select Register 109
external bus master 89, 90 Flash Program Control Register 112
external bus request 70, 235, 239 Flash Row Select Register 111
External I/O Read Timing 349 Flash Write/Erase Protection Register 107
External I/O Write Timing 350 frame check sequence 306
External Memory Read Timing 346 framing error 175, 177, 185, 192
External Memory Write Timing 347 frequency divider 98, 106
external pull-down resistor 51 full-duplex transmission 204
External Reset Input and Indicator 41 Functional Description, Infrared Encoder/Decoder
eZ80 Bus Mode 71 195
eZ80 bus mode 88 Functional Description, Serial Peripheral Interface
eZ80 CPU 8, 69, 70, 74, 81, 195, 241, 257 204
eZ80 Product ID Low and High Byte Registers 251
eZ80 Product ID Revision Register 252
eZ80 Webserver-i 2, 6, 8, 9, 19, 57, 58, 68, 115 G
eZ80 Webserver-i Block Diagram 3 General Purpose I/O Port Input Sample Timing 354
eZ80Acclaim! Flash Microcontrollers 1, 98 General Purpose I/O Port Output Timing 354
eZ80F91 device 4, 5, 27, 340 General-Purpose Input/Output 49
eZ80F92 252 GND 2
GPIO Control Registers 55
GPIO Interrupts 54
F GPIO modes 50, 52
f 71, 74, 346 GPIO Operation 49
falling edge 147, 148, 150, 155 GPIO Overview 49

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

GPIO port pins 41, 49, 55, 354 IEEE 802.3/4.2.3.2.1 Carrier Deference 307, 308
IEEE Standard 1149.1 257, 258
IEF1 59, 125, 253
H IEF2 59
HALT 10, 253, 277 IFLG bit 211, 216, 219, 221, 222, 223, 226, 229
HALT instruction 45 IM 0, Op Code Map 283
HALT Mode 45 IM 1, Op Code Map 283
HALT mode 1, 46, 245, 253 IM 2, Op Code Map 283
HALT_SLP 10, 253, 260 Information Page Characteristics 102
HALT, Op-Code Map 280 Infrared Encoder/Decoder 195
Handshake 216 Infrared Encoder/Decoder Register 199
handshake 175, 177 Infrared Encoder/Decoder Signal Pins 198
hash table 311 Input Capture 128
INPUT capture mode 130
Input capture mode 128
I input capture mode 127, 134
I/O Chip Select Operation 68 INSTRD 9
I/O Chip Selects, External 27 Instruction Store 4
I/O Read 99 0 Registers 249
I/O space 6, 8, 65, 68 Intel- 70
I2C Acknowledge bit 226 Intel Bus Mode 73
I2C bus 211, 214, 215 Intel Bus Mode (Separate Address and Data Buses)
I2C bus clock 211 74
I2C bus protocol 212 internal pull-up 50
I2C Clock Control Register 229 Internal RC oscillator 115
I2C control bit 217, 218, 220 internal RC oscillator 118
I2C Control Register 225 internal system clock 69
I2C Data Register 225 Interpacket Gap 306, 307
I2C Extended Slave Address Register 224 Interpacket gap 306
I2C Registers 223 interpacket gap 296, 308
I2C Software Reset Register 230 Interrupt Controller 57
I2C Status Register 227 interrupt enable 9
IC0 17, 127, 129, 134, 135, 139, 140, 141, 142, Interrupt Enable bit 225
152, 156 interrupt enable bit 160, 178
IC1 17, 127, 129, 134, 135, 139, 141, 152, 156 Interrupt Enable Flag 253
IC2 18, 127, 129, 134, 135, 139, 140, 141, 152, interrupt enable flag 125
156 Interrupt Input 198
IC3 18, 127, 129, 134, 135, 139, 141, 142, 152, interrupt input 11, 12, 13, 14, 15, 16
156 Interrupt Priority 61, 63
IEEE 1149.1 specification 259, 264 interrupt priority 63
IEEE 802.3 311 interrupt priority levels 60
IEEE 802.3 frames 300 Interrupt Priority Registers 60
IEEE 802.3 specification 301, 302 Interrupt request 133, 134
IEEE 802.3, 802.3(u) minimum values 306 interrupt request 54, 58, 108, 127

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

interrupt request signals 57 L

interrupt service routine 58, 59, 60 least-significant byte 58
interrupt service routine, SPI 58 level-sensitive interrupt modes 52
interrupt sources 152 level-sensitive interrupts 55, 198
interrupt vector 57, 58 Level-Triggered Interrupts 54
interrupt vector address 59, 60 Line break detection 175
interrupt vector bus 58 line status error 178
interrupt vector locations 58 Line status interrupt 185
interrupt vector table 58 line status interrupt 177, 179, 180
interrupt, higher-priority 62, 186 Lock Detect 265
interrupt, highest-priority 57, 58 lock detect 267
interrupts, edge-selectable 55 lock detect sensitivity 269
interrupts, level-sensitive 55 Lock Detect, PLL 266
Introduction to On-Chip Instrumentation 257 Loop Filter 265
Introduction, Zilog Debug Interface 231 loop filter 267, 273
IORQ 8, 9, 68, 71, 74, 75, 78 Loop Filter, PLL 13, 266
IORQ Assertion Delay 349, 351 loop mode 177
IORQ Deassertion Delay 350, 351 LOOP_FILT 259
IORQ Hold Time 351 Loopback Testing, Infrared Encoder/Decoder 198
IR_RXD 196, 198, 199 low-byte vector 57
IR_TxD modulation signal 11, 196, 198 LSB 59, 60, 138, 229, 304, 311
IrDA Encoder/Decoder 198 Lsb 291
IrDA encoder/decoder 11 lsb 136, 138, 140, 141, 144, 157, 158, 216,
IrDA endec 47 217, 218, 219, 220, 222, 310, 314, 318, 320,
IrDA Receive Data 11 321, 326, 328, 329
IrDA specifications 196
IrDA standard 195
IrDA standard baud rates 195 M
IrDA transceiver 198
maskable interrupt 46, 57, 60, 62
IrDA Transmit Data 11
Maskable Interrupts 57
IrDA—see Infrared Data Association 195
Mass Erase 101
IRQ 58
mass erase 107, 108, 112
irq_en 205, 208
MASS ERASE operation 102
ISR 58
Mass Erase operation 113
IVECT 57, 58, 59, 60
mass erase operation 101, 110
MASTER mode 203, 211, 226, 228, 229, 230
Master mode 222, 227
J master mode 222
Jitter, Infrared Encoder/Decoder 198 Master Mode Start bit 225
JTAG Boundary Scan 259 Master Mode Stop bit 226
JTAG interface 257, 264 MASTER mode, SPI 204
JTAG mode selection 258 Master Receive 211, 219
JTAG Test Mode 10 Master Transmit 216
MASTER TRANSMIT mode 211

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

master_en bit 204 Multibyte I/O Write (Row Programming) 100

Master-In, Slave-Out 202 multicast address 296, 312
Master-Out, Slave-In 202 multicast packet 311, 312
MAXF 299 multimaster conflict 204, 209
MAXF—see Maximum Frame Length 309 Multi-PWM Control Registers 153
Maximum Frame Length 309 Multi-PWM Mode 145
MBIST 96 Multi-PWM Power-Trip Mode 152
MBIST Control 96 Mux/CLK Sync 265
MDC 24, 314 MUX/CLK Sync, PLL 266
MDIO 25
Memory and I/O Chip Selects 65
Memory Built-In Self-Test controllers 96 N
Memory Chip Select Example 66 NACK 213, 217, 218, 220, 221, 226, 228
Memory Chip Select Operation 65 New Instructions, eZ80 CPU Core 39
Memory Chip Select Priority 66 NMI 9, 39, 46, 57, 115, 116, 117
Memory Read 99 NMI_flag bit 117
Memory Request 8 nmi_out bit 116
memory space 65, 68 Nonmaskable Interrupt 9, 39
Memory Write 101 Nonmaskable interrupt 278
Memory, EMAC 288 nonmaskable interrupt 46, 57, 115, 116
MII 287, 292, 306, 313, 324, 325, 326, 327 nonoverlapping delay, PWM 148, 151
MISO—see SPI Master In Slave Out 19, 202, 204 Not Acknowledge 213
mode fault 209
Mode Fault error flag 202
Mode Fault flag 204 O
Mode Fault, SPI Flag 204 OC0 20, 127, 129, 133, 135, 143, 144, 145
Modem Status 186, 193 OC1 20, 127, 129, 133, 135
Modem status 178 OC2 20, 127, 129, 133, 135
modem status 179, 180, 190 OC3 21, 127, 129, 133, 135, 144, 145
modem status interrupt 198 OCI Activation 258
Modem status signal 12, 13, 15, 16 OCI clock pin 258
MODF 202, 204, 209 OCI Interface 258
Module Reset, UART 179 On-Chip Instrumentation, Introduction to 257
MOSI—see SPI Master Out Slave In 19, 202, 203, on-chip pull-up 340
204 On-chip RAM 65, 93, 94
Motorola Bus Mode 80 Op Code maps 280
Motorola-compatible 70 Op-Code Map 280
mpwm_en 146, 153 Open source I/O 50
MREQ 8, 9, 65, 71, 74, 75, 78, 346, 348 Open-drain I/O 50
MREQ Hold Time 348 open-drain I/O 50
MSB 58, 139 open-drain mode 50
Msb 291 Open-drain output 50
msb 109, 137, 139, 141, 142, 145, 157, 158, open-drain output 211
213, 237, 310, 318, 327, 329, 330, 331 open-source mode 51

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

Open-source output 50 PD2 12, 198

open-source output 11, 12, 13, 14, 15, 16, 17, 18, PD3 12
19 PD4 12
Operating Modes, I2C 216 PD5 13
Operation of the eZ80F91 Device during ZDI Break PD6 13
Points 238 PD7 13, 198
Ordering Information 358 Phase Frequency Detector 265
Output Compare 128 Phase Frequency Detector, PLL 266
Output compare mode 143 PHI 19, 261
output compare mode 127, 128, 130, 133 PHI Clock output 48
overrun condition, receiver 178 PHY 22, 24, 28, 29, 292, 296, 314, 315, 325,
Overrun error 192 326, 327
overrun error 175, 177, 185 PHY, MII 288, 313
Overview, Phase-Locked Loop 265 Pin Characteristics 6
Pin Coverage, JTAG Boundary Scan 259
Pin Description 4
P PLL Characteristics 272
PA7 150 PLL Control Register 0 269
Packaging 357 PLL Control Register 1 270
Page Erase 101 PLL Divider Control Register—Low and High
page erase 112 Bytes 268
Page Erase operation 113 PLL Loop Filter 13
page erase operation 101, 109 PLL Normal Operation 267
PAIR_EN 153, 154 PLL Registers 268
parity error 177, 188, 192 PLL_VDD 268
Part Number Description 359 PLL_VSS 268
PB0 17 Poll Mode Transfers 181
PB1 17 POP, Op Code Map 280, 282, 284
PB2 17 POR Voltage Threshold 341
PB3 18 POR voltage threshold 42
PB4 18 POR/VBO analog RESET duration 341
PB5 18 POR/VBO DC current consumption 341
PB6 19 POR/VBO Hysteresis 341
PB7 19 Port A 20, 21, 47, 49, 58, 62, 63, 145
PC0 14, 20 Port x Alternate Register 1 56
PC1 14, 20 Port x Alternate Register 2 56
PC2 15, 20 Port x Data Direction Registers 55
PC3 15, 21 Port x Data Registers 55
PC4 15, 21 Potential Hazards of Enabling Bus Requests During
PC5 16, 21 Debug Mode 239
PC6 16, 22 Power connections 2
PC7 16, 22 Power Requirement to the Phase-Locked Loop
PD0 11, 198 Function 268
PD1 11, 198 Power-On Reset 41, 42, 340

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

power-trip 153 PWM1 20, 21, 127, 129, 147, 149

Power-Trip Mode, Multi-PWM 152 PWM1 falling edge end-of-count 148, 151
power-trip, multi-PWM 152 PWM1 rising edge end-of-count 148, 151
Primary Crystal Oscillator Operation 335 pwm1_en 153
Program Counter 41, 45, 46, 59, 97, 250, 251, PWM1FH 148
255 PWM1RH 157, 158
Program Counter, Starting 60 PWM1RL 157, 158
Programmable Reload Timers 121 PWM2 20, 22, 127, 129, 147
Programming Flash Memory 99 PWM2 falling edge end-of-count 148
Promiscuous Mode 311 PWM2 rising edge end-of-count 148
PT_EN 153 pwm2_en 153
pull-up resistor, external 51, 211 PWM2RH 148
Pulse-Width Modulation Control Register 1 153 PWM3 21, 22, 127, 147
Pulse-Width Modulation Control Register 2 154 pwm3_en 153
Pulse-Width Modulation Control Register 3 156 PWMCNTRL1 146
Pulse-Width Modulation Falling Edge—High Byte PWMCNTRL2 148
158 PWMCNTRL3 152
Pulse-Width Modulation Falling Edge—Low Byte
158
Pulse-Width Modulation Rising Edge—High Byte Q
157 QMC 311
Pulse-Width Modulation Rising Edge—Low Byte qualified multicast messages 311
157
PUSH, Op Code Map 280, 282, 284
PWM delay feature 151 R
PWM edge transition values 148, 149 RAM 93
PWM generator 145, 146, 147, 148, 153 RAM Address Upper Byte Register 95
PWM generators 146 RAM Control Register 94
PWM Master Mode 148 Random Access Memory 93
PWM mode 121, 127, 130, 131, 134 RD 8, 65, 68, 71, 74, 75, 78
PWM mode, Multi- 145, 146, 148, 149, 153 RD Assertion Delay 347, 350
PWM nonoverlapping delay 148 RD Deassertion Delay 347, 350
PWM nonoverlapping delay time 151 Reading Flash Memory 98
PWM Nonoverlapping Output Pair Delays 150 Reading the Current Count Value 122
PWM output pairs 148 Real-Time Clock 41, 45, 159, 160, 161, 173
PWM outputs 149, 150, 152 Real-Time Clock Alarm 160
PWM Outputs, AND/OR Gating 148, 149 Real-Time Clock alarm 45
PWM outputs, inverted 147 Real-Time Clock Alarm Control Register 173
PWM pairs 149 Real-Time Clock Alarm Day-of-the-Week Register
PWM power-trip state 152 172
PWM signals 145 Real-Time Clock Alarm Hours Register 171
PWM trip levels 156 Real-Time Clock Alarm Minutes Register 170
PWM waveform 149 Real-Time Clock Alarm Seconds Register 169
PWM0 150 Real-Time Clock Battery Backup 160

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

Real-Time Clock Century Register 168 RTC_XOUT 10

Real-Time Clock Control Register 173 RTS 191, 193, 198
Real-Time Clock Day-of-the-Month Register 165 RTS0 12
Real-Time Clock Day-of-the-Week Register 164 RTS1 15
Real-Time Clock Hours Register 163 RX_CLK 24
Real-Time Clock Minutes Register 162 Rx_CLK 23
Real-Time Clock Month Register 166 Rx_DV 24
Real-Time Clock Oscillator and Source Selection Rx_ER 23
160 RxD0 11, 24
Real-Time Clock Overview 159 RxD1 14, 24
Real-Time Clock Recommended Operation 160 RxD2 24
Real-Time Clock Registers 161 RxD3 24
Real-Time Clock Seconds Register 161 RxDMA 290
Real-Time Clock signal 128
Real-Time Clock source 115, 118, 125
Real-Time Clock Year Register 167 S
Receive, Infrared Encoder/Decoder 196 Schmitt Trigger 9
Recommended Usage of the Baud Rate Generator Schmitt trigger 9
181 Schmitt Trigger Input 9, 11, 14, 15, 17, 18, 25
Register Set for Capture in Timer 1 130 Schmitt-trigger input buffers 49
Register Set for Capture/Compare/PWM in Timer 3 SCK 18, 202
130 SCK Idle State 203
Request to Send 12, 15, 191 SCK pin 204, 208
RESET 9, 41, 42, 45, 46, 50, 65, 93, 94, 105, SCK Receive Edge 203
107, 115, 116, 161, 164, 165, 166, 167, 168, SCK signal 204
169, 170, 171, 172, 173, 174, 181, 182, 199, SCK Transmit Edge 203
205, 206, 243, 245, 258, 260, 341 SCL 19, 211, 212, 213, 229
Reset controller 41, 42 SCL line 214, 216
RESET event 41, 49 SCLK 41, 150, 265, 314
RESET mode timer 41, 42 SClk 266
RESET Or NMI Generation 116 Sclk 267
Reset States 66 SCLK periods 155
RESET_OUT 260 SDA 19, 211, 212, 213, 222
Resetting the I2C Registers 223 SDA line 215
RI 177, 191, 193 see system reset 8
RI0 13, 198 serial bus, SPI 209, 210
RI1 16, 51 Serial Clock 211
Ring Indicator 13, 16, 193 Serial Clock, I2C 19
rising edge 147, 148, 150, 155 Serial Clock, SPI 18, 202
rst_flag bit 116 Serial Data 211
RTC Oscillator Input 128 serial data 202
RTC Supply Voltage 340 Serial Data, I2C 19
RTC_VDD 10 Serial Peripheral Interface 1, 47, 58, 62, 201,
RTC_XIN 10 202, 204

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

Serial Peripheral Interface flag 209, 210 SPIF status bit—see Serial Peripheral Interface flag
Serial Peripheral Interface Functional Description 209
204 SPIF—see Serial Peripheral Interface flag 204,
Setting Timer Duration 122 209
Single Pass Mode 123 SRA 279
single pass mode 121, 124, 132 SRA, Op Code Map 281, 285
Single-Byte I/O Write 99 SRAM 1, 104, 231, 329
SLA 218, 220, 224, 279 SRAM, internal Ethernet 292
SLA, Op Code Map 285, 286 SS—see Slave Select 17, 202, 203, 204, 206,
SLA, Op Code map 281 208
SLAVE mode 211, 225, 228 STA 225
slave mode 222, 223, 224 standard mode 211
SLAVE mode, SPI 204 Standard VHDL Package STD_1149_1_2001 260
Slave Receive 211, 222 START and STOP Conditions 212
Slave Select 202 START condition 212, 215, 216, 218, 219, 221,
Slave Transmit 211, 221 222, 223, 225, 227, 228, 229, 230
Slave Transmit mode 226 start condition 213
slave transmit mode 221, 222 Start Condition, ZDI 233
SLEEP Mode 45 Starting Program Counter 59, 60
SLEEP mode 173, 245, 253 STOP condition 212, 213, 215, 219, 221, 222,
sleep-mode recovery 173 226, 227, 229, 230
sleep-mode recovery reset 174 Supply Voltage 340
Software break point instruction 257 supply voltage 2, 42, 50, 211, 267, 339
Specialty Timer Modes 126 Switching Between Bus Modes 84
SPI Baud Rate Generator 205 System clock 47, 48, 115
SPI Baud Rate Generator Registers—Low Byte and system clock 41, 45, 51, 54, 118, 125, 127, 132,
High Byte 206 150, 181, 205, 229, 230, 238, 258, 266, 289,
SPI Control Register 208 354
SPI Data Rate 205 system clock cycle 75, 78, 122
SPI Flag 204 System Clock Cycle Time 344
SPI interrupt service routine 58 system clock cycles 9, 68, 71, 72, 75, 78, 82,
SPI Master device 206 116, 258
SPI master device 19 System clock divider 132
SPI MASTER mode 204 System Clock Fall Time 345
SPI mode 17 System Clock Frequency 122, 181, 205
SPI Receive Buffer Register 210 system clock frequency 99, 101, 105, 106, 232
SPI Registers 206 System Clock High Time 344
SPI serial bus 209 system clock jitter 127
SPI Serial Clock 18 System Clock Low Time 344
SPI Signals 202 System Clock Oscillator Input 14
SPI slave device 19 System Clock Oscillator Output 13
SPI SLAVE mode 204 system clock period 258
SPI Status Register 205, 209 system clock periods 151
SPI Transmit Shift Register 205, 206, 209 System Clock Rise Time 345

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

system clock rising edge 181, 205 Timer Output Compare Value Register—High Byte
System Clock Source 269 145
System clock source 270 Timer Output Compare Value Register—Low Byte
system clock source 269 144
system clock, high-frequency 205 Timer Port Pin Allocation 129
system clock, internal 69 Timer Registers 130
system RESET 41, 162, 163 Timer Reload Register—High Byte 139
system reset 160, 183, 267, 297 Timer Reload Register—Low Byte 138
TMS 258, 259
TOUT0 21, 129
T TOUT1 21, 129
T2 clock 151 Trace buffer memory 257
T2 end-of-count 151 Trace history buffer 257
T23CLKCN 151 Transferring Data 213
TAP 264 transmit shift register 176, 185, 188, 191
TAP Reset 258 Transmit Shift Register, SPI 204, 205, 206, 209,
TCK 233, 258, 259, 264 210
TDI 258, 259, 260 Transmit, Infrared Encoder/Decoder 196
TDO 258, 259, 260 trigger-level detection logic 176
TERI 193 TRIGOUT 258, 260
Test Access Port 257 tristate 152
Test Access Port instruction 264 TRSTN 258, 259
Test Access Port state register 258 Tx_CLK 23
Test Mode 258 Tx_EN 23
Time-Out Period Selection 116 Tx_ER 23
Timer Control Register 132 TxD0 11, 23
Timer Data Register—High Byte 137 TxD1 14, 23
Timer Data Register—Low Byte 136 TxD2 23
Timer Input Capture Control Register 139 TxD3 22
Timer Input Capture Value A Register—High Byte TxDMA 290
141
Timer Input Capture Value A Register—Low Byte
140 U
Timer Input Capture Value B Register—High Byte UART Baud Rate Generator Register—Low and
142 High Bytes 182
Timer Input Capture Value B Register—Low Byte UART FIFO Control Register 187
141 UART Functional Description 176
Timer Input Source Selection 125 UART Functions 176
Timer Interrupt Enable Register 133 UART Interrupt Enable Register 184
Timer Interrupt Identification Register 135 UART Interrupt Identification Register 186
Timer Interrupts 124 UART Interrupts 178
Timer Output 125 UART Line Control Register 188
Timer Output Compare Control Register 1 142 UART Line Status Register 191
Timer Output Compare Control Register 2 143 UART Modem Control 177

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

UART Modem Control Register 190 Wait States 68

UART Modem Status Interrupt 179 Watchdog Timer 1, 45, 115, 116, 238
UART Modem Status Register 193 Watchdog Timer Control Register 117
UART Receive Buffer Register 184 Watchdog Timer Operation 116
UART Receiver 177 Watchdog Timer Registers 117
UART Receiver Interrupts 178 Watchdog Timer Reset Register 119
UART Recommended Usage 179 Watchdog Timer time-out 41, 45, 46
UART Registers 183 wcOl 209
UART Scratch Pad Register 194 WCOL—see Write Collision 204, 205
UART Transmit Holding Register 183 WDT 41, 45, 115, 116, 117
UART Transmitter 176 WDT clock source 115, 116, 118
UART Transmitter Interrupt 178 WDT oscillator 117
Universal Asynchronous Receiver/Transmitter 175 WDT time-out 115, 116, 117, 119
Usage, JTAG Boundary Scan 264 WDT time-out period 116, 118
WP 25
WP pin 97, 107, 108, 109
V WR 8, 65, 68, 71, 75, 78, 348, 351
VBO 41, 42, 340 Write Collision 205
VBO pulse reject period 341 write collision 204
VBO Voltage Threshold 341 write collision, SPI 209
VCC 2, 42, 341
VCC ramp rate 341
VCO 266, 273 X
vco 273 XIN input pin 335
VLAN tagged frame 309 XOUT output pin 335
Voltage Brown-Out 340
Voltage Brown-Out Reset 42
Voltage Controlled Oscillator 265 Z
Voltage Controlled Oscillator, PLL 266 Z80- 70
voltage signal, high 100 Z80 Bus Mode 71
voltage, input 266 ZCL 233, 236, 243
voltage, peak-to-peak 273 ZDA 233, 243, 258
voltage, supply 2, 50, 211, 267, 339, 340 ZDI 231, 232, 257
ZDI Address Match Registers 241
ZDI Block Read 238
W ZDI Block Write 236
WAIT 1, 9, 75, 78, 81, 82 ZDI Break Control Register 242
WAIT condition 112 ZDI Bus Control Register 249
WAIT Input Signal 69 ZDI Bus Status Register 255
WAIT pin, external 71 ZDI Clock and Data Conventions 233
WAIT state 72, 78, 352, 353 ZDI clock pin 233
Wait State Timing for Read Operations 352 ZDI data pin 233
Wait State Timing for Write Operations 353 ZDI debug control 257
WAIT states 58, 75, 78, 87, 239 ZDI Master Control Register 245

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

ZDI Read Memory Register 255

ZDI Read Operations 237
ZDI Read Register Low, High, and Upper 254
ZDI Read/Write Control Register 247
ZDI Read-Only Registers 240
ZDI Register Addressing 235
ZDI Register Definitions 241
ZDI Single-Bit Byte Separator 234
ZDI Single-Byte Read 237
ZDI Single-Byte Write 236
ZDI Start Condition 233
ZDI Status Register 253
ZDI Write Data Registers 246
ZDI Write Memory Register 250
ZDI Write Only Registers 239
ZDI Write Operations 236
ZDI_BUS_STAT 239, 241, 255
ZDI_BUSACK_EN 238
ZDI_BUSAcK_En 255
ZDI-Supported Protocol 232
ZDS II 231
Zilog Debug Interface 231, 257
Zilog Developer Studio II 231

PS019217-1222 Index
 eZ80F91 MCU
Product Specification

374

Customer Support
For answers to technical questions about the product, documentation, or any other issues
with Zilog’s offerings, visit Zilog’s Knowledge Base at http://www.zilog.com/kb.
For any comments, detail technical questions, or reporting problems, visit Zilog’s Techni-
cal Support at http://support.zilog.com.

PS019217-1222