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Address Decoding

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6 views12 pages

Address Decoding

Uploaded by

afifmostakim
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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• Produces a signal to ENABLE desired

memory block (RAM, ROM) or port .


• Makes sure that only one device is ‘alive’ to
communicate with the data bus.
Let us design a microcomputer with 32 kB ROM and 16 kB
RAM. Available ROM IC is 2732 with 4kB storage while
each RAM stores 2 kB data. Thus we will require parallel
operation of 8 ROM and 8 RAMs. A successful design
should allow the user to address each memory block
separately.
•G1, G2A, and G2B will be used to
enable the decoder IC.
•You can select 8 different blocks
using one decoder.
•Common bits of their chip select
address will be used for
‘selecting’/’enabling’ the decoder.
• ROM addresses occupied upto A14
1000 0000
• By reversing the very next bit we can
1001 0001
allocate equal area of storage
1010 0010
• Here we need less area for RAM than
1011 0011
we needed for ROM
1100 0100
• When in need of even more space, we 1101 0101
will have to keep in mind we can start 1110 0110
allocating address for RAM only after 1111 0111
07FFFH i.e. the final address of ROM.
A A A A A A A A A A A A A A A A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Blo Start 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ck
1 End 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1

Blo Start 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
ck
2 End 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1

Blo Start 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
ck
8 End 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Let us allocate address for 8 Seven Segment Displays
connected to our microcomputer. Keep in mind, 8086 can
only handle 64 kB i/o.
PORTS DO NOT HAVE ‘OFFSET/SEGMENT’ ADDRESS.
Memory Mapped I/O
• Treat I/O ports simply as memory blocks
• Allows direct I/O operation on ports : MOV AX, DS:BYTE
PTR 0C23A H
• Limits space for memory blocks
Direct I/O
• Separate space for ports (allowed in 8086)S

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