University of Gondar Institute of Technology

IoT
Digital Logic Design
(CoEng3092)

Lecture-05: Sequential Logic Circuit

By Beyene Jember
 Objectives
 Use logic gates to construct basic latches
 Analyze the operation of a latch made from NAND or NOR gates.
 Explain the difference between an S-R latch and a D latch
 Recognize the difference between a latch and a flip-flop
 Explain how D and J-K flip-flops differ
 Describe the operation of edge-triggered flip-flops.
 Draw the output timing waveforms of several types of flip-flops in response to a
set of input signals.
 Describe the difference between synchronous and asynchronous systems.
 Apply flip-flops in basic applications
2
 Introduction to Sequential Circuits
 Every digital system is likely to have combinational circuits.
 Most systems encountered in practice also include storage elements, which
require that the system be described in terms of sequential logic.
 A Combinational Circuit is a type of circuit in which the output is independent of
time and only relies on the input present at that particular instant.
 A sequential circuit is a type of digital logic circuit whose output not only relies
on the current input but also depends on the previous output.
 It is basically a set of combinational circuits and memory elements connected

in a feedback path.

3
 Introduction to Sequential Circuits

Sequential = Combinational + Memory

 The storage elements are devices capable of storing binary information.

 The binary information stored in these elements at any given time defines the state of the
sequential circuit at that time.
 The sequential circuit receives binary information from external inputs.
 These inputs, together with the present state of the storage elements, determine the binary
value of the outputs.
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 How can a circuit remember?
 Bistable circuits can have two distinct states
 Once they are in one state, they will remain there.

The Loop keeps the state stable

 But how can we move from one state to another?
 We add one switch to break the loop and at the same time add another switch that
connects an input to the circuit.

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 How can a circuit remember?
 The D Latch
 D Latch is the basic bi-stable circuit used in modern CMOS.
 The clock controls the switches. Only one is active at a time.
 Traditionally the input is called D (Data) and the output Q

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 How can a circuit remember?
 The D Latch has two modes
 Latch mode, loop is active, input disconnected, keeps state

 Transparent mode, loop is inactive, input is connected and propagates to output

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 How can a circuit remember?
 Using two transmission gates as switches
 TG1 is used to connect the Data input terminal to point A in the circuit.
 TG2, is used as a switch in the feedback loop that maintains the state of the circuit.

A controlled memory element

 Instead of using the transmission gates, we can construct a similar circuit using ordinary
logic gates. 8
 Basic Latch
 Latch is a type storage device that has two stable states (bistable).
 Latches are useful for storing binary information and for the design of
asynchronous sequential circuits.
 They are not practical for use in synchronous sequential circuits
 The most basic latch circuit can be constructed from either two NAND gates or
two NOR gates.
Set(S) Q
Reset(R) Q

Reset(R) Q
Q
Set(S)

a) NOR gate latch: Active HIGH inputs b) NAND gate latch: Active LOW inputs
9
 Basic Latch
 The gate outputs, labeled Q and Q, respectively, are the latch outputs.
 Under normal conditions, these outputs will always be the inverse of each other.
 There are two latch inputs:
 The SET input is the input that sets Q to the 1 state
 the RESET input is the input that resets Q to the 0 state.
 Under normal conditions, both inputs of the NAND latch remain at 0 unless the state has to
be changed.
 There are two equally likely output states when SET = RESET = 1
 The one that actually exists will depend on what has occurred previously at the inputs.
S 1 1 Q S 1 0 Q

0 1
R 1 Q R 1 Q
10
(a) When previous Q = 1 (b) When previous Q = 0
 Basic Latch
 Normal conditions for NOR Latch
 Both inputs of the NOR latch remain at 0 unless the state has to be changed.
 There are two equally likely output states when SET = RESET = 0
 The one that actually exists will depend on what has occurred previously at the inputs.

R 0 1 Q R 0 0 Q

0 Q 1 Q
S 0 S 0

(a) When previous Q = 1 (b) When previous Q = 0

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 Setting NAND Latch
 Pulsing the SET input to the 0 state

S
S
Q Q

R 1 Q R 1 Q

Outputs make transitions when S No transitions occur because

goes LOW and remain in same latch is already SET.
state after S goes back HIGH.

(a) Q = 0 prior to SET pulse; (b) Q = 1 prior to SET pulse

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 Setting NOR Latch
 Pulsing the SET input to the 1 state
0
0 R
R Q Q

Q S
Q
S

Outputs make transitions when S

No transitions occur because
goes HIGH and remain in same
latch is already SET.
state after S goes back HIGH.

(a) Q = 0 prior to SET pulse; (b) Q = 1 prior to SET pulse

13
 Resetting NAND Latch
 Pulsing the REST input to the 0 state

1 S 1
S
Q Q

Q R Q
R

Outputs make transitions when R

No transitions occur because goes LOW and remain in same
latch is already RESET. state after S goes back HIGH.

(a) Q = 0 prior to RESET pulse; (b) Q = 1 prior to RESET pulse

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 Resetting NOR Latch
 Pulsing the SET input to the 1 state

R R Q
Q

0 Q S
0 Q
S

Outputs make transitions when R

No transitions occur because goes HIGH and remain in same
latch is already RESET. state after S goes back HIGH.

(a) Q = 0 prior to Reset pulse; (b) Q = 1 prior to Reset pulse

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 Simultaneous Setting and resetting
 Simultaneously pulsing LOW the SET and RESET input for NAND Latch.
 This violates the requirement that outputs be the complement of each other.
 Produce HIGH levels at both NAND outputs so that Q = Q = 1
 This action produces an undefined next state.
 The state that results from the input transitions depends on the order in which they
return to 0.
 For these reasons the SET = RESET = 0 condition is normally not used for the
NAND latch.
 This condition is avoided by making sure that 0’s are not applied to both inputs
simultaneously.

 What about for NOR Latch?

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 Summary of basic Latch
 Summary for NAND Latch.
1. SET = RESET = 1. This has no effect on the output state.
 The outputs will remain in whatever state they were in prior to this input condition.
2. SET = 0, RESET = 1. This will always cause the output to go to the Q = 1 state.
 This state will remain even after SET returns HIGH.
3. SET = 1, RESET = 0. This will always produce the Q = 0 state.
 The output will remain even after RESET returns HIGH.
4. SET = RESET = 0. This condition tries to set and clear the latch at the same time(Q = Q = 1)
 If the inputs are returned to 1 simultaneously, the resulting state is unpredictable.
 This input condition should not be used.

 What about for NOR Latch?

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 Summary of basic Latch
S Q

R Q

(c) simplified block symbol

(a) NAND gate latch; (b) function table;

R Q

Q
S
(e) function table; (f) simplified block symbol 18
(d) NOR gate latch;
 Summary of basic Latch
S Q

R Q

(a) NAND gate latch;

R Q

Q
S
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(b) NOR gate latch;
 Summary of basic Latch
 Example: If the S and R waveforms in the figure below are applied to the inputs
of the NAND latch, determine the waveform that will be observed on the Q
output. Assume that Q is initially LOW.

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 Summary of basic Latch
 Solution

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 Drawback of SR Latch
1. It has no control and clock input: Sensitive to any input changes
 It changes its state in response to changes in the signals on these inputs.
 NAND Latch circuit responds any time the inputs are LOW.
 NOR Latch circuit responds any time the inputs are HIGH.
 The state changes occur at the time when the changes in the signals occur.
 We cannot control the time of such changes.
 We don’t know when the latch may change its state
2. It has Race condition:
 When output of the latch becomes unstable it is known as a race condition.
 Has indeterminate (invalid) state.
 NAND Latch circuit.
 When the S and R inputs of an SR are at logical 0
 NOR Latch circuit
 When the S and R inputs of an SR are at logical 1 22
 Gated SR Latch
 The operation of the basic SR latch can be modified by providing an additional
input signal that determines (controls) when the state of the latch can be changed
by determining whether S and R can affect the circuit.
 The control input C acts as an enable signal for the other two inputs.
 Whenever the control signal is 0:
 The outputs of the NAND gates stay at the logic-1 level (SC = S and RC = R; since C =0)
 The output of the AND gate stay at logic-0. (SC = 0 and RC = 0; since C =0)

S S
R R
Q Q

C C
S Q R Q
S R
a) Gated NOR Latch c) Graphical Symbol 23
b) Gated NAND Latch
 Gated SR Latch
S S
Q
C
R Q
R

C S R Q
0 X X Hold →No change
1 0 0 Hold →No change
1 0 1 Q= 0 → Reset
1 1 0 Q= 1→ Set
1 1 1 Q=Q → Invalid 24
 D Latch
 D Latch
 One way to eliminate the undesirable (Race) condition of the indeterminate state
in the SR latch is to ensure that inputs S and R are never equal at the same time.
 D latch has two inputs
 D (data) - directly goes to the S input and its complement is applied to the R input.
 C (control)
 As long as the control(C) input is at 0, SR latch has both inputs at the 1 level
and the circuit cannot change state regardless of the value of D.
 The D input is sampled when C = 1.
 If D = 1, the Q output goes to 1 => placing the circuit in the set state
 If D = 0, output Q goes to 0 => placing the circuit in the reset state
 This circuit is often called transparent latch.
 The output follow changes in the data input as long as the control input is enabled.
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 D Latch
D S
Q
D Q
C
R Q C Q

b) Graphical Symbol
a) D-latch Circuit
C

D
C D Q
0 X HOLD→ No change
Q
1 0 Q = 0 →Reset
1 1 Q = 1 →Set t
Output may change
c) Characteristic table d) Timing diagram
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 FLIP–FLOPS
 Flip–flops are constructed in such a way to make D latches operate properly
when they are part of a sequential circuit that employs a common clock.
 The problem with the latch is that
 It responds to a change in the level of a clock pulse.
 Positive level response in the control input allows changes, in the output
when the D input changes while the control pulse stays at logic 1.
 The key to the proper operation of a flip–flop is
 To trigger it only during a signal transition.

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 FLIP–FLOPS
 Controlled latches are level sensitive– triggered
level

 Flip-Flops are edge –triggered

edge

Positive Edge
CLK

Negative Edge
CLK
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 FLIP–FLOPS
 There are two ways that a latch can be modified to form a flip–flop.
1. Employ two latches in a special configuration that
 isolates the output of the flip–flop from being affected while its input is
changing.
2. Produce a flip–flop that triggers only during a signal transition.
 From 0 to 1 or from 1 to 0 only.
 Disabled during the rest of the clock pulse duration.

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 Master–Slave D flip–flops
QM QS
D D D Latch D
D Latch
(M aster) (Slave)
C C

CLK

M aster Slave

CLK

Looks like it is negative D

edge-triggered
QMaster
QSlave

 The output of the master-slave D flip-flop (QS)responds on the negative edge of the clock signal.
 The circuit can be changed to respond to the positive clock edge by connecting the slave stage directly to the
clock and the master stage to the complement of the clock. 30
 Edge-Triggered D Flip-Flop
 A different circuit that accomplishes the same task as master-slave
 It requires only six NAND gates and, hence, fewer transistors.

• Two latches respond to the external D (data) and

CLK (clock inputs).
• Third latch provides the outputs for the flip-flop.

a) Circuit a) Graphical Symbol 31

Edge-Triggered D Flip-Flop
 Operation of the Circuit

I. When Clock = 0, S = R = 1
• Output = present state
• At the same time, P1 = D, and P2 = D
II. When Clock changes to 1 (0 1)
• The values of P1 and P2 are transmitted through
gates 2 and 3 to cause S = D and P2 = D
• Q = D and Q = D
III. If CLK = 1
• Any further changes in D will not affect the output
latch as long as Clock = 1
• Flip–flop is locked out
• Unresponsive to further changes in the input.
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Edge-Triggered D Flip-Flop
 Operation of the Circuit

III. If CLK = 1
1. If D = 0 at the positive edge of the clock.
• Then R = 0, which will keep the output of gate 4
equal to 1 as long as Clock = 1, regardless of the
value of the D input.
2. The second case is if D = 1 at the positive edge of
the clock. Then S = 0, which forces the outputs of
gates 1 and 3 to be equal to 1, regardless of the D
input.

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 Edge-Triggered D Flip-Flop
 When CLK in the positive-edge-triggered flip–flop
1. Makes positive transition (0→1)
 The value of D is transferred to Q.
2. Makes negative transition (1→0)
 Does not affect the output. Positive-edge-triggered flip–flop
3. Steady CLK 1 or 0
 Does not affect the output.

 What about negative-edge-triggered flip–flop?

Negative-edge-triggered flip–flop
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 Types of Flip-Flop
 Four common flip-flops
 SR Set/reset
 JK Set/reset/toggle
 D Data or delay
 T Toggle
 The most economical and efficient flip–flop constructed is the edge–triggered D
flip–flop.
 It requires smallest number of gates.
 Other types of flip–flops can be constructed by using the D flip–flop and external logic.
 There are three operations that can be performed with a flip–flop:
 Set it to 1
 Reset it to 0
 Complement(toggle) its output 35
 JK Flip–Flop
 JK flip-flop behaves as the SR flip-flop, where J = S and K = R, for all input
values except J = K = 1.
 For the case J = K = 1 the JK flip-flop toggles its state
 It performs all three operations

b) Graphical symbol c) (b) Characteristic table

a) Circuit
36
 T Flip–Flop
 The T(toggle) flip-flop is a complementing flip-flop and can be obtained from a
JK flip-flop when inputs J and K are tied together.
 The T flip flop has only toggle and hold operations.
 In the toggle mode output will be complemented from 1 to 0 and vice versa.

b) Graphical symbol c) Characteristic table

a) Circuit 37
 T Flip–Flop
 The T flip flop has only toggle and hold operations.
 In the toggle mode output will be complemented from 1 to 0 and vice versa.
Flip-Flop Characteristic Tables
D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q 1 Q(t) Toggle 39
Flip-Flop Characteristic Equations
D Q D Q(t+1)
0 0 Reset Q(t+1) = D
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q(t) Toggle

T Q T Q(t+1)
Q(t+1) = T  Q
0 Q(t) No change
Q 1 Q(t) Toggle 40
 Flip-Flop Characteristic Equations
 Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0
No change
J Q 0 0 1 1
0 1 0 0 Reset
Q
0 1 1 0
K
1 0 0 1
Set
1 0 1 1
1 1 0 1
Toggle
1 1 1 0

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 Common Applications of a flip-flop
1. It can be used as one bit to multiple bit memory elements.
 Cascade of two flip-flops is a 2 bit memory element and for n cascaded flip-flops, it is n
element memory.
2. It is used in the architecture section of a computer as
a) an accumulator in (conjunction with) an adder to store and update data when clocked,
b) a status indicator,
c) a storage buffer for a computer input/output system.
3. It can be used for alphanumeric display (to display alphabets or numerals, which can be stored
in the flip-flop output and displayed accordingly).
4. It can be used for various types of registers such as shift register,
 e.g., SIS0, SIPO, PISO, PIPO, and bidirectional shift register
5. It can be used in different types of counter applications.
6. It can be used as a simple divided by N circuit or frequency divider.
7. It is used for the design of sequence generator.
42
8. It is used for error detection and data conversion
 Summary of Flip-flops
 Basic latch is a feedback connection of two NOR gates or two NAND gates,
which can store one bit of information.
 It can be set to 1 using the S input and reset to 0 using the R input
 Gated latch is a basic latch that includes input gating and a control input signal.
 The latch retains its existing state when the control input is equal to 0.
 Its state may be changed when the control signal is equal to 1.
 Flip-flop is a storage element based on the gated latch principle, which can have
its output state changed only on the edge of the controlling clock signal.
 Master-slave flip-flop is built with two gated latches. The master stage is active during half
of the clock cycle, and the slave stage is active during the other half.
 The output value of the flip-flop changes on the edge of the clock that activates the
transfer into the slave stage.
 Edge-triggered flip-flop is affected only by the input values present when the active edge of
the clock occurs. 43
 Registers
 The flip-flops are essential component in clocked sequential circuits.
 Circuits that include flip-flops are usually classified by the function they perform.
 Two of such circuits are registers and counters.

 A register is a group of flip‐flops, each one of which shares a common clock and
is capable of storing one bit of information.
 An n‐bit register consists of a group of n flip‐flops capable of storing n bits of

binary information.
 In addition to the flip‐flops, a register may have combinational gates that

perform certain data‐processing tasks

 The gates determine how the information is transferred into the register

44
 Registers
 A register has two basic functions:
1. Data storage
 The storage capability of a register makes it an important type of memory
device
 The storage capacity of a register is the total number of bits (1s and 0s) of digital
data it can retain.
2. Data movement
 The shift capability of a register permits the movement of data from stage
to stage within the register or into or out of the register upon application of
clock pulse.
 Each stage (flip-flop) in a shift register represents one bit of storage capacity.

45
 Shift Register
A shift register is a digital device used for storage and transfer of data.
 It is a register that provides the ability to shift its contents.
 Basic data movement in shift registers

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 Types of Shift Register Data I/Os
 The shift register forms an important link between the main digital system and
the input/output channels.
 In computer systems it is often necessary to transfer n-bit data items.
 Parallel transfer: transmit all bits at once using n separate wires.
 All the bits of the register are transferred at the same time.
 Serial transfer: transfer all bits using a single wire, by performing the transfer
one bit at a time, in n consecutive clock cycles.
 Information is transferred one bit at a time by shifting the bits out of the source register
and into the destination register.
 Based on the method used to load data onto and read data from shift registers,
they are classified as
 Serial in-serial out (SISO)
 Serial in-parallel out (SIPO)
 Parallel in-serial out (PISO)
47
 Parallel in-parallel out (PIPO)
 Serial In-Serial Out Shift Registers
 The serial in/serial out shift register accepts data serially—that is, one bit at a
time on a single line.
 It produces the stored information on its output also in serial form

Contents of 4-bit SISO shift register for the 1st 4

A 4-bit SISO shift register Logic diagram clock cycle

48
 Serial In-Serial Out Shift Registers

Logic diagram

Timing waveforms 49
 Serial In-Serial Out Shift Registers
 Show the states of the 5-bit register in Figure below for the specified data input
and clock waveforms. Assume that the register is initially cleared (all 0s).

50
 Serial In-Serial Out Shift Registers
 The first data bit (1) is entered into the register on the first clock pulse and then shifted from left to
right as the remaining bits are entered and shifted. The register contains
Q4Q3Q2Q1Q0 = 11010 after five clock pulses

51
 Serial In-Parallel Out Shift Registers
 Data bits are entered serially (least-significant bit first) into a serial in/parallel out shift register
 Once the data are stored, each bit appears on its respective output line, and all bits are
available simultaneously

A 4-bit serial in-parallel out shift register Logic diagram Timing waveforms for the shift register

52
 Parallel In-Serial Out Shift Registers
 The bits are entered simultaneously into their respective stages on parallel lines.
 The serial output is the same as in serial in-serial out shift registers, once the data are
completely stored in the register.

4-bit parallel in-serial out shift register 53

 Parallel In-Parallel Out Shift Registers
 The bits are entered simultaneously into their respective stages on parallel lines.
 Immediately following the simultaneous entry of all data bits, the bits appear on the parallel
outputs.

54
4-bit parallel in-parallel out shift register
Parallel-access shift register

55
 Counters
 Counter is a sequential device which can count the number of clock pulses
applied at its input or which can remember the number of clock pulse applied at
its input.
 On the second basis, counters can also be considered as a memory device.
 It is a register that goes through a prescribed sequence of states upon the
application of input pulses.
 Counters are available in two categories:
1. Asynchronous (ripple) counters:
 A flip‐flop output transition serves as a source for triggering other flip‐flops.
 The CLK input of some or all flip‐flops are triggered, not by the common clock pulses,
but rather by the transition that occurs in other flip‐flop outputs.
2. Synchronous counters
 The CLK inputs of all flip‐flops receive the common clock. 56
 Binary Ripple Counter
 A binary ripple counter consists of a series connection of complementing
flip‐flops, with the output of each flip‐flop connected to the clk input of the next
higher order flip‐flop.
 The flip‐flop holding the least significant bit receives the incoming count pulses.
 A complementing flip‐flop can be obtained from a JK flip‐flop with the J and K
inputs tied together or from a T flip‐flop.
 The other possibility is to use a D flip‐flop with the complement output
connected to the D input.
 The D input is always the complement of the present state, and the next clock pulse will
cause the flip‐flop to complement

57
 Binary Ripple Up Counter
1
1
Q0 Q1 Q2 Q3

T Q T Q T Q T Q

CLK

 This is a 4-bit ripple counter, which is an asynchronous circuit.

 Timing isn’t quite synchronized with the rising clock pulse
 hard to know when output is ready.
 Cheap to implement, but unreliable for timing.

58
 Binary Ripple Up Counter
 Timing diagram
 Note how propagation delay increases for later Qs

CLK

0 1 0 1 0 1 0 1 0
Q0 0 1 1 0

0 0 1 1 0 0 1 1 0 0 11
Q1 0

Q2 0 0 0 0 1 1 1 1 0 0 0 1 0

Q3 0 0 0 0 0 0 0 0 1 1 1 1 1

Count 0 1 2 3 4 5 6 7 8 9 10 11 12
59
 Binary Ripple Dawn Counter
 Down-Counter with T Flip-Flops

(a) Circuit

(b) Timing diagram

60
 Up–Down Binary Counter
 Down-Counter with T Flip-Flops

61
 Synchronous counters
 Synchronous counters are different from ripple counters in that clock pulses are
applied to the inputs of all flip‐flops.
 A common clock triggers all flip‐flops simultaneously, rather than one at a time in
succession as in a ripple counter.
 In a synchronous binary counter, the flip‐flop in the least significant position is
complemented with every pulse.
 A flip‐flop in any other position is complemented when all the bits in the lower significant
positions are equal to 1.

62
 Synchronous counters
 A four-bit synchronous binary up-counter.

63
 Synchronous counters
 Enable and Clear Capability
 The previous counter change their contents in response to each clock pulse.
 Often it is desirable to be able to inhibit counting, so that the count remains in
its present state.
 This may be accomplished by including an Enable control signal.
 In many applications it is also necessary to start with the count equal to zero.
 This can be achieved by driving the flip-flop with Clear control input

The counter counts the clock pulses only if Enable = 1 64

 Synchronous counters
 Synchronous Counter with D Flip-Flops
 While the toggle feature makes T flip-flops a natural choice for the
implementation of counters, it is also possible to build counters using other
types of flip-flops.
 The JK flip-flops can be used in exactly the same way as the T flip-flops.
 When the J and K inputs are tied together, a JK flip-flop becomes a T flip-flop.
 Implement the counter with D flip-flop is not strait forward.
 It is not obvious how D flip-flops can be used to implement a counter.
 We will present a formal method for deriving such circuits in the next lecture.
 Here we will present a circuit structure that meets the requirements.

65
 Synchronous counters
 Synchronous Counter with D Flip-Flops

For a larger counter the ith stage is defined by

66
 Other Types of Counters
 BCD Counter
 Ring Counter In the next lecture
 Johnson Counter
 Modulus of a Counter

67
68