Microprocessors

INSTRUMENTATIOIN ENGINEERING-B.Tech. 5TH SEM

-Dr. Ujjwal Manikya Nath

Assistant Professor, Jorhat Engineering College
Microprocessor

• Architecture
• Interfacing
Hardware • Designing

• Instruction sets
• Coding
Software • Interfacing between
hardware and software

2
Content
 Microprocessor
 Intel 8085

 Interfacing
 Peripheral device 8255
 8254 timer
 8259 programmable interrupt controller
 8279 programmable keyboard/display interface

3
General example

4
Basic block diagram of Microprocessor

5
Microprocessor

6
Intel 8085

7
Features of 8085
The salient features of 8085 μp are :

 It is a 8 bit microprocessor.

 It is manufactured with N-MOS technology.

 It has 16 bit address bus and hence can address upto 216 = 65536 bytes
(64KB) memory locations through A0-A15.
 21 (2), 22 (4), 23 (8), 24 (16), 25 (32),….

 The first 8 lines of address bus (low-order address lines) and 8 lines of data
bus are multiplexed AD0 – AD7.

8
Features of 8085
 Data bus is a group of 8 lines D0 – D7.

 It supports external interrupt request.

 A 16 bit program counter (PC)

 A 16 bit stack pointer (SP)

 Six 8-bit general purpose register arranged in pairs: BC, DE, HL.

 8085 operates at 3 MHz clock frequency

 8085 A2 operates 5 MHz clock frequency

 It is enclosed with 40 pins DIP ( Dual in line package).

9
Address and Data in memory

…
Data
8000 H 02 H
[8000 H] = 02 H
Address 8001 H AE H

8002 H 36 H [8002 H] = 36 H

……….

8100 H F9 H [8100 H] = F9 H
…

10
 Register of 8085
Special purpose reg (8 bit)

Accumulator (A) 8 bit Flag 8 bit

B 8 bit C 8 bit

D 8 bit E 8 bit General purpose regs

8 bit
H 8 bit L 8 bit

Program Counter (PC) 16 bit

Stack pointer (SP) 16 bit

Reg. pairs: BC, DE, HL (16 bit)

Temporary Reg. : W, and Z D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
11
Flag register

D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY

Z Zero Set to 1 when the result is zero; otherwise it is reset

CY Carry Set to 1 if an arithmetical operation results in a carry
S Sign Set to 1 if D7 = 1
P Parity Set to 1 if Even number of 1s.
AC Auxiliary carry When carry is generated by digit D3

12
 Addition
Nibble Nibble
D7 D6 D5 D4 D3 D2 D1 D0
95 H = 1 0 0 1 0 1 0 1

+ D7 D6 D5 D4 D3 D2 D1 D0
30 H = 0 0 1 1 0 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0
[A] = 1 1 0 0 0 1 0 1 = C5 H

Flag
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
0 0 0 1 0

13
 Subtraction
[A] = ? and status of Flag register ?
D7 D6 D5 D4 D3 D2 D1 D0
01 H = 0 0 0 0 0 0 0 1

- D7 D6 D5 D4 D3 D2 D1 D0
0F H = 0 0 0 0 1 1 1 1

D7 D6 D5 D4 D3 D2 D1 D0
[A] = 0 0 0 0 1 1 1 0 = 0E H

Flag
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
0 0 0 0 0

14
Subtraction (A-B)
Convert ‘A’ to binary

Convert ‘B’ to 2s complement

R= (A)2 + 2s complement of ‘B’

If ‘R’ has Cy=1, ‘R’ is the actual result and Sign

flag (S) =0 (+ve)

If ‘R’ has Cy=0, actual result is

2s complement of ‘R’ and Sign flag (S) =1 (-ve)

15
 Subtraction
[A] = ? and status of Flag register ?
D7 D6 D5 D4 D3 D2 D1 D0
05 H = 0 0 0 0 0 1 0 1

- D7 D6 D5 D4 D3 D2 D1 D0
06 H = 0 0 0 0 0 1 1 0

D7 D6 D5 D4 D3 D2 D1 D0
[A] = 0 0 0 0 0 0 0 0

Flag
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY

16
Block diagram of 8085 microprocessor kit

Clock

Peripheral
8 devices
0
8
Memory 5 I/O

17
Real-time snapshoot of 8085 kit

18
 Basic block diagram of Microprocessor

Store data into the memory -> Write Data memory

Fetch data from memory -> Read

Program memory

19
Microprocessor initiated operations and Bus
organization

Address bus

Real World
Input
8
Memory
0
8 Output

5
Data bus

Control bus

20
M/I/O operations

 Memory read: Read data (or instructions) from memory

 Memory write: Writes data (or instructions) into memory

 I/O read: Accepts data from input devices

 I/O write: Sends data to output devices

21
Pin diagram of 8085

22
Signals of 8085

23
Signals of 8085
 Control and status signals

ALE, RD , WR , IO / M , S1 and S0

 Interrupts

INTR, INTA, RST7.5, RST6.5, RST5.5, TRAP, HOLD, HLDA,

READY

24
Block diagram of de multiplexing

(21-28)

(30)
Enable
(12-19)

Disable

ALE = Address Latch Enable

25
74LS373 D type latch

Tri-state

OUTPUT
buffer
INPUT

Latch

Active high =1
Active low = 0
26
De multiplexing the bus AD0-AD7

27
Memory read operation
= 35 H Data bus
Memory

A Flag B C 8002 H
Instruction
D E 0 0 1 1 0 1 0 1
ALU Decoder
= 35 H
H L

Address bus
SP
Control
Unit PC
= 8002 H

Control signals

8085 Microprocessor MEMR

28
 Timing diagram of data flow (Opcode fetch)
T1 T2 T3 T4

CLK

28 A15
21 A Higher-order memory address (80 H) Unspecified
8

Low-order
19 AD7
12 AD0
02 H Data (35 H)
memory address

30 ALE

IO / M
34

RD
32

29
 Operating frequency (f) of 8085 = 3MHz

1 1 −6
T= = = 0. 333  10
f 3  10 6
0.333 micro sec

T- state

4 T-states (T1, T2, T3 and T4)

Time required to execute the four T-states

4  0.333  10 −6 sec

30
Memory size
20 = 1 28= 256

A0 21 = 2 29= 512 A8

210= 1,024 (1 Kb) A9

A1 22 = 4
211= 2,048 A10
23 = 8
212= 4,096
24= 16
213= 8,192
25= 32
214= 16,384
26= 64
215= 32,768 A14
27= 128 216= 65,536 (64 Kb) A15

31
Problem 1

Design a interfacing circuit where NAND is being used to select

ഥ signals of the
the static memory 1024 byte. 𝑊𝑅 and 𝐼𝑂/𝑀

8085 are being used to generate 𝑀𝐸𝑀𝑅 control signal.

Also identify the memory allocation of the developed diagram.

32
 1
1

Problem 1 1 0
MEMR
IO / M
1

1 0 0
1
RD
A15
1 CS OE
A14

8 A10
E
A9

0
A9
A8
P
1024X 8

8
A7
R
5 A2
A1
O 1 byte = 8 bit

A1
A0
M
A0

33 Data Bus
 Address range for 1024 x 8
Starting
A 15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
= FC00 H

Ending
A 15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Chip enable
Register select
= FFFF H

Address range: FC00 H – FFFF H

34
Problem 2
Design a interfacing circuit where output line 4 (O4) of 3-to-8 decoder

is used to select the static memory 4Kb (4096 x 8). The address

lines A12 to A14 are connected as input to the decoder, and the lines

A15 is used as active low Enable line. Other two Enable lines (active

low and active high) is permanently enabled by Gnd and +5 V,

respectively.

35
 =0 Gnd Vcc

I2=1 O0
E1 E2 E3 0
O1
I1=0 0
3-to-8 O4
A15
A14 Decoder CS
A13
A12 I0=0 O7 4
8
A11
0
A11
A10
A9
0
A9
A8
A7
9
8 6
5 x
A2
A1
A0
A1
A0
8

36 Data Bus
 Memory range

A 15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

= 4000 H

A 15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1

= 4FFF H

Chip select Register select

= 4000 – 4FFF H
37
Problem 3
Explain the decoding logic and the memory address range of 8155

RAM (256 x 8) interface. The output line 4 (O4) of 3-to-8 decoder is

used to select the memory. The address lines A11 to A13 are

connected as input to the decoder, and the lines A15 and A14 are

used as active low Enable lines. The third Enable line (E3) (active

high) is permanently enabled by +5 V (Vcc). The address lines A10,

A9, and A8 are not connected (don’t care lines).

38
 =0
Vcc (+5 V)
=0
O0
MSB I2=1 E1 E2 E3
Gnd Vcc O1
0
I1=0
3-to-8 O4
A15
A14 Decoder CS
A13
A12 I0=0 O7

8
A11
A10
LSB
A10
2
0
A9
A8
5
8
A7 A7
6
5 x
A1
A2
A1
8
A0 A0

39 Data Bus
 Memory range
A 15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 =2000 H

0 0 1 0 0 1 1 1 1 1 1 1 1
=20FF H
0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 =2100 H
0 0 1 0 0 1 1 1 1 1 1 1 1 =21FF H
0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 =2200 H
0 0 1 0 0 1 1 1 1 1 1 1 1 =22FF H
0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0

0 0 1 0 0 1 1 1 1 1 1 1 1

0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0

0 0 1 0 0 1 1 1 1 1 1 1 1

0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0

Chip select Don’t care Register select

40
IO interfacing
 Design an output interfacing with 8085 microprocessor. The output device

is a common-node seven-segment LED and the device address is F1 H. The

interfacing has been done using 3 to 8 decoder (75LS138), and NAND gate

ഥ signals of the 8085 are being used to generate

(74LS20), 𝑊𝑅 and 𝐼𝑂/𝑀

𝐼𝑂𝑊 control signal.

 Also write the program to display the digit ‘7’ at the seven-segment display.

41
IO interfacing

Data lines D7 D6 D5 D4 D3 D2 D1 D0
Bits X 1 1 1 1 0 0 0 = 78 H
Segments NC G F E D C B A

42
Interrupt
 Assume that you are reading an interesting novel at your desk, where there is a
telephone.
1. The telephone system should be enabled.
2. You should glance at the light at certain intervals to check whether someone is calling.
3. If you see a blinking light, you should pick up the receiver, say hello, and wait for a
response.
4. Assume that the caller is you roommate. ‘it is going to rain today. Will you shut all the
window in my room?’
5. You insert a bookmark on the page.
6. You shut your roommate’s window.
7. You replace the receiver on the hook.
8. You go bank to your book, find your mark, and start reading again.

43
Interrupt
Step 1 EI (Enable Interrupt), DI (Disable Interrupt)

Step 2 INTR INTA

Step 3 INTR = 1,

Step 4 INTA = 0

Step 5 RST (CALL)

Step 6 The task to be performed (service routine)

Step 7 EI

Step 8 RST

44
Interrupting
INTR (Input) Interrupt Request: This is used as a general purpose interrupt

INTA Interrupt Acknowledgement: This is used to acknowledge an interrupt

(Output)

RST 7.5 (Input) Reset Interrupt: These are vectored interrupts that transfer the program

RST 6.5 control to specific memory locations. They have higher priorities than the

RST 5.5 INTR interrupt. Priority order is 7.5, 6.5, and 5.5

TRAP (Input) This is a non maskable interrupt and has the higher priority

HOLD (Input) This signal indicates that a peripheral such as DMA (Direct Memory Access)
control is required the use of the address and data buses.

HLDA (Output) Hold Acknowledgment: This signal acknowledges the HOLD request

READY (Input) This signal is used to delay the microprocessor Read or Write cycles until a
slow responding peripheral is ready to send or accept data

45
Interrupts
 Vector interrupt: The interrupt address is known to the process.
RST 7.5, RST 6.5, RST 5.5, TRAP

 Non vector interrupt: The interrupt address is not known to the

process
INTR

 Maskable interrupt: The interrupt is disabled by writing some

instruction into the program.
RST 7.5, RST 6.5, RST 5.5

 Non maskable interrupt: The interrupt can not be disabled.

TRAP

46
Interrupts
Software interrupt Hardware interrupt
8 software interrupt 5 hardware interrupt
RST 0 TRAP (highest priority)
RST 1 RST 7.5
RST 2 RST 6.5
RST 3 RST 5.5
RST 4 INTR (lowest priority)
RST 5
RST 6
RST 7

47
RST (Restart) instructions

48
Multiple interrupts and priorities

I7 has the highest priority

D5 1
D4
D3 1
1

49
 D7 6 5 4 3 2 1 D0
1 1 0 0 0 1 1 1 = C7
0 0 1 = CF
0 1 0 = D7
0 1 1

50
The 8085 interrupts and vector locations

51
SIM (Set Interrupt Mask)

52
RIM (Read Interrupt Mask)

53
Machine cycle status and Control signals
Machine Cycle Status Control signals
IO / M S1 S2

Opcode fetch 0 1 1 RD = 0
Memory read 0 1 0
RD = 0
Memory write 0 0 1
WR = 0
I/O Read 1 1 0
RD = 0
I/O Write 1 0 1
WR = 0
Interrupt Acknowledge 1 1 1
INTA = 0
Halt Z 0 0
Hold Z X X
RD, WR = Z
Reset Z X X
INTA = 1
54
Memory mapped I/O and I/O mapped I/O
 I/O mapped I/O (Peripheral mapped I/O):
In this type of I/O, the MPU uses eight address lines to identify an input or
an output device.
Signal: 𝐼𝑂𝑊 or 𝐼𝑂𝑅

 Memory mapped I/O

In this type of I/O, the MPU uses 16 address lines to identify an input or an
output device.
Instruction: STA
Signal: 𝑀𝐸𝑀𝑅 or 𝑀𝐸𝑊𝑅

55
Microprocessor

• Architecture
• Interfacing
Hardware • Designing

• Instruction sets
• Coding
Software • Interfacing between
hardware and software

56
Instruction sets
An instruction is a command to the microprocessor to perform a given task
on specified data. Each instruction has parts: one is the task to be
performed, called the operation code (op-code), and the second is the data
to be operated on, called the operand. The operand (or data) can be
specified in various ways.

 Op-code + Operand

 1 byte instructions Opcode (8-bit/ 1 byte)

 2 byte instructions Opcode (1 byte) Operand (8-bit/ 1 byte)

 3 byte instructions
Opcode (1 byte) Operand (1 byte) Operand (1 byte)
57
Addressing modes
 The various formats of specifying the operands are called
addressing modes.

1. Immediate addressing- MVI R, Data e.g. MVI D, FE H

2. Register addressing- MOV Rd, Rs e.g. MOV C, D

3. Direct addressing- IN/OUT Port#

4. Indirect addressing- LDAX, STAX

5. Implied addressing- RRC, RLC, CMA

58
Common notations in instruction sets
 The following notations are used in the description of the
instructions:

 R = 8085 8-bit/ 1 byte register (A, B, C, D, E, H, L)

 M = Memory register (location)
 Rs = Register source
 Rd = Register destination (A, B, C, D, E, H, L)
 Rp = Register pair (BC, DE, HL, SP)
 () = Contents of

59
One-byte, two-byte and three-byte
instructions

One-byte instruction: A mnemonic followed by a letter (or two letters)

representing the registers (such as A, B, C, D, E, H, L, M, and SP) is one byte
instruction.
 Examples: MOV A,B; DCX SP; RRC

Two-byte instruction: A mnemonic followed by 8-bit (byte) is a two-byte

instruction.
 Examples: MVI A, 8-bit; ADI 8-bit

Three -byte instructions: A mnemonic followed by 16-bit is a three-byte

instruction.
 Examples: LXI B, 16-bit; JNZ 16-bit

60
Instruction cycle, Machine cycle, and T-state
 Instruction cycle- Instruction cycle is defined as the time required to
complete the execution of an instruction. The 8085 instruction cycle
consists of one to six machine cycles or one to six operations.

 Machine cycle- Machine cycle is defined as the time required to complete

one operation of accessing memory, I/O, or acknowledgement an external
request.The cycle may consist of three to six T-states.

 T-state- T-state is defined as one subdivision of operation performed in one

clock period. These subdivisions are internal states synchronized with the
system clock, and each T-state is precisely equal to one clock period. The
terms T-state and clock period are often used synonymously.

61
 Graphical representation of Instruction cycle, Machine
cycle, and T-state
(Instruction)- Instruction cycle

Machine cycle 1 (Opcode) Machine cycle 2 (operand)

T1 T2 T3 T4 T1 T2 T3

CLK 2 MC
7 T-state

62
Addition and subtraction instructions
ADD ADI ADC ACI

SUB SUI SBB SBI

63
 ADD
Add contents of R/M to contents of accumulator [A]<- [R/M] + [A]

Opcode Operand Bytes M-cycles T-states

ADD Reg. (B, C, D..) 1 1 4
Mem. 1 2 (1+1) 7 (4+3)

64
ADI
 Add immediate to accumulator

 (A) <- (A) + 8 bit data

Opcode Operand Bytes M-cycles T-states

ADI 8-bit data 2 2 7

65
ACI
 Add immediate to accumulator with carry

 (A) <- (A) + 8- bit data + carry (1)

Opcode Operand Bytes M-cycles T-states

ACI 8-bit data 2 2 7

66
ADC
 Add (R/M) to (accumulator) with carry

 (A) <- (A)+ (R/M)+ 1 (carry)

Opcode Operand Bytes M-cycles T-states

ADD Reg. (B, C, D..) 1 1 4
Mem. 1 2 (1+1) 7 (4+3)

67
 Move (MOV)
MOV MOV A, M
(MOV Rd, Rs
MOV M, Rs
MOV Rd, M)
A X F 2050 H A2
Opcode Operand Bytes M-cycles T-states B X X C
2051 H 02
MOV Reg. (B, C, ) 1 1 4 D X X E
2052 H AA
H 20 52 L
Mem. 1 2 (1+1) 7 (4+3)

A X F
MOV B, C B X 98 C
D X X E A AA F 2050 H A2
H X X L B X X C 2051 H 02
D X X E
2052 H AA
A X F H 20 51 L
B 98 98 C
D X X E
68 H X X L
 Move (MVI)
Opcode Operand Bytes M- T-states MVI M, 34 H
cycles
MVI Reg., Data (8-bit) 2 2 7 (4+3)
A X F 2050 H X
Mem. , Data (8-bit) 2 3 10 (7+3) B X X C
(2+1) 2051 H X
D X X E
2052 H X
H 20 50 L
MVI B, 92 H A X F
B X X C
D X X E A X F 2050 H 34
H X X L B X X C 2051 H X
D X X E 2052 H X
H 20 50 L
A X F
B 92 X C
D X X E
H X X L

69
Load (Memory to Register) and
Store (Register to Memory)
LDA LDAX LHLD LXI
(Load Acc. Direct) (Load Acc Indirect) (Load H and L regs. (Load Reg. pair
Direct) Immediate)

STA STAX SHLD

(Store Acc. Direct) (Store Acc Indirect) (Store H and L regs.
Direct)

70
LDA
Load Accumulator Direct Opcode Operand Bytes M-cycles T-states

LDA 16 bit address 3 4 13 (4+3+3+3)

LDA 2050 A X X F
2050 H FF
B X X C
2051 H X
D X X E
H X X L 2052 H X

A FF X F 2050 H FF
B X X C
2051 H X
D X X E
2052 H X
H X X L

71
LDAX
Load Accumulator Indirect Opcode Operand Bytes M-cycles T-states

LDAX B/D reg. 1 2 7 (4+3)

BC
LDAX B A X X F
2050 H FF
B 20 50 C
2051 H X
D X X E
H X X L 2052 H X

A FF X F 2050 H FF
B X X C
2051 H X
D X X E
2052 H X
H X X L

72
LHLD
Load H and L registers Direct Opcode Operand Bytes M-cycles T-states

LHLD 16 bit address 3 5 16

LHLD 2052 H A X X F 2050 H FF

B X X C
2051 H 04
D X X E
PC 2052 H 06
H X X L
PC
2053 H B8

A X X F A X X F
B X X C B X X C
D X X E D X X E
H X 06 L H B8 06 L

73
 LXI
Load Register pair Immediate Opcode Operand Bytes M-cycles T-states

LXI Reg. pair 3 3 10

LXI B, 2050 H LXI D, 20A2 H

A X X F A X X F
B X X C B X X C
D X X E D X X E
H X X L H X X L

A X X F A X X F
B 20 50 C B X X C
D X X E D 20 A2 E
H X X L H X X L

74
Increment or decrement
INR INX
(increment the content of R/M by 1) (increment the content register pair by 1)

DCR DCX
(Decrement the content of R/M by 1) (Decrement the content register pair by
1)

75
INR (increment the content of R/M by 1)
Opcode Operand Bytes M- T-states
cycles
INR Reg. 1 1 4

Mem. 1 3 (2+1) 10

INR C A X F
B X FF C
D 02 X E
H X X L

A X F D7 D6 D5 D4 D3 D2 D1 D0

B X 00 C S Z AC P CY
D 03 X E 0 1 1 0 X
H X X L

76
INR (increment the content of R/M by 1)
Opcode Operand Bytes M- T-states
cycles
INR Reg. 1 1 4 2050 FF

Mem. 1 3 (2+1) 10 2051 X

2052 52
A X F 2053 0A
INR M B X X C
2054 89
D X X E
H 20 54 L
PC

2050 FF
A X F
2051 X
B X X C
2052 52
D X X E
H 20 54 L 2053 0A

PC 2054 8A

77
INX (increment the content register pair by
1)
Opcode Operand Bytes M- T-states
cycles
INX Reg. pair 1 1 6

INX H A X F
B X X C
D X X E
H AF FF L

A X F
B X X C
D X X E
H B0 00 L

78
Logical operation
ANA (logical AND with A) ANI (AND Immediate with A)
S, Z, P are modified S, Z, P are modified
CY is RESET CY is RESET
AC is SET AC is SET

ORA (logical OR with A) ORI (OR Immediate with A)

S, Z, P are modified S, Z, P are modified
AC, CY is RESET AC, CY is RESET

XRA (logical Ex-OR with A) XRI (Ex-OR Immediate with A)

S, Z, P are modified S, Z, P are modified
AC, CY is RESET AC, CY is RESET

79
Rotate
RAL RLC
(rotate accumulator left through carry) (rotate accumulator left without carry)

1 byte 1 byte
1 MC 1 MC
4 Ts 4 Ts

RAR RRC
(rotate accumulator right through carry) (rotate accumulator right without carry)

1 byte 1 byte
1 MC 1 MC
4 Ts 4 Ts

80
RAL
RAL

Flag reg. Accumulator

CY D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 0 0 1 0 0 1

Flag reg. Accumulator

CY D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 1 0 0 1 0

81
RLC
RLC

Flag reg. Accumulator

CY D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 0 0 1 0 0 1

Flag reg. Accumulator

CY D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 1 0 0 1 1

82
Complement
 CMA
Opcode Operand Bytes M-cycles T-states
CMA None 1 1 4

 CMC

Opcode Operand Bytes M-cycles T-states

CMC None 1 1 4

83
Compare
 CMP
Opcode Operand Bytes M-cycles T-states
CMP Reg. (B, C, D..) 1 1 4
Mem. 1 2 (1+1) 7 (4+3)

 If (A)<(R/M): Carry flag set and Zero flag reset

 If (A)=(R/M): Carry flag reset and Zero flag set
 If (A)>(R/M): Carry and Zero flag reset

 CPI
Opcode Operand Bytes M-cycles T-states
CPI 8 bit data 2 2 7

84
 DAA (Decimal Adjust Accumulator)
Opcode Operand Bytes M-cycles T-states
DAA None 1 1 4

 DAD (Add Register Pair to H and L Registers)

Opcode Operand Bytes M-cycles T-states
DAD Reg. pair 1 3 10

DAD D, DAD H, DAD SP,

85
Exchange instructions
 XCHG (Exchange H a L with D and E)
1 byte 1 MC 4 Ts

 XTHL (Exchange H a L with Top of Stack)

1 byte 5 MC 16 Ts

 STC (Set Carry)

1 byte 1 MC 4 Ts
86
CALL (unconditional subroutine call)
 3 byte 5 Mc 18 Ts

 CALL 16-bit address

 CALL 2000

87
 Subroutine call
Main program Subroutine: as an example Delay 1
8000
2000
Red 8001
2001
8002 CALL 2000 2002
8003
2003 RET
8004
PC 8005
8006 8005 Last In First Out (LIFO)
8007
8008
8009 1. SP is decremented by 1
2. MSB is stored FFFD 05
800A
3. SP is decremented by 1 FFFE 80
800B HLT 4. LSB is stored
FFFF

88 Stack
Temporary registers
 W and Z are two 8-bit temporary registers, used to hold 8-bit data/address
during execution of some instructions.

 CALL-RET instructions are used in subroutine operations. On getting a CALL

in the main program, the current program counter content is pushed into
the stack and loads the PC with the first memory location of the
subroutine. The address of the first memory location of the subroutine is
temporarily stored in W and Z registers.

 Again, XCHG instruction exchanges the contents H and L with D and E

respectively. W and Z registers are used for temporary storage of such data.

89
 Delay subroutine call
Main program Subroutine: as an example Delay
8000
2000
Red 8001
2001
8002 CALL 2000 2002
8003
2003 RET
8004
8005
Yellow
8006 CALL 2000
8007
8008

Green 8009
800A CALL 2000
FFFE 0B
PC 800B HLT FFFF 80
SP
90
 Subroutines
Main program Subroutine: as an example Delay 1
8000
2000
Red 8001
2001
8002 CALL 2000 2002
8003
2003 RET
8004
8005
Yellow
8006 CALL 3000 Subroutine: as an example Delay 2
8007 3000
8008 3001
Green 8009 3002
800A CALL 2000 3003 RET
PC 800B HLT

800B
91
 CALL, JMP, RET,
 PUSH, POP
 NOP

92
Nesting

9D
20
FFFD 53
FFFE 20

93
FFFF
JMP (Unconditional Jump)
 3 byte 3 Mc 10Ts

 JMP 16-bit address

 JMP 2000

94
 Jump
Main program Subroutine: as an example Delay 1
8000
2000
Red 8001
2001
8002 JMP 2000 2002
8003
PC 2003 HLT
8004
8005
8006
8007
8008
8009
800A
800B HLT

95
RET (Return from subroutine)
 1 byte 3 Mc 10Ts

 RET

96
NOP (No operation)
 1 byte 1Mc 4Ts

 NOP
 NOP

97
Conditional operations

Call Jump Return

CC JC RC On carry CY = 1
CNC JNC RNC On no carry CY = 0
CP JP RP Positive S=0
CM JM RM Negative S=1
CPE JPE RPE P=1
CPO JPO RPO P=0
CZ JZ RZ Z=1
CNZ JNZ RNZ Z=0

98
99
PUSH (Push (M/R) onto stack)
 1 byte 3Mc 12Ts
 PUSH Reg. Pair 1. SP is decremented by 1
2. MSB is stored 8FFE AF
3. SP is decremented by 1 8FFF 82
 PUSH B 4. LSB is stored
9000

Stack
A XX F A XX F

B 82 AF C B 82 AF C

D X X E D X X E

H X X L H X X L

PC XXXX PC XXXX

SP 9000 SP 8FFE

100
POP (Pop off stack to Reg. Pair)
 1 byte 3 Mc 10Ts
A XX F
B XX XX C
 POP Reg. Pair D X X E
8FFE AF
8FFF 82
H X X L
PC XXXX 9000
 POP D SP 8FFE
Stack

A XX F
B XX XX C
D 82 AF E
H X X L
PC XXXX
SP 9000

101
Internal structure of 8255
(PPI: Programmable Peripheral Interface)

102
8255 chip select logic

0A7 11

0 1
1 1
0 0
0 1

A7 A6 A5 A4 A3 A2 A1 A0 Hex Port
1 0 0 0 0 0 0 0 80 A
1 0 0 0 0 0 0 1 81 B
1 0 82 C

103
1 1 CWR
Pin diagram of 8255

104
Control word register 8255

105
8255 CWR for I/O and BSR mode

106
Interfacing problem 1

 Write an 8085 assembly program to read the key status

and output on to the 8 LEDs. Assume PPI 8255 in mode 0
operation. Where, interface 8 LEDs to the port A of 8255.
Interface 8 keys to the port B. Assume that A15 is
connected with chip select line of 8255.

107
Interfacing problem 2

 Write an 8085 assembly program to read the key status

and output on to the 12 LEDs. Assume PPI 8255 in mode
0 operation. Where, interface 8 LEDs to the port A and 4
LEDs of port C lower (PC0- PC3) of 8255. Interface 8
keys to the port B and 4 keys to port C upper (PC4-
PC7).

108
Interfacing problem 3
 Write a BSR control word subroutine to set bits PC7 and
PC3 and reset them after 10 ms.

0A7 11

0 1
1 1
0 0
0 1

109
Mode- 1: input or output with handshake

 Two ports (A and B) function as 8-bit I/O ports. They can be configured as
either as input or output ports.

 Each port uses three lines from port C as handshake signals. The remaining
two lines of port C can be used for simple I/O functions.

 Input and output data are latched.

 Interrupt logic is supported.

110
Mode- 1 configuration (input) of 8255

111
Model 1: input control signals
 STB: Strobe Input

 IBF: Input Buffer Full

 INTR: Interrupt Request

 INTE: Interrupt Enable

112
Mode- 1 configuration (input) of 8255

1 0 1 1 0 0 1 0
(2)
(4)
1 0 1 1 0 0 1 0 (1)
(3) 1
1 1 1
8
(5)
0 1
1 0 1 1 0 0 1 0
8
5
2

(6)

113
Mode 1
CWR (Input):

D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 X 1 1 X

CWR (Output):

D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 X 1 0 X

114
Mode- 1 configuration (output) of 8255

115
Model 1: output control signals
 OBF: Output Buffer Full

 ACK: Acknowledge

 INTR: Interrupt Request

 INTE: Interrupt Enable

116
Status word for mode 1

117
Mode 2: bidirectional data transfer

 The mode is used primarily in applications such as data transfer between

computers or floppy disk controller interface.

 In this mode, port A can be configured as the bidirectional port and B

either in Mode 0 or Mode 1.

 Port A uses five signals from port C as handshake signals for data transfer.
The remaining three signals from port C can be used either as simple I/O
or as handshake for port B.

118
Mode 2 operation

119
Control word of mode 2

120
Status word for mode 2

121
Programmable Interval Timer 8254 (8253)

122
Programmable Interval Timer 8254 (8253)
 The 8254 is an upgraded version of the 8253, and they are pin-compatible.
The features of these two devices are almost identical except that

 8253 can operate with maximum clock frequency 2 MHz.

 The 8254 can operate with higher clock frequency range. Maximum clock
frequency of 8254 is 8 MHz and 10 MHz for 8254-2

 The 8254 includes a Status Read-Back Command that can latch the count
and the status of the counters.

123
Programmable Interval Timer 8254 (8253)

124
Control word register of 8254

125
Write operation
 To initialize a counter, the following steps are necessary.

1. Write a control word into the control register.

2. Load the low-order byte of a count in the counter register.

3. Load the high-order byte of a count in the counter register.

 With a clock and an appropriate gate signal to one of the counters, the
above steps should start the counter and provide appropriate output
according to the control word.

126
Read operation

127
Read operation
 In some applications, especially in event counters, it is necessary to read the
value of the count in progress.This can be done by either of two methods.

 One method involves reading a count after inhibiting (stopping) the

counter to be read.
In the first method, counting is stopped (or inhibited) by controlling the gate
input or the clock input of the selected counter, and two 1/O read
operations are performed by the MPU. The first 1/O operation reads the
low-order byte, and the second 1/O operation reads the high-order byte.

 The second method involves reading a count while the count is in progress
(known as reading on the fly).
In the second method, an appropriate control word is written into the control
register to latch a count in the output latch, and two I/O Read operations
are performed by the MPU.
128
Read Back command
 The Read-Back Command in the 8254 allows the user to read the count
and the status of the counter; this command is not available in the 8253.
The Read-Back Command eliminates the need of writing separate counter-
latch commands for different counters.

129
Mode of operation of 8254

 Mode 0: Interrupt on terminal count

 Mode 1: Programmable one-short

 Mode 2: Rate generator

 Mode 3: Square wave generator

 Mode 4: Software triggered strobe

 Mode 5: Hardware triggered strobe

130
Mode 0: Interrupt on terminal count

131
Problem-1
 Write a code (program) of 8254 for following statement:
 (i) Identify the port addresses of the control register and
counter 2. Assume that A7 is passed through a NOT gate and
connected with chip select line of 8254.
 (ii) Write a subroutine to initialize counter 2 in Mode 0 with a
count 50,00010. The subroutine should also include reading
counts on the fly; when the count reaches zero, it should
return to the main program.

132
Mode 1: Programmable one-short

133
Mode 2 : Rate generator

134
Problem-2
 Write instructions (program) to generate a pulse every
50 micro sec from Counter 0.

135
Mode 3: Square wave generator

136
Problem-3

 Write instructions to generate a 1 KHz square wave from

Counter 1.

137
Mode 4 : Software triggered strobe

138
Mode 5 : Hardware triggered strobe

139
Internal block diagram of 8279

140
Modes of 8279
 Keyboard section:
 Two-key lockout (1 )
 N-key rollover (1 2 A B)

 Scan section

 Display section

 MPU section

141
References

 Ramesh Gaonkar, Microprocessor Architecture, Programming

and Applications with the 8085, Penram International
Publishing (India) Private Limited, 2009

 Barry B. Brey, Intel Microprocessors Architecture,

Programming, and Interface, Pearson Prentice Hall, New Jersey,
2009.

 S.K. Sen, Understanding 8085/8086 Microprocessors and

Peripheral ICs: Through Questions and Answers, New age
international publishers, 2014.

142