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EoC-1 - Lecture - 10 - Combinational Logic-Part2

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11 views32 pages

EoC-1 - Lecture - 10 - Combinational Logic-Part2

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phanimiriyala4649
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22AIE102

Elements of Computing Systems-1


Combinational Logic (Part 2)

Dr. Lekshmi C. R., Assistant Professor


Center for Computational Engineering and Networking (CEN)
Amrita School of Artificial Intelligence, Coimbatore
Acknowledgment: Prof. Noam Nisan, Prof. Shimon Schocken
Multiplexer (MUX)
• A digital multiplexer is a combinational circuit that selects binary
information from one of many inputs and direct it to single output line

• The selection of a particular line is controlled by a set of selection lines


• In general, there are n data lines and m selection lines
n=2m
• Usually, we denote it as 2m to 1 multiplexer
• Also known as data selector

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R. 2


Implementation of 2-to-1 MUX

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)| CEN|Dr. Lekshmi C. R 3


Gate level logic
S0 D1 D0

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)| CEN|Dr. Lekshmi C. R 4


Chip logic Diagram HDL Description I0=D0,
I1=D1

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)| CEN|Dr. Lekshmi C. R 5


2-to-1 MUX using NAND gates

So ’
D0

So f
D1

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)| CEN|Dr. Lekshmi C. R 6


Implementation of 4-to-1 MUX
Truth table (Compact form)

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)| CEN|Dr. Lekshmi C. R 7


Gate level logic
S1 S0 D0 D1 D2 D3

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)| CEN|Dr. Lekshmi C. R 8


HDL Description

Chip logic Diagram

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)| CEN|Dr. Lekshmi C. R 9


4-to-1 MUX using 2-to-1 MUX
If S0 =0

If S0 =1 

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)| CEN|Dr. Lekshmi C. R 10


HDL code

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 11


8-to-1 MUX using smaller MUX-es


14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 12


Implementation of Logic function using MUX

• Implement an n-variable function using 2n to 1


multiplexer
– Connect the n variables to the select lines
– Connect the truth table output column values to
data inputs

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 13


F(A,B,C)= ∑(1,4,5,6)

0
1
0
0
1 8 to 1 MUX F
1
1
0

A B C

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 14


An Interesting observation
• For n-variable function, how many distinct functions are possible?
• Take our previous example, it is a 3 variable function. The last
column specifies the output function ‘f’, which is 8 (23) bits
23
• So in 8 bits, we can have 28 combinations , ie 2

2n
• So in general, 2 distinct functions are possible

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 15


HACK exercises
• Implement 2-to-1 MUX
• Implement 4-to-1 MUX
• Implement 8-to-1 MUX
• Implement 4-to-1 MUX using 2-to-1 MUX
• Implement 8-to-1 MUX using smaller MUX-es

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 16


Multi-bit multiplexer
and Multi-way multiplexer

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 17


Multi-bit multiplexer
An n-bit multiplexor is exactly the same as the binary multiplexor, except that the two
inputs are each n-bit wide; the selector is a single bit.

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 18


HACK Exercise
• Implement and test the following chip
– Mux4
– Mux16

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 19


Multi-bit multi-way multiplexer
An m-way n-bit multiplexor selects one of m n-bit input buses and outputs it to
a single n-bit output bus. The selection is specified by a set of k control bits,
where k = log2 m.

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 21


HACK exercise
• Implement and test the following chip
– Mux4Way16
– Mux8Way16

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 22


Demultiplexer (DEMUX)
• Works in reverse manner as compared to MUX
• In general, n output lines and m select lines
n=2m
• Usually, we denote it as 1 to 2m demultiplexer
• The selection of specific output line is controlled by the bit values of m
selection lines

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 23


Implementation of 1-to-2 DEMUX
in sel a b
0 0 0 0
0 1 0 0
1 0 1 0
1 1 0 1

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 24


Gate level logic
sel

in
b

Try yourself: Design 1-to-2 DEMUX using NAND gates

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 25


Implementation of 1-to-4 DEMUX
D0
D1
in D2
D3

S1 S0

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 26


Chip logic Diagram
Gate level logic
S1 S0 in
HDL Description

D0

D1

D2

D3

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 27


Multi-Way/Multi-Bit Demultiplexer

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 28


4 way Demultiplexer

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 29


4 way Demultiplexer

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 30


HACK Exercise
• Implement
– 4 way Demultiplexer
– 8 way Demultiplexer

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 31


Thank You

14-Oct-24 22AIE102|EOC-1|B.TECH CSE (AI)|CEN|Dr. Lekshmi C. R 32

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