Memory System Design

Importance in Microprocessor Architecture

Memory system design is crucial for the performance and efficiency of microproc
essor-based systems.
Effective memory hierarchy reduces latency and maximizes data throughput.
Key Concepts:
Speed: Faster access to data enhances overall system performance.
Efficiency: Optimized memory usage leads to better resource management.
Hierarchy: Organizing memory into levels (cache, main memory, secondary stora
ge) balances speed and capacity.
Role in Microprocessor Systems:
Ensures that the CPU can quickly access the most frequently used data.
Minimizes delays caused by slower memory accesses.
Supports the execution of complex instructions and multitasking.
 Cache Memory
Definition:
A small, highspeed memory located close to the CPU. It stores frequently
accessed data and instructions to speed up processing.

Purpose:
Speed Enhancement: Cache memory significantly reduces the time neede
d to access data compared to main memory.
Efficiency: By storing frequently used data and instructions, cache reduces
the need to fetch data from slower memory tiers.
 Levels of Cache
• L1 Cache:
• Location: Closest to the CPU cores.
• Speed: Fastest among cache levels.
• Size: Smallest capacity, typically a few kilobytes (KB).
• Purpose: Holds critical data and instructions for immediate use.
• L2 Cache:
• Location: Between L1 cache and main memory.
• Speed: Slower than L1 but faster than main memory.
• Size: Larger than L1, typically in the range of hundreds of kilobytes (KB) to a few megabytes (MB).
• Purpose: Provides a second level of data storage to bridge the gap between L1 cache and main me
mory.
• L3 Cache:
• Location: Shared among multiple CPU cores.
• Speed: Slower than L2 but faster than main memory.
• Size: Largest among cache levels, typically several megabytes (MB).
• Purpose: Reduces access time for data shared between cores.
A cache line (or cache block) is the smallest unit of data that can be transferred between the cach
e and the main memory. Each cache line contains a fixed number of bytes, typically ranging from
16 to 128 bytes depending on the architecture.
Characteristics of Cache Lines:
Fixed Size: Each cache line has a fixed number of bytes, e.g., 64 bytes.
Storage Unit: The cache stores and transfers data in these fixed-size blocks, improving efficiency.
Tags: Each cache line has an associated tag that identifies the memory address of the data it hold
s.
How Cache Lines Work:
Memory Block: The data from the main memory is divided into blocks matching the size of a cac
he line.
Loading Data: When the CPU requests data, the entire cache line containing that data is loaded i
nto the cache.
Storage: The cache line stores the data along with its tag, which helps quickly identify if the data i
s present in the cache.
Example:
Cache Line Size: 64 bytes.
Memory Block: 64 bytes of data from memory, aligned to 64-byte boundaries.
Tag: Identifies which 64-byte block from memory is stored in the cache line.
Direct Mapping Method: Overview
• Definition: Direct mapping is a cache mapping technique where each
block of main memory maps to exactly one cache line. It’s simple and
fast but can lead to conflicts if multiple memory blocks map to the sa
me cache line.
•
Steps
1.Determine Cache Line:
1. Calculate which cache line a memory block maps to.
2. Formula: Cache Line = (Block Address) modulo (Number of Cache Lines)
2.Fetch Memory Block:
1. Retrieve the memory block from the main memory.
2. Load the block into the calculated cache line.
3.Store Tag:
1. Store the tag (part of the memory address) with the cache line to identify which memory
block is stored there.
4.Access Data:
1. When accessing data, calculate the cache line as in Step 1.
2. Check the tag to verify that the correct block is in the cache.
3. If the tag matches, it’s a cache hit and data is read from the cache.
4. If the tag doesn’t match, it’s a cache miss, and the required block is fetched from the main
memory.
 Example
Memory Blocks(from RAM) : Block addresses 3, 7, and 11. (Generally Address is a big num)
Cache Lines: Suppose there are 8 cache lines.
Mapping:
Block 3: 3 % 8 = 3
Block 7: 7 % 8 = 7
Block 11: 11 % 8 = 3 (conflict with Block 3)
Steps:
Block 3 maps to cache line 3.
Block 7 maps to cache line 7.
Block 11 also maps to cache line 3, causing a conflict with Block 3
Same Modulus Value !!!???!!
• In direct mapping, when two or more memory blocks have the same
modulus value, they map to the same cache line, leading to a conflict
or collision
• Memory Blocks: Block addresses 3, 11, and 19.
• Cache Lines: 8 lines.
• Mapping:
• Block 3: 3 % 8 = 3
• Block 11: 11 % 8 = 3 (conflict with Block 3)
• Block 19: 19 % 8 = 3 (conflict with Blocks 3 and 11)
What Happens in Case of Conflict:
1.Replace the Existing Block:
1. When Block 3 is first loaded, Cache Line 3 holds Block 3.
2. When Block 11 is loaded, it replaces Block 3 in Cache Line 3.
3. When Block 19 is loaded, it replaces Block 11 in Cache Line 3.
2.Handling the Conflict:
1. Only one of these conflicting blocks can be in the cache at a time.
2. This leads to cache misses if the program frequently accesses both blocks that conflict
with each other.
3. Example: If Block 3 is loaded and then Block 11, accessing Block 3 again will cause a mis
s because it has been replaced.
• Direct Mapping Drawbacks:
• High Conflict Rate: Multiple blocks can map to the same cache line, causing fr
equent replacements.
• Cache Misses: Increased cache misses reduce the effectiveness of the cache.
What is Cache Hit and Cache Miss

• Definition: • Definition:
• A cache hit occurs when the data requeste • A cache miss happens when the data requeste
d by the CPU is found in the cache memor d by the CPU is not found in the cache.
y. • This necessitates fetching the data from the m
• This results in a quick data retrieval, enhan ain memory, which is slower.
cing performance. • Context:
• Context: • Example: If memory block 11 is requested but
cache line 3 currently holds memory block 3, t
• Example: If memory block 3 has been load he data is not found in the cache (miss), and th
ed into cache line 3 and the CPU requests e CPU must fetch block 11 from the main mem
data from block 3 again, this request can b ory and load it into cache line 3, replacing bloc
e served directly from the cache. k 3.
• Outcome: Fast access to data without nee • Outcome: Increased access time as data needs
ding to fetch from slower main memory. to be loaded from main memory, leading to a
temporary performance drop.