HEF4521B

24-stage frequency divider and oscillator

Rev. 9 — 19 August 2024 Product data sheet

1. General description
The HEF4521B consists of a chain of 24 toggle flip-flops with an overriding asynchronous master
reset input (MR), and an input circuit that allows three modes of operation. The single inverting
stage (A2 to Y2) functions as: a crystal oscillator, an input buffer for an external oscillator or in
combination with A1 as an RC oscillator. The crystal oscillator operates in Low-power mode when
pins VSS1 and VDD1 are supplied via external resistors.
Each flip-flop divides the frequency of the previous flip-flop by two, consequently the HEF4521B
24
counts up to 2 = 16777216. The counting advances on the HIGH-to-LOW transition of the
18 24
clock (A2). The outputs from each of the last seven stages (2 to 2 ) are available for additional
flexibility.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually
ground). Unused inputs must be connected to VDD, VSS, or another input.

2. Features and benefits

• Wide supply voltage range from 3.0 V to 15.0 V
• CMOS low power dissipation
• High noise immunity
• Low power crystal oscillator operation
• Fully static operation
• 5 V, 10 V, and 15 V parametric ratings
• Standardized symmetrical output characteristics
• Complies with JEDEC standard JESD 13-B
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 °C to +85 °C

3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
HEF4521BT -40 °C to +85 °C SO16 plastic small outline package; 16 leads; SOT109-1
body width 3.9 mm
Nexperia HEF4521B
24-stage frequency divider and oscillator

4. Functional diagram
5 4 2 9

VDD1 Y2 MR A1

A2
6 CP
STAGES 1 to 8
VSS1 CD Q8
3

CP
STAGES 9 to 16
CD Q16

CP
STAGES 17 to 24
CD

Q24 Q18 Q19 Q20 Q21 Q22 Q23 Y1

1 10 11 12 13 14 15 7
001aae708

Fig. 1. Functional diagram

VDD1
VDD

A2 to FFs to logic

VSS
VSS1

Y2 001aae711

Fig. 2. Schematic diagram of clock input circuitry

HEF4521B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 9 — 19 August 2024 2 / 15

Nexperia HEF4521B
24-stage frequency divider and oscillator

MR A1
Y2
Q Q Q Q Q Q Q Q
FF 1 FF 2 FF 3 FF 4 FF 5 FF 6 FF 7 FF 8
A2 T T T T T T T T

VSS1
CD CD CD CD CD CD CD CD

VDD1

Q Q Q Q Q Q Q Q
FF 9 FF 10 FF 11 FF 12 FF 13 FF 14 FF 15 FF 16
T T T T T T T T

CD CD CD CD CD CD CD CD

Q Q Q Q Q Q Q Q
FF 17 FF 18 FF 19 FF 20 FF 21 FF 22 FF 23 FF 24
T T T T T T T T

CD CD CD CD CD CD CD CD

Q24 Q18 Q19 Q20 Q21 Q22 Q23 Y1

001aae710

Fig. 3. Logic diagram

HEF4521B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 9 — 19 August 2024 3 / 15

Nexperia HEF4521B
24-stage frequency divider and oscillator

5. Pinning information

5.1. Pinning

T package
SOT109-1 (SO16)

Q24 1 16 VDD

MR 2 15 Q23

VSS1 3 14 Q22

Y2 4 13 Q21

VDD1 5 12 Q20

A2 6 11 Q19

Y1 7 10 Q18

VSS 8 9 A1

aaa-036980

5.2. Pin description

Table 2. Pin description
Symbol Pin Description
MR 2 master reset input
VSS1 3 ground supply voltage 1
VDD1 5 supply voltage 1
Y1, Y2 7, 4 external oscillator connection
VSS 8 ground supply voltage
A1, A2 9, 6 external oscillator connection
Q18, Q19, Q20, Q21, Q22, Q23, Q24 10, 11, 12, 13, 14, 15, 1 output
VDD 16 supply voltage

6. Count capacity
Table 3. Count capacity
Output Count capacity
18
Q18 2 = 262144
19
Q19 2 = 524288
20
Q20 2 = 1048576
21
Q21 2 = 2097152
22
Q22 2 = 4194304
23
Q23 2 = 8388608
24
Q24 2 = 16777216

HEF4521B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 9 — 19 August 2024 4 / 15

Nexperia HEF4521B
24-stage frequency divider and oscillator

7. Functional test
A test function has been included to reduce the test time required to test all 24 counter stages. This
test function divides the counter into three 8-stage sections by connecting VSS1 to VDD and VDD1 to
VSS. 255 counts are loaded into each of the 8-stage sections in parallel via A2 (connected to Y2).
All flip-flops are now at a HIGH level. The counter is now returned to the normal 24-stage in series
configuration by connecting VSS1 to VSS and VDD1 to VDD. Entering one more pulse into input A2
causes the counter to ripple from an all HIGH state to an all LOW state.

Table 4. Functional test sequence

H = HIGH voltage level; L = LOW voltage level; ↓ = HIGH to LOW transition.
Inputs Control terminals Outputs Remarks
MR A2 Y2 VSS1 VDD1 Q18 to Q24
H L L VDD VSS L Counter is in three 8-stage sections in parallel mode; A2 and Y2
are interconnected (Y2 is now input); counter is reset by MR.
L [1] [1] VDD VSS H
L L L VSS VSS H VSS1 is connected to VSS.
L H L VSS VSS H The input A2 is made HIGH.
L H L VSS VDD H VDD1 is connected to VDD; Y2 is now made floating and
24
becomes an output; the device is now in the 2 mode.
L ↓ VSS VDD L Counter ripples from an all HIGH state to an all LOW state.

[1] 255 pulses are clocked into A2, Y2. The counter advances on the LOW to HIGH transition.

8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage -0.5 +18 V
IIK input clamping current VI < -0.5 V or VI > VDD + 0.5 V - ±10 mA
VI input voltage -0.5 VDD + 0.5 V
IOK output clamping current VO < -0.5 V or VO > VDD + 0.5 V - ±10 mA
II/O input/output current - ±10 mA
IDD supply current to any supply terminal - ±100 mA
Tstg storage temperature -65 +150 °C
Tamb ambient temperature -40 +85 °C
Ptot total power dissipation Tamb -40 °C to +85 °C - 500 mW
P power dissipation per output - 100 mW

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Product data sheet Rev. 9 — 19 August 2024 5 / 15

Nexperia HEF4521B
24-stage frequency divider and oscillator

9. Recommended operating conditions

Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 - 15 V
VI input voltage 0 - VDD V
Tamb ambient temperature in free air -40 - +85 °C
Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V
VDD = 10 V - - 0.5 μs/V
VDD = 15 V - - 0.08 μs/V

10. Static characteristics

Table 7. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Unit
Min Max Min Max Min Max
VIH HIGH-level input voltage |IO| < 1 μA 5V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage |IO| < 1 μA 5V - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
VOH HIGH-level output voltage |IO| < 1 μA 5V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage |IO| < 1 μA 5V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 mA
VO = 4.6 V 5V - -0.52 - -0.44 - -0.36 mA
VO = 9.5 V 10 V - -1.3 - -1.1 - -0.9 mA
VO = 13.5 V 15 V - -3.6 - -3.0 - -2.4 mA
IOL LOW-level output current VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA
II input leakage current 15 V - ±0.3 - ±0.3 - ±1.0 μA
IDD supply current IO = 0 A 5V - 20 - 20 - 150 μA
10 V - 40 - 40 - 300 μA
15 V - 80 - 80 - 600 μA
CI input capacitance - - - - 7.5 - - pF

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Product data sheet Rev. 9 — 19 August 2024 6 / 15

Nexperia HEF4521B
24-stage frequency divider and oscillator

11. Dynamic characteristics

Table 8. Dynamic characteristics
VSS = 0 V; Tamb = 25 °C unless otherwise specified; for test circuit see Fig. 5.
Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit
tPHL HIGH to LOW A2 to Q18; 5V 923 ns + (0.55 ns/pF)CL - 950 1900 ns
propagation delay see Fig. 4 10 V 339 ns + (0.23 ns/pF)CL - 350 700 ns
15 V 212 ns + (0.16 ns/pF)CL - 220 440 ns
Qn to Qn + 1; 5V 13 ns + (0.55 ns/pF)CL - 40 80 ns
see Fig. 4 10 V 4 ns + (0.23 ns/pF)CL - 15 30 ns
15 V 2 ns + (0.16 ns/pF)CL - 10 20 ns
MR to Qn 5V 93 ns + (0.55 ns/pF)CL - 120 240 ns
10 V 44 ns + (0.23 ns/pF)CL - 55 110 ns
15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns
A1 to Y1; 5V 63 ns + (0.55 ns/pF)CL - 90 180 ns
see Fig. 4 10 V 24 ns + (0.23 ns/pF)CL - 35 70 ns
15 V 17 ns + (0.16 ns/pF)CL - 25 50 ns
tPLH LOW to HIGH A2 to Q18; 5V 923 ns + (0.55 ns/pF)CL - 950 1900 ns
propagation delay see Fig. 4 10 V 339 ns + (0.23 ns/pF)CL - 350 700 ns
15 V 212 ns + (0.16 ns/pF)CL - 220 440 ns
Qn to Qn + 1; 5V 13 ns + (0.55 ns/pF)CL - 40 80 ns
see Fig. 4 10 V 4 ns + (0.23 ns/pF)CL - 15 30 ns
15 V 2 ns + (0.16 ns/pF)CL - 10 20 ns
A1 to Y1; 5V 33 ns + (0.55 ns/pF)CL - 60 120 ns
see Fig. 4 10 V 19 ns + (0.23 ns/pF)CL - 30 60 ns
15 V 12 ns + (0.16 ns/pF)CL - 20 40 ns
tt transition time Qn; see Fig. 4 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns
15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns
tW pulse width A2 HIGH; 5V 80 40 - ns
minimum width; 10 V 40 20 - ns
see Fig. 4
15 V 30 15 - ns
MR HIGH; 5V 70 35 - ns
minimum width; 10 V 40 20 - ns
see Fig. 4
15 V 30 15 - ns
trec recovery time MR; see Fig. 4 5V +20 -10 - ns
10 V +15 -5 - ns
15 V 15 0 - ns
fmax maximum frequency A1; see Fig. 4 5V 6 12 - MHz
10 V 12 25 - MHz
15 V 17 35 - MHz

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

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Product data sheet Rev. 9 — 19 August 2024 7 / 15

Nexperia HEF4521B
24-stage frequency divider and oscillator

Table 9. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter VDD Typical formula for PD (μW) where:
2
PD dynamic power 5V PD = 1200 × fi + Σ(fo × CL) × VDD fi = input frequency in MHz,
dissipation 10 V PD = 5100 × fi + Σ(fo × CL) × VDD
2 fo = output frequency in MHz,
2
CL = output load capacitance in pF,
15 V PD = 13050 × fi + Σ(fo × CL) × VDD VDD = supply voltage in V,
Σ(CL × fo) = sum of the outputs.

11.1. Waveforms and test circuit

VI

MR input VM

0V
tW
1/fmax
VI

A2 input VM

0V
trec tW
tPHL tPLH
VOH
90 %
Qn output
10 %
VOL
tt tt
001aae712

a. Pulse widths, maximum frequency, recovery and transition times, and A2 to Qn propagation delays
VI VOH

A1 input VM Qn output VM

0V VOL
tPLH tPHL tPLH tPHL

VOH VOH

Y1 output VM Qn + 1 output VM

VOL VOL
Y1 propagation delays Qn to Qn + 1 propagation delays
001aak015

b. A1 to Y1, MR to Qn, and Qn to Qn + 1 propagation delays

Measurement points are given in Table 10.
The logic levels VOH and VOL are typical output voltage levels that occur with the output load.

Fig. 4. Waveforms showing measurement of dynamic characteristics

Table 10. Measurement points

Supply voltage Input Output
VDD VM VM
5 V to 15 V 0.5VDD 0.5VDD

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Product data sheet Rev. 9 — 19 August 2024 8 / 15

Nexperia HEF4521B
24-stage frequency divider and oscillator

tW
VI
90 % 90 %
negative
pulse VM VM
10 % 10 %
0V
tf tr

tr tf
VI
90 % 90 %
positive
pulse VM VM
10 % 10 %
0V
tW
001aaj781

a. Input waveforms
VDD

VI VO
G DUT

RT CL

001aag182

b. Test circuit
Test data is given in Table 11.
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

Fig. 5. Test circuit for measuring switching times

Table 11. Test data

Supply Input Load
VDD VI tr, tf CL
5 V to 15 V VSS or VDD ≤ 20 ns 50 pF

12. Application information

VDD

Ro 1.8 MΩ R(1)

VDD VDD1

A1 Y1
Y2
Q18
A2
HEF4521B

CS CT

MR Q24

VSS VSS1

R(1)

001aae713

(1) Optional for low power operation.

For typical characteristics of this crystal oscillator, see Table 12.
Fig. 6. Crystal oscillator circuit

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Nexperia HEF4521B
24-stage frequency divider and oscillator

Table 12. Typical characteristics for crystal oscillator

Parameter 500 kHz circuit 50 kHz circuit Unit
Crystal characteristics
Resonance frequency 500 50 kHz
Crystal cut S N -
Equivalent resistance; RS 1 6.2 kΩ
External resistor/capacitor values
Ro 47 750 kΩ
CT 82 82 pF
CS 20 20 pF

001aae715
RTC VDD 102
C
fosc (1)
(kHz)
RS VDD VDD1

A1 Y1 10
Y2 (2)

Q18
A2
HEF4521B

MR Q24

VSS VSS1

10- 1
1 10 102 RTC (kΩ) 103
001aae714 10- 1 1 10 C (nF) 102

VDD = 10 V; The test circuit is shown in Fig. 7.

; , where:
(1) RTC; C = 1 nF; RS » 2 RTC.
f is in Hz, R is in Ω, and C is in F. (2) C; RTC = 56 kΩ; RS = 120 kΩ.

, where:
VIL(max) = maximum input voltage LOW;
II = input leakage current.

Fig. 7. RC oscillator circuit Fig. 8. Oscillator frequency as a function of RTC and C

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Product data sheet Rev. 9 — 19 August 2024 10 / 15

Nexperia HEF4521B
24-stage frequency divider and oscillator

001aae658
12.5
gfs
(mA/V)
10
(1)

7.5
(2)
Rbias

560 kΩ 5 (3)
VDD

0.47 µF 100 µF 2.5

A2 Y2

Vi input output
A io
(f = 1 kHz)
0
VSS 0 5 10 15
001aae820 VDD (V)

gfs = dio/dvi with vo constant (see Fig. 10). Tamb = 25 °C.

s = observed standard deviation.
(1) Average +2s
(2) Average
(3) Average -2s

Fig. 9. Test setup for measuring forward Fig. 10. Typical forward transconductance gfs as a
transconductance function of the supply voltage

001aae716 001aae717
75 20

IDD
gain (mA)
(VO/VI)
15
50
typ
typ
10

25
5

0 0
0 5 10 15 0 5 10 15
VDD (V) VDD (V)

For test setup, see Fig. 13. For test setup, see Fig. 13.
Fig. 11. Voltage gain VO/VI as a function of supply Fig. 12. Supply current as a function of supply voltage
voltage
330 kΩ

A2 Y2
001aae718

Fig. 13. Test setup for measuring the voltage gain and supply current graphs

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Product data sheet Rev. 9 — 19 August 2024 11 / 15

Nexperia HEF4521B
24-stage frequency divider and oscillator

13. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

D E A
X

y HE v M A

16 9

A2
A3 A
A1
pin 1 index
q
Lp

1 8 L

e w M detail X
bp

0 5 mm
scale

Dimensions (inch dimensions are derived from the original mm dimensions)

Unit A A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y θ

max 1.75 0.25 0.51 0.25 10.0 4.0 6.2 1.27 8°

mm nom 0.25 1.27 1.05 0.2 0.25 0.1
min 0.10 1.25 0.31 0.10 9.8 3.8 5.8 0.4 0°
max 0.069 0.010 0.020 0.010 0.394 0.16 0.244 0.05 8°
inches nom 0.01 0.05 0.041 0.008 0.01 0.004
min 0.004 0.049 0.012 0.004 0.386 0.15 0.228 0.016 0°
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. sot109-1_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
03-02-19
SOT109-1 MS-012
23-10-27

Fig. 14. Package outline SOT109-1 (SO16)

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Product data sheet Rev. 9 — 19 August 2024 12 / 15

Nexperia HEF4521B
24-stage frequency divider and oscillator

14. Abbreviations
Table 13. Abbreviations
Acronym Description
ANSI American National Standards Institute
CDM Charged Device Model
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
ESDA ElectroStatic Discharge Association
HBM Human Body Model
JEDEC Joint Electron Device Engineering Council

15. Revision history

Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4521B v.9 20240819 Product data sheet - HEF4521B v.8.1
Modifications: • Section 2: ESD specification updated according to the latest JEDEC standard.
• Fig. 14: Aligned SO package outline drawing to JEDEC MS-012
HEF4521B v.8.1 20231019 Product data sheet - HEF4521B v.7
Modifications: • The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Section 2 updated.
• Section 14 added.
HEF4521B v.7 20160330 Product data sheet - HEF4521B v.6
Modifications: • Type number HEF4521BP (SOT38-4) removed.
HEF4521B v.6 20111121 Product data sheet - HEF4521B v.5
Modifications: • Section Applications removed
• Table 4: added references to Table note [1] and [2]
• Table 7: IOH minimum values changed to maximum
• Fig. 10: space between "2" and "s" removed in figure notes [1] and [3]
HEF4521B v.5 20091105 Product data sheet - HEF4521B v.4
HEF4521B v.4 20090421 Product data sheet - HEF4521B_CNV v.3
HEF4521B_CNV v.3 19950101 Product specification - HEF4521B_CNV v.2
HEF4521B_CNV v.2 19950101 Product specification - -

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Product data sheet Rev. 9 — 19 August 2024 13 / 15

Nexperia HEF4521B
24-stage frequency divider and oscillator
injury, death or severe property or environmental damage. Nexperia and its

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customer (a) shall use the product without Nexperia’s warranty of the
or replacement of any products or rework charges) whether or not such
product for such automotive applications, use and specifications, and (b)
damages are based on tort (including negligence), warranty, breach of
whenever customer uses the product for automotive applications beyond
contract or any other legal theory.
Nexperia’s specifications such use shall be solely at customer’s own risk,
Notwithstanding any damages that customer might incur for any reason and (c) customer fully indemnifies Nexperia for any liability, damages or failed
whatsoever, Nexperia’s aggregate and cumulative liability towards customer product claims resulting from customer design and use of the product for
for the products described herein shall be limited in accordance with the automotive applications beyond Nexperia’s standard warranty and Nexperia’s
Terms and conditions of commercial sale of Nexperia. product specifications.
Right to make changes — Nexperia reserves the right to make changes Translations — A non-English (translated) version of a document is for
to information published in this document, including without limitation reference only. The English version shall prevail in case of any discrepancy
specifications and product descriptions, at any time and without notice. This between the translated and English versions.
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical Notice: All referenced brands, product names, service names and
systems or equipment, nor in applications where failure or malfunction trademarks are the property of their respective owners.
of an Nexperia product can reasonably be expected to result in personal

HEF4521B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 9 — 19 August 2024 14 / 15

Nexperia HEF4521B
24-stage frequency divider and oscillator

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................4
5.1. Pinning.........................................................................4
5.2. Pin description............................................................. 4
6. Count capacity..............................................................4
7. Functional test.............................................................. 5
8. Limiting values............................................................. 5
9. Recommended operating conditions..........................6
10. Static characteristics..................................................6
11. Dynamic characteristics.............................................7
11.1. Waveforms and test circuit........................................ 8
12. Application information............................................. 9
13. Package outline........................................................ 12
14. Abbreviations............................................................ 13
15. Revision history........................................................13
16. Legal information......................................................14

© Nexperia B.V. 2024. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: [email protected]
Date of release: 19 August 2024

HEF4521B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 9 — 19 August 2024 15 / 15